LT4430

LT4430ES6 LINER

Document overview

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Technical content

The LT ®4430 drives the optocoupler that crosses the galvanic barrier in an isolated power supply. The IC con- tains a precision-trimmed reference, a high bandwidth error amplifi er, an inverting gain of 6 stage to drive the optocoupler and unique overshoot control circuitry. The LT4430’s 600mV reference provides ±0.75% initial accuracy and ±1.25% tolerance over temperature. A high bandwidth 9MHz error amplifi er permits simple frequency compensation and negligible phase shift at typical loop crossover frequencies. The optocoupler driver provides 10mA of output current and is short-circuit protected. A unique overshoot control function prevents output overshoot on startup and short-circuit recovery with a single capacitor. The LT4430 is available in the low profi le 6-lead SOT-23 package. ■ 48V Input Isolated DC/DC Converters ■ Isolated Telecommunication Power Systems ■ Distributed Power Step-Down Converters ■ Offl ine Isolated Power Supplies ■ Industrial Control Systems ■ Automotive and Heavy Equipment ■ 600mV Reference (1.25% Over Temperature) ■ Wide Input Supply Range: 3V to 20V ■ Overshoot Control Function Prevents Output Overshoot on Startup and Short-Circuit Recovery ■ High Bandwidth Error Amplifi er Permits Simple Loop Frequency Compensation ■ Ground-Referenced OptoCoupler Drive ■ 10mA OptoCoupler Drive with Current Limiting ■ Low Profi le (1mm) ThinSOTTM Package Simplifi ed Isolated Synchronous Forward Converter , LTC and LT are registered trademarks of Linear Technology Corporation. +••VIN

4430 TA01

Isolated Flyback Telecom Converter Startup with Overshoot Control (See Schematic on Page 20) VIN 50V/DIV VOUT 5V/DIV OVERSHOOT CONTROL IMPLEMENTED t = 5ms/DIV 4430 TA01b ThinSOT is a trademark of Linear Technology Corporation.

ABSOLUTE AXI U RATI GSW WW U FOR ATIOPACKAGE/ORDER IUU W

ELECTRICAL CHARACTERISTICS

Operating Junction Temperature Range (Note 2) ORDER PART NUMBER S6 PART MARKING TJMAX = 125°C, θJA = 250°C/W Consult LTC Marketing for parts specifi ed with wider operating temperature ranges. LTBFY LT4430ES6 (Note 1) The ● denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. VIN = 5V, FB = VFB, COMP = 1V, unless otherwise noted (Note 3). SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VIN Input Voltage Range ● 32 0 V IIN Supply Current 3V ≤ V IN ≤ 20V ● 1.9 3.9 mA VUVLO Undervoltage Lockout Threshold OC Held Low for V IN < VUVLO ● 1.95 2.2 2.5 V VFB Feedback Reference Voltage 3V ≤ VIN ≤ 20V ● 0.5955 0.5925 0.6 0.6 0.6045 0.6075 V V V FB Line Regulation 3V ≤ V IN ≤ 20V 0.02 0.1 % IFB FB Input Bias Current FB = V FB –150 –75 nA IOC Overshoot Control Charging Current V OC = 0V ● –15 –8.5 –5 µA OC Clamp Voltage 0.93 V OC Amplifi er Offset Voltage FB = 0.3V 48 mV AVOL Error Amplifi er Open-Loop DC Gain V COMP = 0.8V to 1V ● 60 80 dB Error Amplifi er Unity-Gain Bandwidth No Load (Note 4) 9 MHz Error Amplifi er Output Swing Low FB = 1V

• 0.1 0.35 0.55 V Error Amplifi er Output Swing High FB = 0V ● 1.2 1.33 1.5 V Error Amplifi er Output Source Current FB = 0V, COMP = 1V ● –800 –450 –225 µA Error Amplifi er Output Sink Current FB = 1V, COMP = 1V 25 mA Opto Driver Inverting DC Gain –6.4 –6 –5.6 V/V Opto Driver –3dB Bandwidth No Load (Note 4) 600 kHz Opto Driver Output Swing Low FB = 0V, COMP = Open
• 0.5 0.85 V Opto Driver Output Swing High V IN = 3V, FB = 1V, COMP = Open, IOPTO = 10mA
• VIN – 1.25 V IN – 1.05 V VIN = 20V, FB = 1V, COMP = Open, IOPTO = 10mA
• 4.2 5.6 7.5 V VIN 1 GND 2 OC 3

6 OPTO

5 COMP

TYPICAL PERFOR UWCE CHARACTERISTICSA SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS ISC Opto Driver Output Short-Circuit Current (Sourcing) FB = 1V, COMP = Open, OPTO = 0V ● 10.5 22 45 mA Opto Driver Output Sink Current FB = 0V, OPTO = 1.5V ● 150 350 650 µA Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: The LT4430 is guaranteed to meet performance specifi cations from 0°C to 125°C. Specifi cations over the –40°C to 125°C operating temperature range are assured by design, characterization and correlation with statistical process controls. Note 3: All currents into device pins are positive. All currents out of device pins are negative. All voltages are referenced to GND unless otherwise specifi ed. Note 4: This parameter is guaranteed by correlation and is not tested. The ● denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. VIN = 5V, FB = VFB, COMP = 1V, unless otherwise noted (Note 3). Quiescent Current vs Temperature Undervoltage Lockout Threshold vs Temperature Feedback Reference Voltage vs Temperature FB Voltage Line Regulation FB Input Bias Current vs Temperature TEMPERATURE (°C) –50 1.0 QUIESCENT CURRENT (mA) 1.5 2.0 2.5 3.0 05 0 100 150

4430 G01

3.5 4.0 –25 25 75 125 VIN = 3V VIN = 20V TEMPERATURE (°C) –50 1.0 VUVLO (V) 1.5 2.0 2.5 05 0 100 150

4430 G02

3.0 –25 25 75 125 TEMPERATURE (°C) –50 0.594

0.595 VFB (V)

0.596 0.598 0.600 0.602 05 0 100 150

4430 G03

0.604 0.597 0.599 0.601 0.603 0.605 0.606 –25 25 75 125 VIN (V)

0.5990 VFB (V)

0.5995 0.6000 0.6005 48 12 20

4430 G04

0.6010 26 10 14 16 18 TA = 25°C TEMPERATURE (°C) –50 –200 –175 FB INPUT BIAS CURRENT (nA)–150 –100 –50 05 0 100 150

4430 G07

–125 –75 –25 –25 25 75 125

TYPICAL PERFOR UWCE CHARACTERISTICSA OC Charging Current vs Input Voltage OC Charging Current vs Temperature OC Clamp Voltage vs Temperature OC Amplifi er Offset Voltage vs Temperature Error Amplifi er Output Swing Low vs Temperature Error Amplifi er Output Swing High vs Temperature VIN (V) OC CHARGING CURRENT (µA) 51 0 1 5

4430 G08

TEMPERATURE (°C) –50 OC CHARGING CURRENT (µA)7 05 0 100 150

4430 G09

–25 25 75 125 VIN = 5V TEMPERATURE (°C) –50 0.5 OC CLAMP VOLTAGE (V) 0.7 0.9 1.1 1.3 05 0 100 150

4430 G10

1.5 –25 25 75 125 TEMPERATURE (°C) –50 VOC – VFB (mV) 05 0 100 150

4430 G11

–25 25 75 125 Error Amplifi er Open Loop Gain and Phase vs Frequency TEMPERATURE (°C) –50 ERROR AMPLIFIER OUTPUT SWING LOW (V) 0.1 0.2 0.3 0.4 05 0 100 150

4430 G13

0.5 –25 25 75 125 Error Amplifi er Output Source Current vs Temperature TEMPERATURE (°C) –50 100 ERROR AMPLIFIER OUTPUT SOURCE CURRENT (µA) 200 400 600 800 05 0 100 150

4430 G16

–25 25 75 125 FREQUENCY (Hz) –20 GAIN (dB) –10 50M10M

4430 G12

–45 PHASE (°) 135 180 10k 100k 1M PHASE GAIN TEMPERATURE (°C) –50 1.0 ERROR AMPLIFIER OUTPUT SWING HIGH (V) 1.1 1.2 1.3 1.4 05 0 100 150

4430 G14

1.5 –25 25 75 125

TYPICAL PERFOR UWCE CHARACTERISTICSA Opto Driver Inverting DC Gain vs Temperature Opto Driver Inverting Closed Loop Gain and Phase vs Frequency Opto Driver Output Swing Low vs Temperature Opto Driver Output Swing High vs Temperature Opto Driver Output Swing High vs Temperature Opto Driver Output Sink Current vs Temperature Opto Driver Output Short-Circuit Current (Sourcing) vs Temperature TEMPERATURE (°C) –50 100 OPTO DRIVER OUTPUT SINK CURRENT (µA) 200 400 600 800 05 0 100 150

4430 G23

–25 25 75 125 Error Amplifi er Output Sink Current vs Temperature TEMPERATURE (°C) –50 ERROR AMPLIFIER OUTPUT SINK CURRENT (mA) 05 0 100 150

4430 G15

–25 25 75 125 TEMPERATURE (°C) –50 5.6 OPTO DRIVER INVERTING DC GAIN (V/V) 5.7 5.8 6.0 6.2 05 0 100 150

4430 G17

6.4 5.9 6.1 6.3 –25 25 75 125 TEMPERATURE (°C) –50 0.1OPTO DRIVER OUTPUT SWING LOW (V) 0.2 0.4 0.6 0.8 05 0 100 150

4430 G19

0.3 0.5 0.7 0.9 1.0 –25 25 75 125 TEMPERATURE (°C) –50 0.5

0.6 VIN – VOPTO (V)

0.7 0.9 1.1 1.3 05 0 100 150

4430 G20

0.8 1.0 1.2 1.4 1.5 –25 25 75 125 VIN = 3V IOPTO = 10mA TEMPERATURE (°C) –50

4.0 OPTO DRIVER OUTPUT SWING HIGH (V)

5.0 6.0 7.0 05 0 100 150

4430 G21

4.5 5.5 6.5 7.5 8.0 –25 25 75 125 VIN = 20V IOPTO = 10mA TEMPERATURE (°C) –50 OPTO DRIVER SHORT-CIRCUIT CURRENT (mA) 05 0 100 150

4430 G22

–25 25 75 125 FREQUENCY (Hz) –10 GAIN (dB) 10M

4430 G18

–45 PHASE (°) 135 180 10k 100k 1M PHASE GAIN

VIN (Pin 1): This is the input supply that powers all in- ternal circuitry. The input supply range is 3V minimum to 20V maximum and the typical input quiescent current is 1.9mA. Connect a 1µF bypass capacitor directly from V IN to GND. GND (Pin 2): Analog Ground Pin. It is also the negative sense terminal for the internal 0.6V reference. Connect the external feedback divider network that terminates to ground directly to this pin for best regulation and performance. OC (Pin 3): Overshoot Control Pin. A typical 8.5µA current source and a capacitor placed from this pin to GND controls output voltage overshoot on startup and recovery from short-circuit. The typical ramp time is (C OC • 0.6V)/8.5µA. If VIN is below VUVLO (its undervoltage lockout threshold), the OC pin is actively held low. The OC pin also ties to the overshoot control amplifi er output. This amplifi er monitors the FB pin voltage and the error amplifi er output. If FB is low due to a short-circuit fault condition, the COMP pin goes high. Logic detects the error amplifi er COMP pin high state and activates the overshoot control amplifi er. The amplifi er responds by discharging the OC capacitor down to the FB voltage plus a built-in offset voltage of 48mV. If the short-circuit condition persists, the amplifi er maintains the voltage on OC. If the short-circuit condition goes away, the FB pin recovers under the control of the OC pin. FB (Pin 4): This is the inverting input of the error ampli- fi er. The non-inverting input is tied to the internal 0.6V reference. Input bias current for this pin is typically 75nA fl owing out of the pin. This pin normally ties to a resistor divider network to set output voltage. Tie the top of the external resistor divider directly to the output voltage for best regulation performance. COMP (Pin 5): This is the output of the error amplifi er. The error amplifi er is a true voltage-mode error amplifi er and frequency compensation is performed around the amplifi er. Typical LT4430 compensation schemes use series R-C in parallel with C networks from the COMP pin to the FB pin. COMP also ties to the overshoot control amplifi er logic that detects if the COMP pin is at its high clamp level. The logic activates the overshoot control amplifi er if COMP is at its clamp level for longer than 1µs. OPTO (Pin 6): This is the output of the amplifi er that drives the optocoupler. The opto driver amplifi er uses an inverting gain of six confi guration to drive the optocoupler referenced to ground. Driving the optocoupler referenced to GND accommodates low output voltages and eases loop frequency compensation as the secondary feedback path with a traditional “431” topology is eliminated. The opto driver amplifi er sources a maximum of 10mA, sinks 350µA typically and is short-circuit protected.

S I FOR ATIOAPPLICATIO WU UU BLOCK DIAGRA W VIN IOC 8.5µA VIN VIN 12.5µA 1.1V 0.6V FB DFB 0.2V +– VOS 48mV GND NORMALLY OPEN LOGIC AND DELAY UVLO STARTUP BIAS AND REFERENCE GENERATOR ERROR AMP OC AMP OC COMP OUT 0.6V OPTO DRIVER VIN 12.5µA 15k 90k

4430 BD01

A precision voltage reference, a high-bandwidth error amplifi er, an inverting optocoupler driver and an overshoot control amplifi er comprise the LT4430. Referring to the block diagram, a start-up circuit establishes all internal current and voltage biasing for the IC. A precision-trimmed bandgap generates the 600mV reference voltage and a 1.1V bias voltage for the optocoupler driver. Room tem- perature reference voltage accuracy is specifi ed at ±0.75% and operating temperature range tolerance is specifi ed at ±1.25%. The 600mV reference ties to the non-inverting input of the error amplifi er. The LT4430 error amplifi er senses the output voltage through an external resistor divider and regulates the FB pin to 600mV. The FB pin ties to the inverting input of the error amplifi er. The error amplifi er’s open loop DC gain is 80dB and its unity-gain crossover frequency of 9MHz provides negligible phase shift at typical feedback loop crossover frequencies. The error amplifi er is a true voltage-mode amplifi er and frequency compensation con- nects around the amplifi er. Typical LT4430 compensation schemes use series R-C in parallel with C networks from the COMP pin to the FB pin. The optocoupler driver amplifi es the voltage difference between the COMP pin and the 1.1V bias potential applied to its non-inverting terminal with an inverting gain of 6. This signal drives the optocoupler referenced to GND. Driving the optocoupler referenced to GND accommodates low output voltages and simplifi es loop frequency compen- sation as the secondary feedback path with a traditional “431” topology is eliminated. A resistor in series with the optocoupler sets the optocoupler’s DC bias current. The opto driver amplifi er sources a guaranteed maximum of 10mA, sinks 350µA typically and is short-circuit protected. The optocoupler driver amplifi er’s typical –3dB bandwidth is 600kHz. The optocoupler’s output crosses the galvanic isolation barrier and closes the feedback loop to the pri- mary-side controller.

S I FOR ATIOAPPLICATIO WU UU purposes. First, the offset voltage prevents the overshoot control amplifi er from interfering with normal transient operating conditions. Second, the offset voltage biases the feedback loop so that if the short-circuit condition ends, the feedback loop immediately starts to increase the output voltage to its regulated value. If the fault condition ceases, the output voltage increases. In response, the error amplifi er COMP pin’s voltage decreases. This action opens switch S1, deactivates the overshoot control amplifi er and allows the OC pin capacitor to charge. The FB pin voltage increases quickly until the FB pin voltage exceeds the OC pin voltage. The feedback loop increases the drive to the optocoupler until the FB pin follows and regulates to the OC pin voltage. Again, as the OC pin voltage increases past 600mV, the reference voltage takes control of the error amplifi er and the FB pin regulates to 600mV. Generating a V IN Bias Supply Biasing an LT4430 is crucial to proper operation. If the overshoot control (OC) function is not being used and the output voltage is greater than 3.3V, the IC may be biased from V OUT. In these cases, it is the user’s responsibility to verify large-signal startup and fault recovery behavior. If the overshoot control function is being used or the output voltage is below the LT4430’s minimum operat- ing voltage of 3V, employing an alternate bias method is necessary. The LT4430’s undervoltage lockout (UVLO) circuitry, controlled by V IN, resets and holds the OC pin capacitor low for VIN less than 2.2V. When VIN increases above 2.2V, the circuit releases the OC pin capacitor. The LT4430’s supply voltage must come up faster than the ouput voltage to assert loop control and limit output volt- age overshoot. In most cases, a few simple components accomplish this task. Adding a few biasing components to control overshoot is advantageous. Let’s examine bias circuits for different topologies. The LT4430 incorporates a unique overshoot control function that allows the user to ramp the output voltage on startup and recovery from short-circuit conditions, preventing overshoot. A capacitor, connected from the OC pin to GND and charged by internal 8.5µA current source I OC, sets the ramp rate. On startup, Q1 actively holds the OC capacitor low until VIN of the LT4430 reaches its typi- cal undervoltage lockout threshold of 2.2V. Q1 then turns off and the OC capacitor charges linearly. Q2 and Q3 OR the OC pin voltage and the 600mV reference voltage at the non-inverting terminal of the error amplifi er. The OC pin voltage is the reference voltage for the error amplifi er until it increases above 600mV. If the feedback loop is in control, the FB pin voltage follows and regulates to the OC pin voltage. As the OC pin voltage increases past 600mV, the reference voltage takes control of the error amplifi er and the FB pin regulates to 600mV. The OC pin voltage increases until it is internally clamped by R2, Q6 and V1. The OC pin’s typical clamp voltage of 0.93V ensures that Q3 turns off. All of I1’s current fl ows in Q2, matching I2’s current in Q4. In a short-circuit condition, the output voltage decreases to something well below the regulated level. The error ampli- fi er reacts by increasing the COMP pin voltage, thereby decreasing the drive to the optocoupler. The decreased optocoupler bias signals the primary-side controller to increase the amount of power it delivers in an attempt to raise the output voltage back to its regulated value. As long as the fault persists, the output voltage remains low. The error amplifi er’s COMP pin voltage increases until it reaches a clamp level set by Q7 and V2. Q7’s resultant collector current drives internal logic that closes normally open switch S1. This action activates the overshoot control amplifi er which employs a unity-gain follower confi gura- tion. The overshoot control amplifi er monitors the FB pin voltage and, on S1’s closing, pulls the OC pin voltage down to the FB pin voltage plus a built-in offset voltage of typically 48mV. The built-in offset voltage serves two

S I FOR ATIOAPPLICATIO WU UU Figures 1a to 1e illustrate bias supply circuits for the fl yback converter. Figure 1a shows the typical fl yback output connection. Figures 1b and 1c exhibit equivalent circuit performance but rotate the rectifi er connection to the ground-referred side. This connection permits the user to take advantage of the transformer secondary’s forward behavior when the primary-side switch is on. Figures 1d to 1e illustrate the bias generator circuit. V IN • N volts appear across the secondary winding when the primary-side switch is on. D2 forward biases and C1 charges. During this time, the secondary-voltage is in series with V OUT and C1 ultimately charges to (VIN • N + VOUT – VF). VF is the forward voltage of D2. When V OUT is zero at startup, VIN • N volts exists to charge C1. C1 is generally much smaller in value than C OUT and the bias supply starts up ahead of V OUT. R1 in Figures 1d and 1e limits peak charging currents, lowering D2’s current rating. R1 also fi lters C1 from peak-charging to the volt- age spikes induced by the secondary winding’s leakage inductance. Between 1Ω to 10Ω is generally suffi cient. R1 is usually necessary if C1 is a low ESR ceramic capacitor or if the transformer has high leakage inductance. It may be possible to eliminate R1 if C1 is a low cost, high ESR, surface-mount tantalum. V IN variation changes the bias supply in Figure 1d. Depend- ing on VOUT, the transformer turns ratio N and VIN range, the bias supply may exceed the LT4430’s 20V VIN absolute maximum rating. If this occurs, two solutions exist. One is to tap the secondary-side inductor to create a lower voltage from which to rectify as illustrated in Figure 2a. The bias voltage decreases to (V IN • N1/N + V OUT – VF). This solution relies on secondary-side pins being available for the tap point. The second solution is to make a preregulator as shown in Figure 2b. In this example, the bias supply equals (V – VBE). Select R2 to bias zener diode Z1 and to supply base current to QBS. Resistor R3 (on the order of a few hundred ohms), in series with Q5’s base, suppresses possible high frequency oscillations depending on QBS’s selection. The preregulator circuit has additional value for fully synchronous converters. Fully synchronous convert- ers require gate drivers to control the secondary-side MOSFETs turn on and turnoff. The gate driver circuitry requires supply current in the range of 10mA to 100mA depending on the gate driver supply voltage, MOSFET size and switching frequency. The preregulator bias supply is ideal for powering both the LT4430 and the gate driver

• VIN

4430 F01a

1:N VOUT COUT

• VIN

4430 F01b

1:N VOUT COUT

• VIN

4430 F01c

1:N VOUT COUT SYNC

• VIN

4430 F01d

1:N VOUT COUT *OPTIONAL SEE TEXT LT4430 VBIAS C1R1*D2

• VIN

4430 F01e

1:N VOUT COUT *OPTIONAL SEE TEXT SYNC LT4430 VBIAS C1R1*D2 Figure 1a. Typical Flyback Converter Connection Figure 1b. Equivalent Flyback Converter Connection Figure 1c. Synchronous Flyback Converter Connection Figure 1d. Flyback Converter with Bias Generator Figure 1e. Synchronous Flyback with Bias Generator

S I FOR ATIOAPPLICATIO WU UU circuitry, especially since the gate drivers typically use a supply voltage between 5V to 12V. The preregulator circuit fi nds wide use in fully synchronous forward converters, push-pull converters and full-bridge converters. Generate a bias supply for a forward converter using similar techniques to that of the fl yback converter. Figure 3a to 3c detail the three common bias circuits for the synchronous

4430 F02a

1:N N = N1 + N2 VOUT COUT *OPTIONAL SEE TEXT LT4430 VBIAS C1R1*D2

• •VIN •
• VIN

4430 F02b

1:N VOUT LT4430 VBIAS COUT R1*D2 *OPTIONAL SEE TEXT R3* QBS Figure 2a. Flyback Converter with Tapped Secondary Bias Figure 2b. Flyback Converter with Preregulator Bias

• •VIN

4430 F03a

1:N VOUT COUT CG *OPTIONAL SEE TEXT Q2FGQ1 LT4430 VBIAS C1R1*D1

4430 F03b

1:N N = N1 + N2 VOUT COUT CG *OPTIONAL SEE TEXT LT4430 VBIAS C1R1*D1

• •VIN FGQ1
• •VIN

4430 F03c

1:N VOUT LT4430 VBIAS COUT R1*D1 CG *OPTIONAL SEE TEXT Q2FGQ1 R3* QBS Figure 3a. Typical Single-Switch Synchronous Forward Converter with Bias Generator Figure 3b. Single-Switch Synchronous Forward Converter with Tapped Secondary Bias Generator Figure 3c. Single-Switch Synchronous Forward Converter with Preregulator Bias Generator single-switch forward converter. In the fl yback converter of Figure 1d, the bias supply is proportional to V IN and VOUT. However, in the forward converter, L1’s presence decouples the bias supply from V OUT. In Figure 3a, the bias supply equals (VIN • N – V F). In Figure 3b, the bias supply equals (V IN • N1/N – V F). In Figure 3c, the bias supply equals (VZ1 – VF).

S I FOR ATIOAPPLICATIO WU UU straints such as a very wide input voltage range may force employment of other biasing circuits. Other methods of generating the bias supply may include an additional transformer or output inductor winding, low-cost linear regulators, discrete or monolithic charge pumps and buck/boost regulators. However, if the bias supply gets this complicated, a quick chat with your local LTC applications engineer may result in a simpler solution. Figures 4a to 4d demonstrate bias supply circuits for the fully-synchronous push-pull topology. Biasing for full- bridge schemes is identical to the push-pull circuits with the obvious difference in the primary-side drive. In Figure 4a, the bias supply equals (V IN • N – VF). In Figure 4b and 4d, the bias supply equals (2 • VIN • N – VF). In Figure 4c and 4e, the bias supply equals (VZ1 – VF). In general, one of the simple, low-cost biasing schemes suffi ces for LT4430 applications. However, design con- VIN

4430 F04a

1:N VOUT COUT *OPTIONAL SEE TEXTMF ME Q2 LT4430 VBIAS C1R1*D1 VIN

4430 F04b

1:N VOUT COUT *OPTIONAL SEE TEXTMF ME LT4430 VBIAS C1R1*D1 Figure 4a. Typical Synchronous Push-Pull Converter with Bias Generator Figure 4b. Typical Synchronous Push-Pull Converter with 2x Bias Generator Figure 4c. Typical Synchronous Push-Pull Converter with Preregulator Bias Figure 4d. Typical Synchronous Push-Pull Current-Doubler Converter with Bias Generator Figure 4e. Typical Synchronous Push-Pull Current-Doubler Converter with Preregulator Bias VIN

4430 F04c

1:N VOUT LT4430 VBIAS COUT R1*D1 *OPTIONAL SEE TEXTMF ME R3* QBS VIN

4430 F04d

1:N VOUT LT4430 VBIAS COUT C1R1*D1 ME *OPTIONAL SEE TEXT MF VIN

4430 F04e

1:N VOUT LT4430 VBIAS COUT R1*D1 ME *OPTIONAL SEE TEXT MF R3* QBS

current of 75nA fl owing out of the pin. controller’s error amplifi er. many cases, this pole limits the achievable loop bandwidth.

4430 F06a

Figure 5. Setting Output Voltage

4430 F05

and still transfers the loop error signal. output phototransistor separated by an insulating gap.

S I FOR ATIOAPPLICATIO WU UU side error amplifi er’s output is: V V A R RR sR C sR C sAR C C sR CC CC sR C s RR R C OUT KK KD K = + ⎝⎜ ⎞ ⎠⎟ ++ ++ + + +  (  )  () 12 11 1 13 3 12 3 1 3 23 6 1

1 RR C

D K C KD C KD CB BE CC )    ()   ( ) ()  + + +⎡ +() π where: A = LT4430 open loop DC Gain R D = Optocoupler diode equivalent small-signal resistance CTR = Optocoupler AC current transfer ratio C CB = Optocoupler non-linear collector-to-base capacitor C BE = Optocoupler non-linear base-to-emitter capacitor r π = Optocoupler small-signal base-to-emitter resistor Figure 6a and its transfer function illustrate most of the possible poles and zeroes that can be set and are shown for the sake of completeness. In a practical application, the transfer function simplifi es considerably because not all the poles and zeroes are used. Also, different combinations of poles and zeroes can result in the same small signal gain-phase characteristics but demonstrate dramatically different large-signal behavior. The common-collector confi guration eliminates the miller effect of the output transistor’s collector-to-base capaci- tance and generally increases achievable loop bandwidth. Figure 6b illustrates the common-collector design with the output transistor’s emitter connected to the inverting input of the primary-side controller’s error amplifi er. In this example, the error amplifi er is typically a voltage error amplifi er confi gured as a transimpedance amplifi er. The optocoupler transistor’s emitter provides feedback information directly to the FB pin and the resistor R E from FB to GND sets the DC bias condition for the optocoupler. The open loop transfer function from the output voltage to the primary-side error amplifi er’s output is: V V A R RR sR C sR C sAR C C sR CC CC sR C s RR R C OUT KK KD K = + ⎝⎜ ⎞ ⎠⎟ ++ ++ + + +  (  )  () 12 11 1 13 3 12 3 1 3 23 6 1 D K C KD BE C C )    ()  +() +()π Figure 6b and its transfer function illustrate most of the possible poles and zeroes that can be set and are shown for the sake of completeness. In a practical application, the transfer function simplifi es considerably because not all the poles and zeroes are used. Figure 6b. Frequency Compensation with Optocoupler Common-Collector Confi guration VCC VREF VC RE RK PRIMARY-SIDE ERROR AMP OPTO DRIVER OPTO OPTO LT4430 COMP 1.1V 0.6V FB ERROR AMP 15k 90k

4430 F06b

In both confi gurations, the terms RD, CTR, rπ, CCB and CBE. vary from part to part and also change with bias current. the feedback loop for all operating conditions. Table 1. Optocoupler Vendors connecting a capacitor from the OC pin to GND. stability requirements with the overshoot control amplifi er. by externally driving the OC pin. responses is diffi cult. Compromise values often result. circuitry being powered, not a desirable trait. Figure 7. Setting Overshoot Control Time

4430 F07

S I FOR ATIOAPPLICATIO WU UU The LT4430’s overshoot control circuitry plus one external capacitor (COC) provide independent control of startup and short-circuit recovery response without compro- mising small-signal frequency compensation. Choosing the optimum C OC value is a straightforward laboratory procedure. The following description and set of pictures explain this procedure. Before choosing a value for the OC pin capacitor, complete the remainder of the power supply design. This process includes evaluating the chosen V IN bias generator topology (please consult prior applications information section) and optimizing frequency compensation under all normal operating conditions. During this design phase, set C OC to its minimum value of 100pF. This ensures negligible interaction from the overshoot control circuitry. Once these steps are complete, construct a test setup that monitors startup and short-circuit recovery waveforms. Perform this testing with the output lightly loaded. Light load, following full slew operation, is the worst-case as the feedback loop transitions from full to minimal power delivery. As an example, refer to the schematic on the last page illustrating the 5V, 2A isolated fl yback converter. All of the following photos are taken with V IN = 48V and I LD = 20mA. Figure 8a demonstrates the power supply startup and short-circuit recovery behavior with no overshoot control compensation (C OC = 100pF minimum). The 5V output overshoots by several volts on both startup and short-circuit recovery due to the conservative nature of the small-signal frequency compensation values. Next, increase C OC’s value. Either use a capacitor substitu- tion box or solder each new value into the circuit. Monitor the startup and short-circuit recovery waveforms. Note any changes. Figures 8b to 8e illustrate what happens as C OC increases. In general, overshoot decreases as C OC increases. COC = 0.0168µF in Figure 8b begins to affect loop dynam- ics, but startup still exhibits about 1.5V of overshoot. Short-circuit recovery is considerably more damped. C OC = 0.022µF in Figure 8c damps startup overshoot to 0.5V and short-circuit recovery remains similar to that of Figure 8b. C OC = 0.033µF in Figure 8d provides under 100mV of overshoot and short-circuit recovery is slightly more damped. C OC = 0.047µF in Figure 8e achieves zero over- shoot at the expense of additional damping and delay time in short-circuit recovery. In this example, COC = 0.033µF provides the best value for both startup and short-circuit recovery. Figure 8f provides an expanded scale of the waveforms. After a C OC value is selected, check startup and short-circuit recovery over the VIN supply range and with higher output load conditions. Modify the value as necessary. Startup and short-circuit recovery waveforms for various designs will differ from the photos shown in this example. Factors affecting these waveforms include the isolated topology chosen, the primary-side and secondary-side bias circuitry and input/output conditions. For instance, in many isolated power supplies, a winding on the main power transformer bootstraps the supply voltage for the primary-side control circuitry. Under short-circuit condi- tions, the primary-side control circuitry’s supply voltage collapses, generating a restart cycle. Recovery from short-circuit is therefore identical to startup. In the fl yback example discussed, the primary-side control circuitry is always active. Switching never stops in short-circuit. The LT4430 error amplifi er COMP pin changes from its low clamp level to its higher regulating value during startup and changes from its high clamp level to its lower regulat- ing point during short-circuit recovery. This large-signal behavior explains the observed difference in the startup versus short-circuit recovery waveforms. A fi nal point of discussion involves the chosen C OC value. LTC recommends that the designer use a value that con- trols overshoot to the acceptable level, but is not made overly large. The temptation arises to use the overshoot control function as a power supply “soft-start” feature. Larger values of C OC, above what is required to control overshoot, do result in smaller dV/dt rates and longer startup times. However, large values of C OC may stall the feedback loop during startup or short-circuit recovery, resulting in an extended period of time that the output voltage “fl atspots”. This voltage shelf may occur at an intermediate value of output voltage, promoting anomalous behavior with the powered load circuitry. If this situation occurs with the desired C OC value, solutions may require circuit modifi cations. In particular, bias supply holdup times are a prime point of concern as switching stops during these output voltage fl atspots. As a reminder,

4430 TA03a

8A7, 10 PA0741 8, 112 R24 26.1k R22 330Ω R21 330Ω C OUT = TDK D1, D2, D7 = PHILIPS Q1, Q2 = PHILIPS L1 = PULSE ENGINEERING PB2020.103 T1 = PULSE ENGINEERING T2 = COILCRAFT Q4470-B R23 8.2k C15 2.2nFC13 1µF R25 6.04k 1VBS VBS COUT 22µF 50V X7R NEC PS2701 PH21NQ15 BCX55 LT4430 ISOLATION BARRIER 1nF C14 33nF C16 10pF VU1 PH20100 PH20100 12V VU1 R10 22k R11 1.2k 82k 370k 47k R26 10Ω 2.2µF 100V 1µF R14 0.008Ω LT1952 2.2µF VU1 SD_VSEC ROSC SS_MAXDC SYNCNC SOUT VIN BLANK GND PGND SOUT 21 0 FB I SENSE 11 1COMP OC 61 2 VREF DELAY 18V BAS516 VBS LTC3900 SYNC87 TIMER GND62 CS–CS– VCC41 CS+ FG53 CG VIN GND OC OPTO COMP FB C11 1µF 220pF C17 2200pF 250V R18 10k 10µH R19 10k R17 10k C12 1nF R20 15k VBS R15 2.2Ω C10 1µF R16 BCX55 8.2V 10nF 100VD5 B0540W B0540W 6.8nF 100V R12 39k 13.2k 33k 114k 33k 33k R13 680Ω 33k BAT760 0.47µFC6 0.1µF 200W, 26V, 95% Effi cient Base Station Converter

0.47µF 1µF DRVA DPRG V REFSPRGGND SSFB C T 330pF 22nF 68nF 270pF 1(1.5mH):0.5 4T:6T(65µHMIN):6T:2T:2T 243k 604Ω 11.5k 1%750Ω 1.5k 813 1mH 68µF 20V VF 10k 33k 200Ω 1/4W 0.03Ω 1.5W 66.5k RLEB 127 14 220pF 4.7nF 100Ω 1.1k 866Ω 1.5nF 464k 30k 1/4W SYNC PV CC CSF+ VF LTC3901EGN CSF– 11 12 41 0 1 3 7 1µF 1µF

4430 TA03b

–VOUTVOUT –VOUT 10V VOUT MF MF2 GND PGND GND2 PGND2 TIMER VCC 470pF 14 15 1% 866Ω 42.2k 100Ω 6.19k 1/4W 6.19k 1/4W 1/4W C1, C2 47µF 16V CSE+ VE VF VOUT 12V/20A –VOUT CSE– ME ME2 23 1 6 Si7852DP Si7370DP Si7370DP Si7852DP 0.56µH 112 12V D5

• • • VE 0.1µF Si7852DP B A LTC4440ES6 BOOSTINP TG TSGND VCC 12V 0.1µF Si7852DP B LTC4440ES6 BOOSTINP TG TSGND VCC 12V +VIN VIN –VIN 42V TO 56V 1µF 100V 1µF 1µF 100V 1µF, 100V TDK C3225X7R2A105M C1, C2: SANYO 16TQC47M C3: AVX TPSE686M020R0150 C4: MURATA GHM3045X7R222K-GC D1: DIODES INC. ES1B D3-D6: BAS21 D7: MMBZ5240B L4: COILCRAFT DO1608C-105 L5: COILCRAFT DO1813P-561HC L6: PULSE PA1294.132 OR PANASONIC ETQP1H1R0BFA R1, R2: IRC LRC2512-R03G T1: PULSE PA0805.004 T2: PULSE PA0785 ISNS ISNS 0.1µF MOC207 2.2nF 250V 470pF VIN GND OPTO

A 1.5k 22Ω 4.7Ω4.7Ω 0.03Ω 1.5W VE 1nF 100V 1.25µH EFFICIENCY (%) 81 0 1 2 LOAD CURRENT (A) 14 16 18 20 42VIN 48VIN 56VIN MMBT3904 1µF 100V 1/4W LTC3723-1 240W 42VIN to 56VIN to 12V/20A Isolated 1/4 Brick (2.3" × 1.45")

Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. PACKAGE DESCRIPTIO U 1.50 – 1.75 0.25 – 0.50 TYP 6 PLCS NOTE 3 DATUM ‘A’ 0.09 – 0.20 (NOTE 3) S6 SOT-23 0502 2.80 – 3.10 (NOTE 4)

0.95 BSC

1.90 BSC

0.90 – 1.30 0.90 – 1.45 0.09 – 0.15 NOTE 3

0.20 BSC

0.35 – 0.55 REF PIN ONE ID NOTE: 1. DIMENSIONS ARE IN MILLIMETERS 2. DRAWING NOT TO SCALE 3. DIMENSIONS ARE INCLUSIVE OF PLATING 4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR 5. MOLD FLASH SHALL NOT EXCEED 0.254mm 6. PACKAGE EIAJ REFERENCE IS SC-74A (EIAJ) ATTENTION: ORIGINAL SOT23-6L PACKAGE. MOST SOT23-6L PRODUCTS CONVERTED TO THIN SOT23 PACKAGE, DRAWING # 05-08-1636 AFTER APPROXIMATELY APRIL 2001 SHIP DATE

3.85 MAX

0.62 MAX 0.95 REF RECOMMENDED SOLDER PAD LAYOUT PER IPC CALCULATOR 1.4 MIN2.62 REF

1.22 REF

(Reference LTC DWG # 05-08-1634)

Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2004 LT/TP 0804 1K • PRINTED IN USA TYPICAL APPLICATIO U RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1693 High Speed Single/Dual N-Channel MOSFET Drivers CMOS Compatible Input, V CC Range: 4.5V to 13.2V LTC1698 Isolated Secondary Synchronous Rectifi er Controller Pulse Transformer Synchronization, Optocoupler Driver LT1950 Forward Controller Programmable Volt-Second Clamp and Slope Compensation LT1952 Single-Switch Synchronous Forward Controller Synchronous Output Driver, Precision Current Limit, Programmable Volt-Second Clamp and Slope Compensation LT3710 Secondary Side Synchronous Post Regulator Generates Regulated Auxiliary Output in Isolated DC/DC Converters, Dual N-Channel MOSFET Synchronous Drivers LTC3722-1/ LTC3722-2 Synchronous Dual Mode Phase Modulated Full-Bridge Controllers 50W to 2kW Power Supply Design, Adaptive Direct Sense ZVS LTC3723-1/ LTC3723-2 Synchronous Push-Pull PWM Controllers LTC3723-1: Peak Current Mode Control, Programmable Slope Compensation, Leading Edge Blanking LTC3723-2: Voltage Mode Control with Voltage Feedforward LT3781 Dual Transistor Synchronous Forward Controller Operation up to 72V Maximum LTC3803 Constant Frequency Current Mode Flyback DC/DC Controller in ThinSOT Adjustable Slope Compensation, Internal Soft-Start, 200kHz LT3804 Secondary Side Dual Output Controller with Opto Driver Regulates Two Outputs, OptoCoupler Feedback Driver and Second Outpu t Synchronous Driver Controller LTC3900 Synchronous Rectifi er Driver for Forward Converters Programmable Timeout, Synchronization Sequence Monitor, Reverse Inductor Current Sense LTC3901 Synchronous Rectifi er Driver for Push-Pull and Full- Bridge Converters Programmable Timeout, Synchronization Sequence Monitor, Reverse Inductor Current Sense 5V, 2A Isolated Flyback Telecom Converter Startup Waveforms with and without Overshoot Control Implemented 36V TO 72V VIN –VIN

4430 TA02

2A9, 10 CTX-02-15242 11, 12 11k R10 680Ω C1 = TDK, X7R CO1, C02, C03 = TDK, X5R D1, D2, D3 = PHILIPS D4 = MICROSEMI Q1 = FAIRCHILD Q2 = DIODES, INC. T1 = COOPER MOC207 = FAIRCHILD MBR0530 0.1µFC5 1µF 1500Ω VIN OPTO CO3 100µF 6.3V GND COMP OC FBMOC207 FDC2512 MMBTA42 LT4430 ISOLATION BARRIER 150pF 200V 0.047µF 0.033µF 2200pF 250V 8.5V CO2 100µF 6.3V CO1 100µF 6.3V UPS840 BAS516 PDZ-9.1B 9.1V 8.5V BAS516 470k 6.8k 220k 100k 220Ω 1µF 10V 1µF 100V RCS 0.068Ω 4.7k ITH/RUNITH/SHDN NGATE GND V CC FB SENSE LTC3803