LT4351IMS

LT4351 LINER

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MOSFET Diode-OR Controller n Low Loss Replacement for ORing Diode in Multiple Sourced Power Supplies n External N-Channel MOSFETs for High Current Capability n Internal Boost Regulator Supply for MOSFET Gate Drive n Wide Input Range: 1.2V to 18V n Fast Switching MOSFET Gate Control n Input Under and Overvoltage Detection n STATUS and FAULT Outputs for Monitoring n Internal MOSFET Gate Clamp n Available in a 10-pin MSOP , LTC and LT are registered trademarks of Linear Technology Corporation. n Paralleled Power Supplies n Uninterrupted Supplies n High Availability Systems n N + 1 Redundant Power Supplies The LT4351 creates a near-ideal diode using external single or back-to-back N-channel MOSFETs. This ideal diode function permits low loss ORing of multiple power sources. Power sources can easily be ORed together to increase total system power and reliability with minimal effect on supply voltage or efficiency. Disparate power supplies can be efficiently ORed together. The IC monitors the input supply with respect to the load and turns on the MOSFET(s) when the input supply is higher. If the MOSFET’s R DS(ON) is sufficiently small, the LT4351 will regulate the voltage across the MOSFET(s) to 15mV. A STATUS pin indicates the MOSFET on state. An internal boost regulator generates the MOSFET gate drive voltage. Low operating voltage allows for OR’ing of supplies as low as 1.2V. The LT4351 will disable power passage during undervolt- age or overvoltage conditions. These voltages are set by resistive dividers on the UV and OV pins. The undervoltage threshold has user programmable hysteresis. Overvolt- age detection is filtered to reduce false triggering. The LT4351 is available in a 10-pin MSOP. Dual 5V Redundant Supply RLOADCLOAD GATE OUTVIN VDD SW LT4351 UV OV STATUS 1µF 24.9k 232Ω 1.47k 10µF 10µF POWER SUPPLY 4.7µH MBR0530 FAULT GND Si4862DYSi4862DY GATEOUT 5V COMMON VIN VDD SW LT4351 UV OV STATUS 1µF 24.9k 232Ω 1.47k

4351 TA01

4.7µH MBR0530 FAULT GND POWER SUPPLY DESCRIPTIO UFEATURES APPLICATIO SU TYPICAL APPLICATIO U

Operating Temperature Range ORDER PART NUMBER MS PART MARKING TJMAX = 125°C, qJA = 120°C/W LTZZ LTA1 LT4351CMS LT4351IMS (Note 1) ABSOLUTE AXI U RATI GSW WW U PACKAGE/ORDER I FOR ATIOUU W Consult LTC Marketing for parts specified with wider operating temperature ranges. The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = VOUT = 5V, VDD = 16.1V, VUV = 0.4V, VOV = 0.2V, GATE Open, unless otherwise specified.

ELECTRICAL CHARACTERISTICS

V DD VIN SW GND OUT STATUS FAULT UV OV TOP VIEW MS PACKAGE 10-LEAD PLASTIC MSOP SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Supply and Protection VIN Operating Range l 1.2 18 V VIN = 18V, VOUT = 17.9V, VDD = 29.1V l 1.71 2.1 mA VUV(TH) Undervoltage Turn-Off Voltage Threshold UV Falling l 290 300 310 mV IUV(HYST) IUV Hysteresis Difference Between I UV at VUV(TH) + 10mV l 71 0 1 3 mA and VUV(TH) – 10mV IUV UV Input Bias Current V UV = VUV(TH) + 10mV l –100 –400 nA VOV(TH) Overvoltage Threshold OV Rising l 290 300 310 mV IOV OV Input Bias Current V OV = VOV(TH) – 10mV l –100 –400 nA VF(ON) FAULT Pin On Voltage I F = 5mA In Fault Condition l 0.14 0.25 V IF(OFF) FAULT Pin Leakage Current V F = 30V, VIN = 4.9V l 0.04 1 mA Boost Supply VBR Boost Regulation Trip Voltage Measured as V DD to VIN, Rising Edge l 10.2 10.7 11.1 V tOFF Boost Supply Off Time 600 ns ISWLIM Boost Supply Switch Current Limit l 350 450 650 mA Gate Drive VIOR Input to Output Regulated Voltage l 41 5 2 5 m V DVGL Gate Voltage Limit V IN = 5V, VOUT = 4.9V, VDD = 13V Measured with l –2.3 –3 V Respect to VDD DVG(MAX) Maximum Gate Voltage V IN = 5V, VOUT = 4.9V, VDD = 16.1V Measured with l 7 7.4 7.8 V Respect to VOUT VGOFF Gate Off Voltage V OUT = 5.1V l 0.16 0.30 V IGSO Gate Source Current V OUT = 4.9V, VGATE = 9V 0.670 A IGSK Gate Sink Current V OUT = 4.9V, VGATE = 9V 0.670 A

The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = VOUT = 5V, VDD = 16.1V, VUV = 0.4V, VOV = 0.2V, GATE Open, unless otherwise specified. Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. TYPICAL PERFOR A CE CHARACTERISTICS UW Undervoltage Threshold vs Temperature Overvoltage Threshold vs Temperature Undervoltage Threshold vs V IN Note 2: TJ is calculated from the ambient temperature TA and power dissipation PD according to the following formula: TJ = TA + (PD • 120°C/W) TEMPERATURE (°C) –50

290 VUV(TH) (mV)

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–25 25 100 125 VIN = 1.2V VIN = 5V VIN = 12V VIN = 20V TEMPERATURE (°C) –50

293 VOV(TH) (mV)

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–25 25 100 125 VIN = 1.2V VIN = 5V VIN = 12V VIN = 20V VIN (V) VUV(TH) (mV) 302 306 310

4351 G03

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VDD Operating Range l 30 V VIN = 18V, VOUT = 17.9V, VDD = 29.1V, GATE Open l 3.6 5.6 mA Status Functions DVGIS Min Gate Voltage for Turning On Status V OUT = 4.9V, ISTATUS = 1mA l 0.75 1 V VIOGF VIN to VOUT Fault Voltage V OUT Falling, Measured with Respect to VIN 185 210 230 mV with Open Gate VSTON Status Pin On Voltage I ST = 5mA, VOUT = 4.9V, Status On l 0.13 0.25 V ISTOFF Status Pin Leakage Current V ST = 30V, Status Off, VIN = 4.9V l 0.04 1 mA Specifications are at TA = 25°C unless otherwise specified.

IVIN vs Temperature Gate Off Voltage vs Temperature GATE Pin Turn On and Off Waveform with 10nF Capacitor Load Typical SW Pin Waveform Overvoltage Threshold vs VIN Overvoltage Hysteresis vs Temperature VIN (V) VUV(TH) (mV) 302 306 310

4351 G04

TEMPERATURE (°C) –50 –25 OV HYSTERESIS (mV) 0 50 75

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VIN = 5V Overvoltage Turn-Off Delay vs Overvoltage Overdrive OV VOLTAGE ABOVE THRESHOLD (mV) TURN-OFF DELAY (µs) 10 20 25

3451 G06

VIN = 5V TEMPERATURE (°C) –50 1.0 IVIN (mA) 1.1 1.3 1.4 1.5 2.0 1.7 0 50 75

4351 G07

1.2 1.8 1.9 1.6 –25 25 100 125 VIN = 1.2V VIN = 5V VIN = 12V VIN = 20V IVDD vs Temperature TEMPERATURE (°C) –50 2.0 IVDD (mA) 3.0 3.5 4.5 0 50 75

4351 G08

2.5 4.0 –25 25 100 125 VIN = 1.2V VIN = 5V VIN = 12V VIN = 20V TEMPERATURE (°C) –50 VGOFF (V) 0.05 0.15 0.20 0.25 0.50 0.35 0 50 75

4351 G09

0.10 0.40 0.45 0.30 –25 25 100 125 VIN = 5V VOUT = 5V VIN = 5V VOUT = 5.1V VSW 2V/DIV VIN = 5V 50ns/DIV 3451 G10 VOUT = 4.9V to 5.1V SQUARE WAVE TURN ON TURN OFF VSW 5V/DIV VIN = 5V 500ns/DIV 3451 G11 L = 4.7mH TYPICAL PERFOR A CE CHARACTERISTICS UW Specifications are at TA = 25°C unless otherwise specified.

GATE (Pin 1): MOSFET Gate Drive Pin. This pin is tied to the gate(s) of the external N-channel MOSFET(s). The GATE pin drives high when UV is above the V UV(TH) threshold, OV is below the V OV(TH) threshold and V IN is greater than OUT by 15mV. When not driven high, GATE actively pulls to GND. GATE can sink or source up to 600mA. V DD (Pin 2): Gate Drive Supply Pin. This is the supply pin for the gate drive amplifier. It is either generated by the onboard boost regulator or supplied externally. When turning on the MOSFET(s), a large high current pulse flows through this pin. Bypass the pin with a 1 mF capacitor placed in close proximity to the part. The voltage on this pin is also the feedback for the boost regulator. If the V DD voltage exceeds the VIN voltage by 10.7V, the boost switch is held off. VIN (Pin 3): Input Supply Pin. This pin is the supply pin for the control circuitry and the boost regulator. It is also one input in conjunction with OUT for controlling the MOSFET(s). Bypassing should include a low ESR/ESL capacitor placed in close proximity to the part. SW (Pin 4): Boost Regulator Switch Pin. This pin is the boost regulator switch output. It is connected to the boost inductor and the boost diode. Peak switch current is limited internally to 450mA. If an external V DD supply is used, leave this pin open. GND (Pin 5): Device Ground Pin. This pin is ground for the boost switch, gate driver as well as the control circuitry. Tie the VIN and VDD bypass capacitors and ground plane close to this pin to minimize the effects of switching currents on part performance. Typical SW Pin Waveform SW Pin Waveform at Maximum Boost Regulator Output VSW 5V/DIV VIN = 5V 10 ms/DIV 3451 G12 4.7mH INDUCTOR VSW 5V/DIV VIN = 5V 10 ms/DIV 3451 G13 4.7mH INDUCTOR TYPICAL PERFOR A CE CHARACTERISTICS UW Specifications are at TA = 25°C unless otherwise specified.

OV (Pin 6): Overvoltage Shutdown Pin. This pin is used for input overvoltage detection. It is connected to a resistive divider from VIN. When the voltage exceeds the OV threshold (0.3V), GATE is pulled to GND disabling power transfer. In addition, the FAULT pin pulls low indicating a fault. Overvoltage detection has filtering on it to prevent false triggering. The filtering depends on the level of overdrive. Filtered tripping will occur when OV exceeds 0.3V. If OV exceeds 0.33V, the gate immediately turns off (no filtering). If overvoltage detection is not required, ground the OV pin. See Applications Informa- tion for further information. UV (Pin 7): Undervoltage Shutdown Pin. This pin is used for the undervoltage detect function. It is connected to a resistive divider from VIN. When the voltage is below the UV threshold, GATE pulls to GND disabling power transfer. In addition, the FAULT pin pulls low indicating a fault. When the UV pin voltage drops below the threshold, a 10mA current is pulled from the divider to provide hysteresis. If under- voltage detection is not required, tie the UV pin to a voltage greater than 320mV and not greater than V IN. Do not force more than 9V on UV due to an internal clamp. See Appli- cations Information for further information. FAULT (Pin 8): Fault Comparator Status Pin. This pin pulls low when a fault occurs. A fault has occured if the UV pin is below threshold or the OV pin is above threshold. The FAULT pin low indicates that there is a problem with the V IN (source) supply. GATE is pulled to GND during a fault, disabling the MOSFET(s) and prohibits common supply contamination. If the GATE pin goes to compliance (GATE equals the lesser of V DD – 2.3V or OUT + 7.4V) and VIN is greater than OUT by more than 0.21V, FAULT turns on as an indicator that the MOSFETs are probably not function- ing. Leave this pin open if not used. STATUS (Pin 9): MOSFET Status Pin. This pin pulls low when GATE is above V IN by more than 0.7V and V IN is greater than OUT by 15mV. This indicates the MOSFET is on. Leave this pin open if not used. OUT (Pin 10): Common Supply Pin. This pin is connected to the supply common and is used in conjunction with VIN as one input controlling the MOSFET(s).

+–15mV ENABLE ENABLE QSW CUV COV 0.3V 0.3V 0.33V COVF GND OV UV RA SW VDD VIN GATE VIN 324 OPEN MOSFET DETECT 600ns ONE SHOT 10.7V REG RB VIN FROM INDIVIDUAL SUPPLY TO COMMON SUPPLY VOUT OUT OUT ST STATUS FAULT 4351 BD DRIVER

Increasingly, system designers have to deal with multiple supply sources. The multiplicity may provide parallel, re- dundant supplies for increased reliability or provide a means of connecting disparate supplies. In all cases the desire is for behavior like a diode but with no loss or voltage drop. ORing diodes have been the conventional means of connecting these supplies. The disadvantage of this ap- proach is that diodes introduce efficiency loss because of their forward voltage drop. This variable voltage drop also degenerates supply tolerance. Additionally, diodes pro- vide no information concerning the status of the sourcing supply. Separate control must also be added to ensure that a supply that is out of range is not allowed to affect the common supply. The LT4351 eliminates these problems by using N-channel MOSFETs as the pass elements. The MOSFET is turned on when power is being passed, allowing for a low voltage drop from the supply to the load. When the input source voltage drops below the output common supply voltage it turns off the MOSFET, thereby matching the function and performance of an ideal diode. The LT4351 drives either a single MOSFET or dual back- to-back MOSFETs. Dual MOSFETs are chosen to eliminate current flow from the input supply to the output supply when the V IN voltage is greater than OUT. A driver amplifier monitors the input (V IN) and output (OUT) and controls the MOSFETs. If VIN exceeds OUT by 15mV, GATE goes high and turns on the MOSFET(s) allowing for power passage. Undervoltage and overvoltage comparators C UV, COV and COVF also control power passage. A resistive divider in conjunction with the UV and OV pins sets appropriate thresholds such that the MOSFET(s) is off when the UV pin is below 300mV or OV pin is above 300mV. To help deal with the transients on the supply lines, the UV input has current hysteresis. When the UV voltage drops below the 300mV threshold, a 10mA current is pulled from the pin. Thus the user can set the hysteresis level through appropriate values in the divider. Overvoltage shutdown occurs in two stages. The first occurs when the OV pin exceeds the 300mV reference. When OV just exceeds the reference, an internal capacitor starts charging, delaying the signal to turn off the MOSFET(s). The second occurs when the OV pin exceeds 330mV. The OVF comparator will immediately trip pulling GATE to GND. This affords a delay inversely proportional to the amount of overdrive. This also provides for glitch immu- nity without compromising response time in the event of a serious overvoltage condition. The FAULT output indicates the status of the C OV, COVF and CUV comparators. It pulls low during a fault condition. It also pulls low when GATE is at compliance and VIN > OUT by more than 0.21V indicating a probable nonfunctioning MOSFET. Compliance occurs when GATE is at the lesser of OUT + 7.4V or V DD – 2.3V. FAULT derives its drive from the greater of VIN or OUT. It is active if VIN or OUT is greater than 0.9V. If VIN or OUT is below this level, the output state is not guaranteed. The gate drive consists of a high current, wide bandwidth amplifier (Driver). When the amplifier is enabled, it at- tempts to regulate the GATE voltage such that the voltage across the MOSFET(s) is approximately 15mV. If the MOSFET(s) on resistance is so high as to prevent regula- tion, then GATE goes to compliance and the MOSFET(s) fully turns on. The inputs to the amplifier are V IN and OUT. The GATE pin sources current from VDD and sinks current to GND. The maximum GATE to VIN voltage is the lesser of VDD – 2.3V or 7.4V above V OUT or V IN (internal clamp voltage). The STATUS comparator, ST, pulls low when GATE ex- ceeds VIN by 0.7V. This occurs when VIN > OUT + 15mV. The STATUS pin pulls low as an indication that power is passing through the MOSFET(s). If VIN is greater than OUT by 0.21V and GATE > VIN + 7.4V or at compliance (GATE = V DD – 2.3V), STATUS will go high as an indication of a likely open MOSFET. FAULT will pull low in this state indicating the probable fault. The gate drive amplifier and STATUS function derive power from VDD. The circuit requires VDD > 2.5V. If VDD is present, the gate drive amplifier and STATUS are active independent of the state of V IN. If in a fault, GATE pulls

APPLICATIO S I FOR ATIOWU UU Setting Fault Thresholds The gate drive amplifier implements the ideal diode func- tion. The fault comparators (UV and OV) prevent out of range input voltages from affecting the output by disabling the amplifier during these conditions. Think of the UV and OV as gating the ideal diode function, something a regular diode can’t do. A resistive divider from V IN to UV and one from VIN to OV are the usual way of setting the FAULT thresholds. For UV the resistor values are set by: R UV I R V UV V R HYST UVHYST UV FAULT UV = ± · where UVHYST is the desired undervoltage hysteresis at the input. UVFAULT is the desired undervoltage trip voltage at the input. VUV is the part undervoltage trip point (0.3V) and IHYSTUV is the undervoltage hysteresis current (10mA). See Figure 1. The divider on the OV pin is a straightforward resistive divider (Figure 2): R OV V R R V R R Divider Current B FAULT OV A A AB = æ Łç ö where OVFAULT is the desired overvoltage trip point at the input and VOV is the OV pin threshold (0.3V). The OV pin has 7mV of voltage hysteresis at room. It is possible to do both dividers together using only three resistors though with more interdependence in compo- nents (Figure 3). The input bias current for UV and OV is less than 200nA, so keep resistor values less than 10k. UV IHYS 10µA VUV 300mV VIN UV TURNING ON UV TURNING OFF UV IHYS 10µA VUV 300mV

4351 F01

4351 F02

4351 F03

4351 F04

actively low. In the event of VDD collapse there still is an active pull-down (though of lesser strength) of GATE powered from OUT, guaranteeing turn off. The on-chip boost regulator uses a constant off-time control scheme. When V DD is below the regulation trip voltage, the switch turns on after a 600ns off-time. When the switch turns on current ramps up in the inductor until the current limit is reached (450mA). The switch turns off and the inductor’s current flows through the external diode to charge up the V DD capacitor. If VDD is still too low, the switch turns on again after a fixed off-time of 600ns. The boost regulator regulates VDD to approximately 10.7V above VIN. When VDD is above this level, the SW transistor turn-on is disabled. When VDD falls below this level by the hysteresis level, the SW transistor is allowed to turn on. There is approximately 0.15V of hysteresis. OPERATIOU

• ± · Hysteresis helps prevent erratic behavior due to the noise on VIN. Two of the most common noise sources are: VIN dipping when the MOSFETs first turn on and draw down the voltage on the V IN capacitors, and the boost regulator switch turning on and drawing current from the VIN capacitors. Use low ESR capacitors for VIN and OUT filtering. Note that because the UV pin uses current hysteresis, placing a capacitor on UV to ground to filter noise will reduce the effective hysteresis. Filtering can be achieved by splitting the R2 resistor as shown in Figure 4. To defeat undervoltage fault detection, the UV pin should be tied higher than 0.33V. UV can be tied to VIN provided VIN < 9V. Overvoltage fault detection can be defeated by grounding the OV pin. Do not exceed VIN. Boost Regulator The boost regulator will start working as soon as V IN is greater than 0.85V. The regulator will supply all the current for the gate drive amplifier. While the amplifier itself requires only about 3mA, larger current pulses are re- quired when charging the MOSFET gate. The reservoir capacitor on V DD will provide this current (Figure 6). OVERVOLTAGE FILTERED FAULT INPUT REFERRED OV REFERRED UV REFERRED VUV = 0.33V VUV = 0.3V VUV < 0.3VVOV > 0.3V VOV = 0.3V

4351 F05

Figure 5. Graphical Representation of the UV and OV Functions

4351 F06

which will continue to operate. reduce the noise due to inductive switching. Table 1. Recommended Inductors

breakdown when VIN or OUT are at their maximum value. Figure 8. VIN Capacitors rent pulses required for the gate driver. switching. Typically the average current will be under 10mA. back-to-back N-channel MOSFETs as the pass element.

4351 F08

sink current to signal the potential problem. ORing can be done either at the load or at the source. Figure 9. Redundant Backplane Supplies Figure 10

4351 F09

4351 F10

OUT voltage controls MOSFET turn on. or OUT, the GATE pin actively sinks low. all the time, which does not occur in normal practice. in Figure 12, representing a more typical situation. quency at which the gate is charged and discharged. power dissipation of a typical application at steady state. Figure 11. PBOOST(MAX) Figure 12. PBOOST(TYP)

4351 F11

4351 F12

(120°C/W) and P TOTAL is ascertained from the above. temperature rise above ambient. Two separate resistive dividers are used. Figure 14. Total Power (Typical)Figure 13. PGATE vs VIN (VDD = VIN + 10.7) The OV resistors are set as a straight resistive divider. schematic is shown in Figure 15.

4351 F13

4351 F14

Figure 15. 5V/5A Design Example through the MOSFETs should have low resistance.

4351 F15

1µF 10µF MBR0530MBR0530 365Ω RB 73.2k 10µH 12V LEAD-ACID BATTERY CHARGER LT4351 SW VDD STATUS FAULT GND Si4408DY 11 0 RA 1.5k 12.7k 0.1µF 220µF 10µF 10µF 10k 4351TA02 OUT LOAD 10k UVFAULT = 10.8V OVFAULT = 15V 14V POWER SUPPLY Lead Acid Battery Backup

1µF 1.69k R B 25.5k 1% LT4351 SW VDD STATUS FAULT GND 1ST SOURCE Si4838DY 10µF 11 0 RA 1.47k 24.9k 0.1µF 100µF 10µF 10µF

4351 TA03

5V Redundant Supply with External VDD

(Reference LTC DWG # 05-08-1661) MSOP (MS) 0603 0.53 – 0.152 (.021 – .006) SEATING PLANE 0.18 (.007) 1.10 (.043) MAX 0.17 – 0.27 (.007 – .011) TYP 0.127 – 0.076 (.005 – .003) 0.86 (.034) REF 0.50 (.0197) BSC 12 3 45 4.90 – 0.152 (.193 – .006) 0.497 – 0.076 (.0196 – .003) REF8910 7 6 3.00 – 0.102 (.118 – .004) (NOTE 3) 3.00 – 0.102 (.118 – .004) (NOTE 4) NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 0.254 (.010) 0° – 6° TYP DETAIL “A” DETAIL “A” GAUGE PLANE 5.23 (.206) MIN 3.20 – 3.45 (.126 – .136) 0.889 – 0.127 (.035 – .005) RECOMMENDED SOLDER PAD LAYOUT 0.305 – 0.038 (.0120 – .0015) TYP 0.50 (.0197) BSC Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 l FAX: (408) 434-0507 l www.linear.com ª LINEAR TECHNOLOGY CORPORATION 2003 LT/TP 1203 1K • PRINTED IN USA PART NUMBER DESCRIPTION COMMENTS LTC1473 Dual PowerPath TM Switch Driver Switches and Isolates Sources Up to 30V LTC4350 Hot Swappable Load Sharing Controller Output Voltage 1.2V to 12V, Equal Load Sharing LTC4412 Low Loss PowerPath Controller in ThinSOT TM P-Channel MOSFET, 3V to 28V Range PowerPath and ThinSOT are trademarks of Linear Technology Corporation. RELATED PARTS TYPICAL APPLICATIO U GATE OUTVIN UV OV 1µF MBR0530MBR0530 1.07k 10µH 12.6V BATTERY1 CHARGER LT4351 SW V DD STATUS FAULT GND Si4408DY 11 0 40.1k 0.1µF 10µF 100µF UVFAULT = 11.8V 10µF 10k 10k OUT 100k 10µF GATE OUTVIN UV OV 1µF MBR0530MBR0530 300k 10µH 1N914 12.6V BATTERY2 CHARGER LT4351 SW VDD STATUS FAULT GND POWER IS SWITCHED TO BATTERY2 WHEN BATTERY1 DROPS TO 11.8V Si4408DY 11 0 120k 10µF 0.1µF 10µF 10µF 10k 4351TA04 OUT 100µF 10k LOAD 100µF Primary Battery with Secondary Battery Backup