LT4275

LT4275 LINER

Document overview

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Technical content

The LT®4275 is a pin-for-pin compatible family of IEEE 802.3 and L TPoE++ powered device (PD) controllers. The LT4275A employs a proprietary L TPoE++ classification scheme, delivering 38.7W, 52.7W, 70W or 90W of power at the PD RJ45 connector. The LT4275A is fully compat- ible with IEEE 802.3. The LT4275B is an IEEE 802.3at compliant, Type 2 (PoE+) PD delivering up to 25.5W. The LT4275C is an IEEE 802.3af compliant, Type 1 (PoE) PD delivering up to 13W. The LT4275 internal charge pump provides an N-channel MOSFET solution, eliminating a larger and more costly P-channel MOSFET. A low R DS(ON) MOSFET also maxi- mizes power delivery and efficiency, reduces power and heat dissipation, and eases thermal design. Startup inrush current is adjustable with an external capacitor. The LT4275 also includes a power good output, on-board signature resistor, undervoltage lockout, and thermal protection. The LT4275A/LT4275B drives a single opto-coupler to indicate the power level of the attached PSE. Pin-selectable sup- port for non-standard low voltage operation is provided. Auxiliary power override is supported with the AUX pin. The LT4275A can be configured to support all possible L TPoE++, 802.3at and 802.3af power levels with external component changes. L, LT, LT C, LT M, Linear Technology and the Linear logo are registered trademarks and L TPoE++ and Hot Swap are trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. L TPoE++ 90W Powered Device Interface

applicaTions

n IEEE 802.3af/at and L TPoE++™ Powered Device (PD) Controller n L TPoE++ Supports Power Levels Up to 90W n LT4275A Supports All of the Following Standards: n L TPoE++ 38.7W, 52.7W, 70W and 90W n IEEE 802.3at 25.5W Compliant n IEEE 802.3af Up to 13W Compliant n LT4275B is IEEE 802.3at/af Compliant n LT4275C is IEEE 802.3af Compliant n 100V Absolute Maximum Input Voltage n Wide Junction Temperature Range (–40°C to 125°C) n Overtemperature Protection n Integrated Signature Resistor n External Hot Swap™ N-Channel MOSFET for Lowest Power Dissipation and Highest System Efficiency n Programmable Aux Power Support as Low as 9V n Optional Support of Non-Standard Low Voltage PoE n Available in 10-Lead MSOP and 3mm × 3mm DFN Packages n High Power Wireless Data Systems n Outdoor Security Camera Equipment n Commercial and Public Information Displays n High Temperature Industrial Applications LT4275 Family MAX DELIVERED POWER LT4275 GRADE A B C L TPoE++ 90W l L TPoE++ 70W l L TPoE++ 52.7W l L TPoE++ 38.7W l 25.5W l l 13W l l l L T4275A VPORT HSGATE GND

4275 TA01a

0.1µFVPORT DATA PAIR SPARE PAIR RUN 47nF 3.3k FDMC86102 VIN VOUT ISOLATED POWER SUPPL Y OPTO PSE TYPE (TO µP) CPORT VAUX (9V TO 60V)

IEEEUVLO, RCLASS, RCL 0.3V to 8V (and ≤ VPORT) .4mA 0.3V to 100V (Notes 1, 3) orDer inForMaTion LEAD FREE FINISH TAPE AND REEL PART MARKING* MAX PD POWER PACKAGE DESCRIPTION TEMPERATURE RANGE LT4275AIDD#PBF LT4275AIDD#TRPBF LGBS 90W 10-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C LT4275AHDD#PBF LT4275AHDD#TRPBF LGBS 90W 10-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C LT4275AIMS#PBF LT4275AIMS#TRPBF L TGBT 90W 10-Lead Plastic MSOP –40°C to 85°C LT4275AHMS#PBF LT4275AHMS#TRPBF L TGBT 90W 10-Lead Plastic MSOP –40°C to 125°C LT4275BIDD#PBF LT4275BIDD#TRPBF LGBV 25.5W 10-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C LT4275BHDD#PBF LT4275BHDD#TRPBF LGBV 25.5W 10-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C LT4275BIMS#PBF LT4275BIMS#TRPBF L TGBW 25.5W 10-Lead Plastic MSOP –40°C to 85°C LT4275BHMS#PBF LT4275BHMS#TRPBF L TGBW 25.5W 10-Lead Plastic MSOP –40°C to 125°C LT4275CIDD#PBF LT4275CIDD#TRPBF LGBX 13W 10-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C LT4275CHDD#PBF LT4275CHDD#TRPBF LGBX 13W 10-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C LT4275CIMS#PBF LT4275CIMS#TRPBF L TGBY 13W 10-Lead Plastic MSOP –40°C to 85°C LT4275CHMS#PBF LT4275CHMS#TRPBF L TGBY 13W 10-Lead Plastic MSOP –40°C to 125°C Consult LT C Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LT C Marketing for information on nonstandard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ TOP VIEW GND DD PACKAGE 10-LEAD (3mm × 3mm) PLASTIC DFN

1 VPORT

T2P/NC* IEEEUVLO AUX RCLASS RCLASS++/NC* GND TJMAX = 150°C, θJC = 5°C/W EXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB GND IEEEUVLO AUX RCLASS RCLASS++/NC* GND VPORT HSGATE HSSRC PWRGD T2P/NC* TOP VIEW MS PACKAGE 10-LEAD PLASTIC MSOP TJMAX = 150°C, θJC = 45°C/W * RCLASS++ is not connected in the LT4275B/C versions. T2P is not connected in the LT4275C version. pin conFiguraTion Operating Junction Temperature Range (Note 4) 40°C to 85°C 40°C to 125°C 65°C to 150°C 0°C

elecTrical characTerisTics

Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: Signature resistance specifications do not include resistance added by the external diode bridge which can add as much as 1.1k to the port resistance. The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VPORT Operating Input Voltage At VPORT Pin l 23 60 V VSIG VPORT Signature Range At VPORT Pin l 1.5 10 V VCLASS VPORT Classification Range At VPORT Pin l 12.5 21 V VMARK VPORT Mark Range At VPORT Pin, Preceded by VCLASS l 5.6 10 V VPORT Aux Mode Range At VPORT Pin, AUX > VAUXT l 8 60 V Signature/Class Hysteresis Window l 1.0 V VRESET Reset Threshold l 2.6 5.6 V VHSON Hot Swap Turn-On Voltage IEEEUVLO = 0V IEEEUVLO Open l l V V V HSOFF Hot Swap Turn-Off Voltage IEEEUVLO = 0V IEEEUVLO Open l l 21.5 22.5 V V Hot Swap On/Off Hysteresis Window l 3 V Supply Current Supply Current VPORT = HSSRC = 57V l 2 mA Supply Current During Classification VPORT = 17.5V, RCLASS and RCLASS ++ Open l 0.4 0.7 1.1 mA Supply Current During Mark Event V MARK l 0.5 2.2 mA Signature and Classification Signature Resistance VSIG (Note 2) l 23.7 24.4 25.2 kΩ Signature Resistance During Mark Event V MARK (Note 2) l 5.8 8.3 11 kΩ VRCLS RCLASS/RCLASS++ Operating Voltage –10mA ≥ I RCLASS ≥ –36mA, VCLASS l 1.32 1.40 1.43 V Classification Stability Time VPORT Step to 17.5V, RCLASS = 34.8Ω l 2 ms Analog/Digital Interface VAUXT AUX Threshold l 6.1 6.3 6.5 V IAUXH AUX Pin Hysteresis Current AUX = 6.1V l 4 5.8 8 µA T2P Output Low 1mA Load (LT4275A/LT4275B Only) l 0.8 V PWRGD Output Low 1mA Load l 0.8 V PWRGD Leakage Current PWRGD = 60V l 5 µA T2P Leakage Current T2P = 60V l 5 µA Hot Swap Control I GPU HSGATE Pull-Up Current VHSGATE – VHSSRC = 5V, VPORT > 42V, Out of Pin l 18 22 27 µA VGOC HSGATE Open Circuit Voltage VHSGATE – VHSSRC, 0µA to 10µA Load with Respect to HSSRC l 10 18 V HSGATE Pull-Down Current VHSGATE – VHSSRC = 5V l 200 µA Timing f T2P T2P Frequency After PWRGD Valid, if L TPoE++ PSE Is Mutually Identified l 690 840 990 Hz Note 3: All voltages with respect to GND unless otherwise noted. Positive currents are into pins; negative currents are out of pins unless otherwise noted. Note 4: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 150°C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability.

Typical perForMance characTerisTics Signature Resistance vs Input Voltage VPORT Hot Swap Thresholds Reset Threshold PWRGD, T2P Output Low Voltage vs Current VPORT Classification Thresholds T2P Frequency VPORT Current vs VPORT Voltage 25k Detection Range VPORT Hot Swap Thresholds Supply Current During Power-On VPORT VOL TAGE (V) VPORT CURRENT (mA) 0.2 0.3 0.4 0.5 0.1

4275 G01

T = –40°C T = 25°C T = 75°C T = 125°C TEMPERATURE (°C) –50 VPORT VOL TAGE (V)32 100

4275 G02

12575–25 50 25 0 IEEEUVLO = 0V Hot Swap OFF Hot Swap ON VPORT VOL TAGE (V) SUPPL Y CURRENT (mA) 1.0 1.5 2.0 0.5

4275 G03

T = –40°C T = 25°C T = 75°C T = 125°C VPORT VOL TAGE (V) SIGNATURE RESISTANCE (k/uni03A9) 25.25 25.75 26.25 24.75 24.25 23.75

4275 G04

T = –40°C T = 25°C T = 75°C T = 125°C TEMPERATURE (°C) –50 VPORT VOL TAGE (V) 24.5 26.0 27.5 29.0 23.0 21.5 100

4275 G05

12575–25 50 25 0 IEEEUVLO = FLOAT Hot Swap OFF Hot Swap ON TEMPERATURE (°C) –50 VPORT VOL TAGE (V)3.6 4.1 5.1 4.6 5.6 3.1 2.6 100

4275 G06

12575–25 50 25 0 CURRENT (mA) VOL TAGE (V)

4275 G07

T = –40°C T = 25°C T = 75°C T = 125°C TEMPERATURE (°C) –50 VPORT VOL TAGE (V) 11.0 11.5 12.0 12.5 10.5 10.0 100

4275 G08

12575–25 50 25 0 DETECT OR MARK TO CLASS CLASS TO MARK TEMPERATURE (°C) –50 T2P FREQUENCY (Hz) 840 740 890 940 990 790 690 100

4275 G09

12575–25 50 25 0

IEEEUVLO (Pin 1): Hot Swap Turn-on Threshold Level Control. Connect to ground for IEEE compliant turn-on and turn-off (UVLO) voltage thresholds. Leave open for lower turn-on and turn-off voltage thresholds. AUX (Pin 2): Auxiliary Sense. Assert AUX via a resistive divider from the auxiliary power input to set the voltage at which the auxiliary supply takes over. Asserting AUX pulls down HSGATE, disconnects the signature resistor, disables classification and floats the PWRGD pin. The AUX pin sinks IAUXH when below its threshold voltage of VAUXT to provide hysteresis. Tie to GND when not used. RCLASS (Pin 3): Programmable PoE Classification Resis- tor. See Table 1. RCLASS ++ ( Pin 4, LT4275A Only): Programmable L TPoE++ Classification Resistor. This pin is not connected on the LT4275B/LT4275C. See Table 1. GND (Pin 5): Ground Pin. Must be soldered to PCB GND. T2P (Pin 6, LT4275A/LT4275B Only): PSE Type Indica- tor, Open-Drain Output. T2P floats for a 13W PSE. T2P pulls down for a 25.5W PSE. T2P pulls down at f T2P with a 50% (typical) duty cycle to indicate the presence of an L TPoE++ PSE. T2P is valid after PWRGD is active. This pin is not connected on the LT4275C. See the Applications Information section for behavior when using the AUX pin. PWRGD (Pin 7): Power Good Indicator, Open-Drain Output. Pulls down during VCLASS and inrush. HSSRC (Pin 8): External Hot Swap MOSFET Source. Con- nect to source of the external MOSFET. HSGATE (Pin 9): External Hot Swap MOSFET Gate Control, Output. Connect to gate of the external MOSFET. VPORT (Pin 10): PD interface upper power rail and external Hot Swap MOSFET drain connection. Exposed Pad (Pin 11, DFN Package Only): GND. Must be soldered to PCB GND. block DiagraM 4275 BD CONTROL LOGIC CLASSIFICATION LOGIC VOL TAGE AND CURRENT REFERENCES CHARGE PUMP OVERTEMP ON GND VPORT VPORT VGOC 6.3V 1.4V 1.4V EN EN VPORT VPORT AUX RCLASS RCLASS++ T2P HSSRC HSGATE PWRGD IEEEUVLO

on the input voltage sequence applied to the VPORT pin. tion, mark, inrush and powered on. a ∆V/∆I measurement technique. resistance introduced by the IEEE required bridge. down and floating T2P at a rate of fT2P. Figure 1. Type 1 Detect/Class Signaling Waveform Figure 2. Type 2 Detect/Class Signaling Waveform

4275 F01

Table 1. Classification Codes, Power Levels and Resistor Selection *An L TPoE++ PD will be classified as class 4 by an IEEE 802.3 compliant PSE. by extending the classification signaling of IEEE 802.3. will classify an L TPoE++ PD as a Type 2 PD. port as required by the IEEE specification. inrush current (IINRUSH in Figure 3).

4275 F03

Figure 3. Programming IINRUSH dissipation, and eases thermal design. HSGATE charges up to approximately 7V above HSSRC. HSOFF or the AUX pin is above VAUXT. LT4275A when the RCLS++ resistor is present.

and VAUXOFF via R1 and R2 in Figure 4. Figure 4. AUX Threshold and Hysteresis Calculation 100V and is designed to tolerate brief overvoltage events. and GND. This TVS must be mounted near the LT4275. contact Linear Technology Applications. of RCLS++ from Table 1 in addition to RCLS. the CPORT capacitor is fully charged. on the printed circuit board. LT4275A, place RCLS++ nearby as well. close to the LT4275 as possible.

4275 F04

if this condition persists abnormally. an input impedance requirement in IEEE 802.3.

IEEE 802.3af (Type 1) 13W Powered Device L T4275A/L T4275B/L T4275C VPORT HSGATE GND

4275 TA02

0.1µF RUN 47nF 3.3k FDN8601 SMAJ58A VIN VOUT ISOLATED POWER SUPPL Y ETHERNET MAGNETICS CPORT VPORT L T4275A/L T4275B VPORT HSGATE GND

4275 TA03

0.1µF RUN 47nF 3.3k FDN8601 SMAJ58A VIN VOUT ISOLATED POWER SUPPL Y OPTO PSE TYPE (TO µP) ETHERNET MAGNETICS CPORT VPORT IEEE 802.3at (Type 2) 25.5W Powered Device L TPoE++ 38.7W to 90W Powered Device L T4275A VPORT HSGATE GND

4275 TA04

0.1µF RUN 47nF 3.3k FDMC86102 SMAJ58A VIN VOUT ISOLATED POWER SUPPL Y OPTO PSE TYPE (TO µP) WÜRTH 749022016 CPORT VPORT

10-Lead Plastic DFN (3mm × 3mm) (Reference L TC DWG # 05-08-1699 Rev C) Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. 3.00 ±0.10 (4 SIDES) NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2). CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 0.40 ±0.10 BOTTOM VIEW—EXPOSED PAD 1.65 ±0.10 (2 SIDES) 0.75 ±0.05 R = 0.125 TYP 2.38 ±0.10 (2 SIDES) 106 PIN 1 TOP MARK (SEE NOTE 6)

0.200 REF

0.00 – 0.05 (DD) DFN REV C 0310 0.25 ±0.05 2.38 ±0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 1.65 ±0.05 (2 SIDES)2.15 ±0.05 0.50 BSC 0.70 ±0.05 3.55 ±0.05 PACKAGE OUTLINE 0.25 ±0.05

0.50 BSC

10-Lead Plastic DFN (3mm × 3mm) (Reference LTC DWG # 05-08-1699 Rev C) PIN 1 NOTCH R = 0.20 OR 0.35 × 45° CHAMFER

Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package DescripTion 10-Lead Plastic MSOP (Reference L TC DWG # 05-08-1661 Rev E) Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. MSOP (MS) 0307 REV E 0.53 ± 0.152 (.021 ± .006) SEATING PLANE 0.18 (.007) 1.10 (.043) MAX 0.17 –/uni00A00.27 (.007 – .011) TYP 0.86 (.034) REF 0.50 (.0197) BSC 1 2 3 4 5 4.90 ± 0.152 (.193 ± .006) 0.497 ± 0.076 (.0196 ± .003) REF8 9 107 6 3.00 ± 0.102 (.118 ± .004) (NOTE 3) 3.00 ± 0.102 (.118 ± .004) (NOTE 4) NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 0.254 (.010) 0° – 6° TYP DETAIL “A” DETAIL “A” GAUGE PLANE 5.23 (.206) MIN 3.20 – 3.45 (.126 – .136) 0.889 ± 0.127 (.035 ± .005) RECOMMENDED SOLDER PAD LAYOUT 0.305 ± 0.038 (.0120 ± .0015) TYP 0.50 (.0197) BSC 0.1016 ± 0.0508 (.004 ± .002)

Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear .com  LINEAR TECHNOLOGY CORPORA TION 2012 LT 0712 • PRINTED IN USA relaTeD parTs Typical applicaTion PART NUMBER DESCRIPTION COMMENTS LTC4257-1 IEEE 802.3af PD Interface Controller Internal 100V, 400mA Switch, Dual Current Limit, Programmable Class LTC4263 Single IEEE 802.3af PSE Controller Internal FET Switch LTC4265 IEEE 802.3at PD Interface Controller Internal 100V, 1A Switch, 2-Event Classification Recognition LTC4266 Quad IEEE 802.3at PoE PSE Controller With Programmable I CUT/ILIM, 2-Event Classification LTC4266A Quad L TPoE ++ PSE Controller Provides Up to 90W. Backwards Compatible with IEEE 802.3af and IEEE 802.3at PDs. With Programmable ICUT/ILIM, 2-Event Classification LTC4266C Quad IEEE 802.3af PSE Controller With Programmable ICUT/ILIM, 1-Event Classification LTC4267-3 IEEE 802.3af PD Interface with Integrated Switching Regulator Internal 100V, 400mA Switch, Programmable Class, 300kHz Constant Frequency PWM LTC4269-1 IEEE 802.3af PD Interface with Integrated Flyback Switching Regulator 2-Event Classification, Programmable Class, Synchronous No-Opto Flyback Controller, 50kHz to 250kHz, Aux Support LTC4269-2 IEEE 802.3af PD Interface with Integrated Forward Switching Regulator 2-Event Classification, Programmable Class, Synchronous Forward Controller, 100kHz to 500kHz, Aux Support LTC4270/LTC4271 12-Port PoE/PoE+/L TPoE++ PSE Controller T ransformer Isolation, Supports IEEE 802.3af, IEEE 802.3at and L TPoE ++ PDs LTC4274 Single IEEE 802.3at PoE PSE Controller With Programmable I CUT/ILIM, 2-Event Classification LTC4274A Single L TPoE ++ PSE Controller Provides Up to 90W. Backwards Compatible with IEEE 802.3 PDs. With Programmable I CUT/ILIM, 2-Event Classification LTC4274C Single IEEE 802.3af PSE Controller With Programmable I CUT/ILIM, 1-Event Classification LTC4278 IEEE 802.3af PD Interface with Integrated Flyback Switching Regulator 2-Event Classification, Programmable Class, Synchronous No-Opto Flyback Controller, 50kHz to 250kHz, 12V Aux Support LTC4290/LTC4271 8-Port PoE/PoE+/L TPoE++ PSE Controller T ransformer Isolation, Supports IEEE 802.3af, IEEE 802.3at and L TPoE ++ PDs 25W PD Solution with 12VDC and 24VAC Auxiliary Input L T4275A/L T4275B VPORT HSGATE

4275 TA05

34.8/uni03A9 931k SMAJ58A 158k 47nF 3.3k FDN8601 MMSD4148 MMSD4148 (2plcs) B2100 (4plcs) OPTO PSE TYPE (TO µP) TO ISOLATED POWER SUPPL Y RUN TO ISOLATED POWER SUPPL Y 8.2Ω 0.1µF 0.1µF 470µF VAUX 9V TO 57VDC OR 24VAC WÜRTH 7499511001 1–12 TO PHY B2100 (8plcs)