LT4250L LINER
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ID (Q1) 5A/DIV 500µs/DIV FEATURES DESCRIPTIO U APPLICATIO SU TYPICAL APPLICATIO U Negative 48V Hot Swap Controller n Allows Safe Board Insertion and Removal from a Live – 48V Backplane n Circuit Breaker Immunity to Voltage Steps and Current Spikes n Programmable Inrush and Short-Circuit Current Limits n Pin Compatible with LT1640L/LT1640H n Operates from –20V to – 80V n Programmable Overvoltage Protection n Programmable Undervoltage Lockout n Power Good Control Output n Bell-Core Compatible ON/OFF Threshold The LT 4250L/LT4250H are 8-pin, negative 48V Hot Swap TM controllers that allow a board to be safely inserted and removed from a live backplane. Inrush current is limited to a programmable value by controlling the gate voltage of an external N-channel pass transistor. The pass transistor is turned off if the input voltage is less than the program- mable undervoltage threshold or greater than the over- voltage threshold. A programmable current limit protects the system against shorts. After a 500 ms timeout the current limit activates the electronic circuit breaker. The PWRGD (LT4250L) or PWRGD (LT4250H) signal can be used to directly enable a power module. The LT4250L is designed for modules with a low enable input and the LT4250H for modules with a high enable input. The LT4250L/LT4250H are available in 8-pin PDIP and SO packages. n Central Office Switching n – 48V Distributed Power Systems n Negative Power Supply Control Hot Swap is a trademark of Linear Technology Corporation. , LTC and LT are registered trademarks of Linear Technology Corporation. Voltage Step On Input Supply VEE VDD LT4250L SENSE C1† 470nF 25V C2† 15nF 100V 0.1mF 100V 100mF 100V IRF530 10W R3† 1k, 5% R4† 549k R6† 10k R1† 0.02W OV –48V RTN –48V RTN (SHORT PIN) OV = 71V * DIODES INC. SMAT70A † THESE COMPONENTS ARE APPLICATION SPECIFIC AND MUST BE SELECTED BASED UPON OPERATING CONDITIONS AND DESIRED PERFORMANCE. SEE APPLICATIONS INFORMATION. UV = 38.5V UV GATE DRAIN PWRGD
4250 TA01
SENSE– VOUT–VIN– ON/OFF LUCENT JW050A1-E VIN+ 9 5V + C5 100mF 16V –48V INPUT 1 –48V INPUT 2 UV RELEASE AT 43V 6.49k 0.1µF 10V
ABSOLUTE MAXIMUM RATINGSW WW U Operating Temperature Range (Note 1), All Voltages Referred to VEE ELECTRICAL CHARACTERISTICSThe l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 2), VDD = 48V, VEE = 0V unless otherwise noted. WU UPACKAGE/ORDER I FOR ATIO ORDER PART NUMBER S8 PART MARKING LT4250LCN8 LT4250LCS8 LT4250LIN8 LT4250LIS8 4250L 4250LI TJMAX = 125°C, qJA = 120°C/W (N8) TJMAX = 125°C, qJA = 150°C/W (S8) TOP VIEW VDD DRAIN GATE SENSE PWRGD OV UV V EE N8 PACKAGE 8-LEAD PDIP S8 PACKAGE 8-LEAD PLASTIC SO ORDER PART NUMBER S8 PART MARKING LT4250HCN8 LT4250HCS8 LT4250HIN8 LT4250HIS8 4250H 4250HI TJMAX = 125°C, qJA = 120°C/W (N8) TJMAX = 125°C, qJA = 150°C/W (S8) TOP VIEW VDD DRAIN GATE SENSE PWRGD OV UV V EE N8 PACKAGE 8-LEAD PDIP S8 PACKAGE 8-LEAD PLASTIC SO Consult LTC Marketing for parts specified with wider operating temperature ranges. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS DC VDD Supply Voltage Operating Range l 20 80 V IDD Supply Current UV = 3V, OV = V EE, SENSE = VEE l 1.6 5 mA VUVL Undervoltage Lockout l 15.4 V VCL Current Limit Trip Voltage V CL = (VSENSE – VEE) l 40 50 60 mV IPU GATE Pin Pull-Up Current Gate Drive On, V GATE = VEE l –3 0 –4 5 –6 0 mA IPD GATE Pin Pull-Down Current Gate Drive OFF 24 50 70 mA ISENSE SENSE Pin Current V SENSE = 50mV – 20 mA DVGATE External Gate Drive (V GATE – VEE), 20V £ VDD £ 80V l 10 13.5 18 V VUVH UV Pin High Threshold Voltage UV Increasing l 1.240 1.255 1.270 V VUVL UV Pin Low Threshold Voltage UV Decreasing l 1.105 1.125 1.145 V VUVHY UV Pin Hysteresis 130 mV IINUV UV Pin Input Current V UV = VEE l – 0.02 – 0.5 mA VOVH OV Pin High Threshold Voltage OV Increasing l 1.235 1.255 1.275 V VOVL OV Pin Low Threshold Voltage OV Decreasing l 1.210 1.235 1.255 V
ELECTRICAL CHARACTERISTICSThe l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 2), VDD = 48V, VEE = 0V unless otherwise noted. TYPICAL PERFOR A CE CHARACTERISTICS UW SUPPLY VOLTAGE (V) SUPPLY CURRENT (mA) 1.3 1.4 1.5 60 100
1640 G01
1.2 1.1 20 40 80 1.6 1.7 1.8 TA = 25°C Supply Current vs Supply Voltage TEMPERATURE (°C) –50 –25 1.0 SUPPLY CURRENT (mA) 1.1 1.2 1.3 1.4 1.6 02 5 5 0 7 5
1640 G02
1.5 VDD = 48V Supply Current vs Temperature SUPPLY VOLTAGE (V) GATE VOLTAGE (V) 40 80 100
1640 G03
TA = 25°C Gate Voltage vs Supply Voltage SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VOVHY OV Pin Hysteresis 20 mV IINOV OV Pin Input Current V OV = VEE l – 0.03 –0.5 mA VDL DRAIN Low Threshold V DRAIN – VEE, DRAIN Decreasing 1.1 1.6 2.3 V VGH GATE High Threshold DVGATE – VGATE Decreasing 1.3 V IDRAIN Drain Input Bias Current V DRAIN = 48V l 10 80 500 mA VOL PWRGD Output Low Voltage PWRGD (LT4250L), (V DRAIN – VEE) < VDL IOUT = 1mA l 0.48 0.8 V IOUT = 5mA l 1.2 3.0 V PWRGD Output Low Voltage PWRGD (LT4250H), V DRAIN = 5V (PWRGD – DRAIN) I OUT = 1mA l 0.75 1.0 V IOH Output Leakage PWRGD (LT4250L), V DRAIN = 48V, VPWRGD = 80V l 0.05 10 mA PWRGD (LT4250H), VDRAIN = 0V, VPWRGD = 80V l 0.05 10 mA AC tPHLOV OV High to GATE Low Figures 1a, 2 1.7 ms tPHLUV UV Low to GATE Low Figures 1a, 3 1.5 ms tPLHOV OV Low to GATE High Figures 1a, 2 5.5 ms tPLHUV UV High to GATE High Figures 1a, 3 6.5 ms tPHLSENSE SENSE High to Gate Low Figures 1a, 4a 1 3 ms tPHLCB Current Limit to GATE Low Figures 1b, 4b 500 ms tPHLDL DRAIN Low to PWRGD Low (LT4250L) Figures 1a, 5a 1 ms DRAIN Low to (PWRGD – DRAIN) High (LT4250H) Figures 1a, 5a 1 ms tPHLGH GATE High to PWRGD Low (LT4250L) Figures 1a, 5b 1.5 ms GATE High to (PWRGD – DRAIN) High (LT4250H) Figures 1a, 5b 1.5 ms Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to VEE unless otherwise specified.
TYPICAL PERFOR A CE CHARACTERISTICS UW Gate Voltage vs Temperature TEMPERATURE (°C) 12.0 GATE VOLTAGE (V)13.0 14.0 15.0 12.5 13.5 14.5 –25 0 75
1640 G04
100–50 25 50 VDD = 48V TEMPERATURE (°C) –50 TRIP VOLTAGE (mV) 250 50
1640 G05
100–25 75 TEMPERATURE (°C) –50 GATE PULL-UP CURRENT (mA)
1640 G06
–25 100 50250 VGATE = 0V Gate Pull-Up Current vs Temperature Gate Pull-Down Current vs Temperature TEMPERATURE (°C) –50 GATE PULL-DOWN CURRENT (mA)
1640 G07
–25 0 25 50 100 VGATE = 2V PWRGD Output Low Voltage vs Temperature (LT4250L) TEMPERATURE (°C) –50 PWRGD OUTPUT LOW VOLTAGE (V) 0.3 0.4 0.5
1640 G08
0.2 0.1 –25 25 0 50 100 IOUT = 1mA TEMPERATURE (°C) –50 OUTPUT IMPEDANCE (kW ) –25 25 05 0 7 5
1640 G09
VDRAIN – VEE > 2.4V PWRGD Output Impedance vs Temperature (LT4250H) Current Limit Trip Voltage vs Temperature This condition is latched until the GATE pin is turned off via the UV, OV, UVLO or the electronic circuit breaker. When the DRAIN pin of the LT4250H is above VEE by more than VDL or V GATE is more than V GH from DVGATE, the PWRGD pin will sink current to the DRAIN pin which pulls the module’s enable pin low, forcing it off. When VDRAIN drops below VDL and VGATE rises above VGH, the PWRGD sink current is turned off, allowing the module’s pull-up current to pull the enable pin high and turn on the module. This condition is latched until the GATE pin is turned off via the UV, OV, UVLO or the electronic circuit breaker. PIN FUNCTIONSUU U PWRGD/PWRGD (Pin 1): Power Good Output Pin. This pin will latch a power good indication when VDRAIN is within VDL of VEE and VGATE is within VGH of DVGATE. This pin can be connected directly to the enable pin of a power module. When the DRAIN pin of the LT4250L is above VEE by more than VDL or VGATE is more than V GH from DVGATE, the PWRGD pin will be high impedance, allowing the pull-up current of the module’s enable pin to pull the pin high and turn the module off. When V DRAIN drops below V DL and VGATE rises above VGH, the PWRGD pin sinks current to VEE, pulling the enable pin low and turning on the module.
OV (Pin 2): Analog Overvoltage Input. When OV is pulled above the 1.255V threshold, an overvoltage condition is detected and the GATE pin will be immediately pulled low. The GATE pin will remain low until OV drops below the 1.235V threshold. UV (Pin 3): Analog Undervoltage Input. When UV is pulled below the 1.125V threshold, an undervoltage condition is detected and the GATE pin will be immedi- ately pulled low. The GATE pin will remain low until UV rises above the 1.255 threshold. The UV pin is also used to reset the electronic circuit breaker. If the UV pin is cycled low and high following the trip of the circuit breaker, the circuit breaker is reset and a normal power-up sequence will occur. The response time for this pin is 1.5ms. Add an external capacitor to this pin for additional filtering. V EE (Pin 4): Negative Supply Voltage Input. Connect to the lower potential of the power supply. SENSE (Pin 5): Circuit Breaker Sense Pin. With a sense resistor placed in the supply path between V EE and SENSE, the overcurrent condition will pull down the GATE pin and regulate the voltage across the resistor to be 50mV. If the overcurrent condition exists for more than 500ms the electronic circuit breaker will trip and turn off the external MOSFET. If the current limit value is set to twice the normal operating current, only 25mV is dropped across the sense resistor during normal operation. To disable the current limit feature, V EE and SENSE can be shorted together. GATE (Pin 6): Gate Drive Output for the External N-Channel MOSFET. The GATE pin will go high when the following start-up conditions are met: the UV pin is high, the OV pin is low, (V SENSE – VEE) < 50mV and the VDD pin is greater than VUVLOH. The GATE pin is pulled high by a 45mA current source and pulled low with a 50mA current source. During current limit the GATE pin is pulled low using a 100mA current source. DRAIN (Pin 7): Analog Drain Sense Input. Connect this pin to the drain of the external N-channel MOSFET and the V– pin of the power module. When the DRAIN pin is below VDL, the PWRGD/PWRGD pin will latch to indicate the switch is on. VDD (Pin 8): Positive Supply Voltage Input. Connect this pin to the higher potential of the power supply inputs and the V + pin of the power module. An undervoltage lockout circuit disables the chip until the VDD pin is greater than the 16V VUVLOH threshold. BLOCK DIAGRA W DRAIN 4250 BD GATESENSEVEE VEE VDL OUTPUT DRIVE PWRGD/PWRGD 50mV VCC VDD REF REF UV OV LOGIC VCC AND REFERENCE GENERATOR ∆VGATE VGH 500µs DELAY GATE DRIVER UVLO
1640 F01a
4250 F02
Figure 2. OV to GATE Timing
4250 F03
Figure 3. UV to GATE Timing
4250 F04a
4250 F04b
4250 F01b
4250 F05bVPWRGD – VDRAIN = 0
4250 F05aVPWRGD – VDRAIN = 0V
APPLICATIONS INFORMATIONWU UU Hot Circuit Insertion When circuit boards are inserted into a live – 48V backplane, the bypass capacitors at the input of the board’s power module or switching power supply can draw huge tran- sient currents as they charge up. The transient currents can cause permanent damage to the board’s components and cause glitches on the system power supply. The LT4250 is designed to turn on a board’s supply voltage in a controlled manner, allowing the board to be safely inserted or removed from a live backplane. The chip also provides undervoltage, overvoltage and overcurrent protection while keeping the power module off until its input voltage is stable and within tolerance. Power Supply Ramping The input to the power module on a board is controlled by placing an external N-channel pass transistor (Q1) in the power path (Figure 6a, all waveforms are with respect to the V EE pin of the LT4250). R1 provides current fault detection and R2 prevents high frequency oscillations. Resistors R4, R5 and R6 provide undervoltage and over- voltage sensing. By ramping the gate of Q1 up at a slow rate, the inrush current charging load capacitors C3 and C4 can be limited to a safe value when the board makes connection. Resistor R3 and capacitor C2 act as a feedback network to accurately control the inrush current. The C2 capacitor can be calculated with the following equation: C2 = (45mA • C L)/IINRUSH where CL is the total load capacitance = C3 + C4 + module input capacitance. Capacitor C1 and resistor R3 prevent Q1 from momen- tarily turning on when the power pins first make contact. Without C1 and R3, capacitor C2 would pull the gate of Q1 up to a voltage roughly equal to V EE • C2/CGS(Q1) before the LT4250 could power up and actively pull the gate low. By placing capacitor C1 in parallel with the gate capacitance of Q1 and isolating them from C2 using resistor R3 the problem is solved. The value of C1 is given by: C VV V CCINMAX TH TH GD12= -æ Łç ö ł÷ •+() C1@ 35 • C2 for VINMAX = 72V where VTH is the MOSFET’s minimum gate threshold and VINMAX is the maximum operating input voltage. R3 should not exceed a value that produces an R3 • C2 time-constant of 150 ms. A 1k value for R3 will ensure this for C2 values up to 150nF. The waveforms are shown in Figure 6b. When the power pins make contact, they bounce several times. While the contacts are bouncing, the LT4250 senses an undervoltage condition and the GATE is immediately pulled low when the power pins are disconnected. Once the power pins stop bouncing, the GATE pin starts to ramp up. When Q1 turns on, the GATE voltage is held constant by the feedback network of R3 and C2. When the DRAIN voltage has finished ramping, the GATE pin then ramps to its final value. Figure 6a. Inrush Control Circuitry VEE VDD LT4250H PWRGD UV = 38.5V OV = 71V SENSE 470nF 25V 0.1mF 100V 100mF 100V C5 100mF 16V IRF530 10W 1k, 5% 15nF 100V 549k 6.49k 10k 0.02W OV –48V RTN –48V RTN (SHORT PIN) –48V UV GATE DRAIN VICOR VI-J30-CY VOUT+ VOUT– VIN+ 5V
4250 F06a
VIN– * DIODES INC. SMAT70A Figure 6b. Inrush Control Waveforms INRUSH CURRENT 500mA/DIV GATE –VEE 10V/DIV DRAIN 50V/DIV VEE 50V/DIV 25ms/DIV
4250 F06b
combined with the minimum trip voltage (40mV). MOSFET current is limited to 50mV/RSENSE (see Figure 7). deactivate and release the GATE. Figure 7. Short-Circuit Protection Waveforms current and the dynamic current in the load capacitance. resistor and diode, Q1 remains on during the voltage step. recover before the UV pin resets the circuit breaker.
Figure 10. Automatic Restart After Current Fault Figure 9. Circuit for Input Steps with Small C2 (<10nF) Figure 8. Voltage Step on cycle is set to 10% to prevent Q1 from overheating.
4250 F09
4250 F10a
4250 F11
4250 F12
PWRGD pin one SAT drop (» 0.3V) above the DRAIN pin. the PWRGD pin will pull low, enabling the module. Figure 11. With R4 = 549k, R5 = 6.49k and R6 = 10K, the Figure 12. Active High Enable ModuleFigure 11. Undervoltage and Overvoltage Sensing
Figure 14. Using PWRGD to Drive an OptoisolatorFigure 13. Active Low Enable Module Information furnished by Linear Technology Corporation is believed to be accurate and reliable. tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. *THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
4250 F13
4250 F14
1421 Dual Hot Swap Controller with Additional –12V Control Operates from 3V to 12V
Figure 15. When using a filter, an optoisolator is required Figure 15. Typical Application Using a Filter Module