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The L TC®4252 negative voltage Hot Swap TM controller allows a board to be safely inserted and removed from a live backplane. Output current is controlled by three stages of current limiting: a timed circuit breaker , active current limiting and a fast feedforward path that limits peak current under worst-case catastrophic fault conditions. Adjustable undervoltage and overvoltage detectors dis- connect the load whenever the input supply exceeds the desired operating range. The L TC4252’s supply input is shunt regulated, allowing safe operation with very high supply voltages. A multifunction timer delays initial start- up and controls the circuit breaker’s response time. The circuit breaker’s response time is accelerated by sensing excessive MOSFET drain voltage, keeping the MOSFET within its safe operating area (SOA). An adjustable soft- start circuit controls MOSFET inrush current at start-up. The LTC4252-1/LTC4252A-1 latch off after a circuit breaker fault times out. The L TC4252-2 provides automatic retry after a fault. The L TC4252A-1/L TC4252A-2 feature tight ±1% undervoltage/overvoltage threshold accuracy. The L TC4252 is available in either an 8-pin or 10-pin MSOP. –48V/2.5A Hot Swap Controller Start-Up Behavior
APPLICATIONS
n Allows Safe Board Insertion and Removal from a Live – 48V Backplane n Floating Topology Permits Very High Voltage Operation n Programmable Analog Current Limit With Circuit Breaker Timer n Fast Response Time Limits Peak Fault Current n Programmable Soft-Start Current Limit n Programmable Timer with Drain Voltage Accelerated Response n ±1% Undervoltage/Overvoltage Threshold Accuracy (L TC4252A) ■ Adjustable Undervoltage/Overvoltage Protection ■ L TC4252-1/L TC4252A-1: Latch Off After Fault ■ L TC4252-2: Automatic Retry After Fault ■ Available in 8-Pin and 10-Pin MSOP Packages n Hot Board Insertion n Electronic Circuit Breaker n – 48V Distributed Power Systems n Negative Power Supply Control n Central Office Switching n High Availability Servers n ATCA L, L T , L TC, L TM, Linear Technology and the Linear logo are registered trademarks and Hot Swap is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners.
425212 TA01
–48RTN OV UV VEE VIN SENSESS TIMER GATE PWRGD DRAIN L TC4252-1 402k 32.4k 1% CT 0.33μF DIN DDZ13B** CSS 68nF CC 18nF –48V RS 0.02Ω IRF530S VOUT RC 10Ω 5.1k RIN 3× 1.8k IN SERIES 1/4W EACH 10nF CIN 1μF CL 100μF –48RTN (SHORT PIN) RD 1M LOAD EN * M0C207 **DIODES, INC †RECOMMENDED FOR HARSH ENVIRONMENTS
425212 TA01a
2.5A/DIV PWRGD 10V/DIV 1ms/DIV VOUT 20V/DIV NOT RECOMMENDED FOR NEW DESIGNS Please See LTC4252B/LTC4252C for Drop-In Replacement
All Voltages Referred to VEE (Note 1) TOP VIEW MS8 PACKAGE 8-LEAD PLASTIC MSOP VIN SS SENSE VEE TIMER UV/OV DRAIN GATE TJMAX = 125°C, θJA = 160°C/W V IN PWRGD SS SENSE VEE TIMER UV OV DRAIN GATE TOP VIEW MS PACKAGE 10-LEAD PLASTIC MSOP TJMAX = 125°C, θJA = 160°C/W PIN CONFIGURATION ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE L TC4252-1CMS8 L TC4252-1CMS8#TRPBF L TWM 8-Lead Plastic MSOP 0°C to 70°C L TC4252-2CMS8 L TC4252-2CMS8#TRPBF L TWP 8-Lead Plastic MSOP 0°C to 70°C L TC4252-1IMS8 L TC4252-1IMS8#TRPBF L TRQ 8-Lead Plastic MSOP –40°C to 85°C L TC4252-2IMS8 L TC4252-2IMS8#TRPBF L TRR 8-Lead Plastic MSOP –40°C to 85°C LEAD BASED FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE L TC4252-1CMS L TC4252-1CMS#TR L TWN 10-Lead Plastic MSOP 0°C to 70°C L TC4252-2CMS L TC4252-2CMS#TR L TWQ 10-Lead Plastic MSOP 0°C to 70°C L TC4252A-1CMS L TC4252A-1CMS#TR L TAFX 10-Lead Plastic MSOP 0°C to 70°C L TC4252A-2CMS L TC4252A-2CMS#TR L TAGE 10-Lead Plastic MSOP 0°C to 70°C L TC4252-1IMS L TC4252-1IMS#TR L TRS 10-Lead Plastic MSOP –40°C to 85°C L TC4252-2IMS L TC4252-2IMS#TR L TRT 10-Lead Plastic MSOP –40°C to 85°C L TC4252A-1IMS L TC4252A-1IMS#TR L TAFY 10-Lead Plastic MSOP –40°C to 85°C L TC4252A-2IMS L TC4252A-2IMS#TR L TAGF 10-Lead Plastic MSOP –40°C to 85°C Consult L TC Marketing for parts specified with wider operating temperature ranges. For more information on lead free part marking, go to: http://www.linear .com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear .com/tapeandreel/ Operating Temperature Range LTC4252-1C/LTC4252-2C LTC4252-1I/LTC4252-2I
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 2) SYMBOL PARAMETER CONDITIONS L TC4252-1/-2 L TC4252A-1/-2 UNITSMIN TYP MAX MIN TYP MAX VZ VIN – VEE Zener Voltage I IN = 2mA l 11.5 13 14.5 11.5 13 14.5 V rZ VIN – VEE Zener Dynamic Impedance I IN = 2mA to 30mA 5 5 Ω IIN VIN Supply Current UV = OV = 4V , V IN = (VZ – 0.3V) ● 0.8 2 0.9 2 mA VLKO VIN Undervoltage Lockout Coming Out of UVLO (Rising V IN) ● 9.2 11.5 9 10 V VLKH VIN Undervoltage Lockout Hysteresis 1 0.5 V VCB Circuit Breaker Current Limit Voltage V CB = (VSENSE – VEE) ● 40 50 60 45 50 55 mV VACL Analog Current Limit Voltage V ACL = (VSENSE – VEE), SS = Open or 2.2V
- 80 100 120 mV VACL/ VCB Analog Current Limit Voltage/ Circuit Breaker Voltage V ACL = (VSENSE – VEE), SS = Open or 1.4V
- 1.05 1.20 1.38 V/V VFCL Fast Current Limit Voltage V FCL = (VSENSE – VEE) ● 150 200 300 150 200 300 mV VSS SS Voltage After End of SS Timing Cycle 2.2 1.4 V RSS SS Output Impedance 100 50 kΩ ISS SS Pin Current UV = OV = 4V , V SENSE = VEE, VSS = 0V (Sourcing) 22 28 μA UV = OV = 0V , VSENSE = VEE, VSS = 2V (Sinking) 28 28 mA VOS Analog Current Limit Offset Voltage 10 10 mV VACL+VOS/ VSS Ratio (VACL + VOS) to SS Voltage 0.05 0.05 V/V IGATE GATE Pin Output Current UV = OV = 4V , V SENSE = VEE, VGATE = 0V (Sourcing)
- 40 58 80 40 58 80 μA UV = OV = 4V , VSENSE – VEE = 0.15V , VGATE = 3V (Sinking) 17 17 mA UV = OV = 4V , VSENSE – VEE = 0.3V , VGATE = 1V (Sinking) 190 190 mA VGATE External MOSFET Gate Drive V GATE – VEE, IIN = 2mA ● 10 12 V Z 10 12 V Z V VGATEH Gate High Threshold V GATEH = VIN – VGATE, IIN = 2mA, for PWRGD Status (MS Only) 2.8 2.8 V VGATEL Gate Low Threshold (Before Gate Ramp-Up) 0.5 0.5 V VUVHI UV Pin Threshold HIGH ● 3.075 3.225 3.375 V VUVLO UV Pin Threshold LOW ● 2.775 2.925 3.075 V VUV UV Pin Threshold Low-to-High T ransition ● 3.05 3.08 3.11 V VUVHST UV Pin Hysteresis ( ● for L TC4252A Only) ● 300 292 324 356 mV VOVHI OV Pin Threshold HIGH ● 5.85 6.15 6.45 V VOVLO OV Pin Threshold LOW ● 5.25 5.55 5.85 V VOV OV Pin Threshold Low-to-High T ransition ● 5.04 5.09 5.14 V VOVHST OV Pin Hysteresis ( ● for L TC4252A Only) ● 600 82 102 122 mV ISENSE SENSE Pin Input Current UV = OV = 4V , V SENSE = 50mV ● –15 –30 –15 –30 μA IINP UV , OV Pin Input Current UV = OV = 4V ● ± 0.1 ±1 ± 0.1 ±1 μA VTMRH TIMER Pin Voltage High Threshold 4 4 V VTMRL TIMER Pin Voltage Low Threshold 1 1 V
SYMBOL PARAMETER CONDITIONS L TC4252-1/-2 L TC4252A-1/-2 UNITSMIN TYP MAX MIN TYP MAX ITMR TIMER Pin Current Timer On (Initial Cycle/Latchoff/ Shutdown Cooling, Sourcing), V TMR = 2V 5.8 5.8 μA Timer Off (Initial Cycle, Sinking), VTMR = 2V 28 28 mA Timer On (Circuit Breaker , Sourcing, IDRN = 0μA), VTMR = 2V 230 230 μA Timer On (Circuit Breaker , Sourcing, IDRN = 50μA), VTMR = 2V 630 630 μA Timer Off (Circuit Breaker/ Shutdown Cooling, Sinking), V TMR = 2V 5.8 5.8 μA ΔITMRACC/ ΔIDRN [(ITMR at IDRN = 50μA) – (ITMR at IDRN = 0μA)]/ΔIDRN Timer On (Circuit Breaker with I DRN = 50μA) 8 8 μA/μA VDRNL DRAIN Pin Voltage Low Threshold For PWRGD Status (MS Only) 2.385 2.385 V IDRNL DRAIN Leakage Current V DRAIN = 5V (4V for L TC4252A) ± 0.1 ±1 ± 0.1 ±1 μA VDRNCL DRAIN Pin Clamp Voltage I DRN = 50μA 7 6 V VPGL PWRGD Output Low Voltage I PG = 1.6mA (MS Only) IPG = 5mA (MS Only) 0.2 0.4 1.1 0.2 0.4 1.1 V V IPGH PWRGD Pull-Up Current V PWRGD = 0V (Sourcing) (MS Only) ● 40 58 80 40 58 80 μA tSS SS Default Ramp Period SS Pin Floating, V SS Ramps from 0.2V to 2V 180 μs SS Pin Floating, VSS Ramps from 0.1V to 0.9V 230 μs tPLLUG UV Low to Gate Low 0.4 0.4 μs tPHLOG OV High to Gate Low 0.4 0.4 μs ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 2) Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to V EE unless otherwise specified.
TYPICAL PERFORMANCE CHARACTERISTICS IIN vs VIN Undervoltage Lockout VLKO vs Temperature Undervoltage Lockout Hysteresis VLKH vs Temperature Circuit Breaker Current Limit Voltage VCB vs Temperature Analog Current Limit Voltage VACL vs Temperature Fast Current Limit Voltage VFCL vs Temperature VZ vs Temperature r Z vs Temperature IIN vs Temperature TEMPERATURE (°C) –55 IIN (μA) 2000 1800 1600 1400 1200 1000 800 600 400 200 –15 25 45 125
425212 G01
–35 5 65 85 105 VIN = (VZ – 0.3V) TEMPERATURE (°C) –55 VZ (V) 14.5 14.0 13.5 13.0 12.5 12.0 –15 25 45 125
425212 G04
–35 5 65 85 105 IIN = 2mA TEMPERATURE (°C) –55 rZ (Ω) –15 25 45 125
425212 G03
–35 5 65 85 105 IIN = 2mA VIN (V) 02468 1 0 1 2 1 4 1 6 1 8 2 0 2 2 IIN (mA) 1000 100 0.1
425212 G02
TA = –40°C TA = 125°C TA = 85°C TA = 25°C TEMPERATURE (°C) –55 VLKO (V) 12.0 11.5 11.0 10.5 10.0 9.5 9.0 8.5 8.0 –15 25 45 125
425212 G05
–35 5 65 85 105 TEMPERATURE (°C) –55 0.5 VLKH (V) 0.7 1.1 1.3 1.5 –15 25 45 125
425212 G06
0.9 –35 5 65 95 105 TEMPERATURE (°C) –55 VCB (mV) –15 25 45 125
425212 G07
–35 5 65 85 105 TEMPERATURE (°C) –55 VACL (mV) 120 115 110 105 100 –15 25 45 125
425212 G08
–35 5 65 85 105 TEMPERATURE (°C) –55 VFCL (mV) 300 275 250 225 200 175 150 –15 25 45 125
425212 G09
–35 5 65 85 105
TYPICAL PERFORMANCE CHARACTERISTICS VOS vs Temperature (V ACL + VOS)/VSS vs Temperature I GATE (Sourcing) vs Temperature IGATE (ACL, Sinking) vs Temperature IGATE (FCL, Sinking) vs Temperature V GATE vs Temperature VSS vs Temperature R SS vs Temperature I SS (Sinking) vs Temperature TEMPERATURE (°C) –55 –35 –15 5 25 45 65 85 105 125 VSS (V)
425212 G26
2.40 2.35 2.30 2.25 2.20 2.15 2.10 2.05 2.00 TEMPERATURE (°C) –55 –35 –15 5 25 45 65 85 105 125 RSS (kΩ)
425212 G28
TEMPERATURE (°C) –55 –35 –15 ISS (mA) 65 85 105
425212 G39
UV = OV = VSENSE = VEE IIN = 2mA VSS = 2V TEMPERATURE (°C) –55 –35 –15 5 25 45 65 85 105 125 VOS (mV)
425212 G29
11.0 10.8 10.6 10.4 10.2 10.0 9.8 9.6 9.4 9.2 9.0 TEMPERATURE (°C) –55 –35 –15 5 25 45 65 85 105 125 (VACL + VOS)/V SS (V/V)
425212 G30
0.060 0.058 0.056 0.054 0.052 0.050 0.048 0.046 0.044 0.042 0.040 TEMPERATURE (C) –55 IGATE (A) –15 25 45 125
425212 G10
–35 5 65 85 105 UV/0V = 4V TIMER = 0V V SENSE = VEE VGATE = 0V TEMPERATURE (°C) –55 IGATE (mA) –15 25 45 125
425212 G11
–35 5 65 85 105 UV/0V = 4V TIMER = 0V V SENSE – VEE = 0.15V VGATE = 3V TEMPERATURE (°C) –55 IGATE (mA) 400 350 300 250 200 150 100 –15 25 45 125
425212 G12
–35 5 65 85 105 UV/0V = 4V TIMER = 0V V SENSE – VEE = 0.3V VGATE = 1V TEMPERATURE (°C) –55 VGATE (V) 14.5 14.0 13.5 13.0 12.5 12.0 11.5 11.0 10.5 10.0 –15 25 45 125
425212 G13
–35 5 65 85 105 UV/0V = 4V TIMER = 0V V SENSE = VEE
TYPICAL PERFORMANCE CHARACTERISTICS OV Threshold vs Temperature I SENSE vs Temperature I SENSE vs (VSENSE – VEE) TIMER Threshold vs Temperature ITMR (Initial Cycle, Sourcing) vs Temperature ITMR (Initial Cycle, Sinking) vs Temperature VGATEH vs Temperature V GATEL vs Temperature UV Threshold vs Temperature TEMPERATURE (°C) –55 –35 –15 5 25 45 65 85 105 125 VGATEH (V)
425212 G31
3.6 3.4 3.2 3.0 2.8 2.6 2.4 2.2 2.0 VGATEH = VIN – VGATE, IIN = 2mA (MS ONLY) TEMPERATURE (°C) –55 VGATEL (V) 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 –15 25 45 125
425212 G14
–35 5 65 85 105 UV/0V = 4V TIMER = 0V GATE THRESHOLD BEFORE RAMP-UP TEMPERATURE (°C) –55 UV THRESHOLD (V) 3.375 3.275 3.175 3.075 2.975 2.875 2.775 –15 25 45 125
425212 G15
–35 5 65 85 105 VUVH VUV VUVL TEMPERATURE (°C) –55 OV THRESHOLD (V) 6.45 6.25 6.05 5.85 5.65 5.45 5.25 5.05 4.85 –15 25 45 125
425212 G16
–35 5 65 85 105 VOVH VOVL VOV TEMPERATURE (°C) –55 ISENSE (A) –10 –12 –14 –16 –18 –20 –22 –24 –26 –28 –30 –15 25 45 125
425212 G17
–35 5 65 85 105 UV/0V = 4V TIMER = 0V GATE = HIGH V SENSE – VEE = 50mV (VSENSE – VEE) (V) –ISENSE (mA) 0.01 0.1 1.0 100 1000
425212 G18
UV/0V = 4V TIMER = 0V GATE = HIGH T A = 25°C TEMPERATURE (°C) –55 TIMER THRESHOLD (V) 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 –15 25 45 125
425212 G19
–35 5 65 85 105 VTMRH VTMRL TEMPERATURE (°C) –55 ITMR (μA) –15 25 45 125
425212 G20
–35 5 65 85 105 TIMER = 2V TEMPERATURE (°C) –55 ITMR (mA) –15 25 45 125
425212 G21
–35 5 65 85 105 TIMER = 2V
TYPICAL PERFORMANCE CHARACTERISTICS ITMR vs IDRN ∆ITMRACC/∆IDRN vs Temperature I DRN vs VDRAIN VDRNL vs Temperature V DRNCL vs Temperature V PGL vs Temperature ITMR (Circuit Breaker , Sourcing) vs Temperature ITMR (Circuit Breaker , IDRN = 50μA, Sourcing) vs Temperature ITMR (Cooling Cycle, Sinking) vs Temperature TEMPERATURE (°C) –55 ITMR (μA) 280 260 240 220 200 180 –15 25 45 125
425212 G22
–35 5 65 85 105 TIMER = 2V IDRN = 0μA TEMPERATURE (°C) –55 –35 –15 5 25 45 65 85 105 125
550 ITMR (μA)
425212 G32
TIMER = 2V IDRN = 50μA TEMPERATURE (°C) –55 ITMR (A) –15 25 45 125
425212 G23
–35 5 65 85 105 TIMER = 2V IDRN (mA) 0.001 0.01 0.1 ITMR (mA)1 0.1 1 10
425212 G33
TEMPERATURE (°C) –55 –35 –15 5 25 45 65 85 105 125 ΔITMRACC/IDRN (μA/μA)
425212 G34
9.0 8.8 8.6 8.4 8.2 8.0 7.8 7.6 7.4 7.2 7.0 TIMER ON (CIRCUIT BREAKING, I DRN = 50μA) VDRAIN (V) 0 2 4 6 8 10 12 14 16 IDRN (mA) 100 0.1 0.01 0.001 0.0001 0.00001
425212 G25
IIN = 2mA TA = –40°C TA = 25°C TA = 125°C TA = 85°C TEMPERATURE (°C) –55 –35 –15 5 25 45 65 85 105 125 VDRNL (V)
425212 G35
2.60 2.55 2.50 2.45 2.40 2.35 2.30 2.25 2.20 FOR PWRGD STATUS (MS ONLY) TEMPERATURE (°C) –55 –35 –15 5 25 45 65 85 105 125 VDRNCL (V)
425212 G36
8.0 7.8 7.6 7.4 7.2 7.0 6.8 6.6 6.4 6.2 6.0 IDRN = 50μA TEMPERATURE (°C) –55 –35 –15 5 25 45 65 85 105 125 VPGL (V)
425212 G37
3.0 2.5 2.0 1.5 1.0 0.5 (MS ONLY) IPG = 10mA IPG = 5mA IPG = 1.6mA
VIN (Pin 1/Pin 1): Positive Supply Input. Connect this pin to the positive side of the supply through a dropping resistor . A shunt regulator clamps V IN at 13V . An internal undervoltage lockout (UVLO) circuit holds GATE low until the V IN pin is greater than VLKO, overriding UV and OV . If UV is high, OV is low and VIN comes out of UVLO, TIMER starts an initial timing cycle before initiating a GATE ramp- up. If V IN drops below approximately 8.2V , GATE pulls low immediately. PWRGD (Pin 2/Not Available): Power Good Status Output (MS only). At start-up, PWRGD latches low if DRAIN is below 2.385V and GATE is within 2.8V of V IN. PWRGD status is reset by UV , VIN (UVLO) or a circuit breaker fault timeout. This pin is internally pulled high by a 58μA cur- rent source. SS (Pin 3/Pin 2): Soft-Start Pin. This pin is used to ramp inrush current during start up, thereby effecting control over di/dt. A 20x attenuated version of the SS pin voltage is presented to the current limit amplifier . This attenuated voltage limits the MOSFET’s drain current through the sense resistor during the soft-start current limiting. At the begin- ning of a start-up cycle, the SS capacitor (C SS) is ramped by a 22μA (28μA for the L TC4252A) current source. The GATE pin is held low until SS exceeds 20 • V OS = 0.2V . SS is internally shunted by a 100k resistor (R SS) which limits the SS pin voltage to 2.2V (50k resistor and 1.4V for the L TC4252A). This corresponds to an analog current limit SENSE voltage of 100mV (60mV for the L TC4252A). If the SS capacitor is omitted, the SS pin ramps up in about 180μs. The SS pin is pulled low under any of the following conditions: in UVLO, in an undervoltage condition, in an overvoltage condition, during the initial timing cycle or when the circuit breaker fault times out. SENSE (Pin 4/Pin 3): Circuit Breaker/Current Limit Sense Pin. Load current is monitored by a sense resistor R S con- nected between SENSE and VEE, and controlled in three steps. If SENSE exceeds VCB (50mV), the circuit breaker comparator activates a (230μA + 8 • IDRN) TIMER pull-up current. If SENSE exceeds VACL, the analog current limit amplifier pulls GATE down to regulate the MOSFET current at V ACL/RS. In the event of a catastrophic short-circuit, SENSE may overshoot. If SENSE reaches VFCL (200mV), the fast current limit comparator pulls GATE low with a strong pull-down. To disable the circuit breaker and cur- rent limit functions, connect SENSE to VEE. (MS/MS8) TYPICAL PERFORMANCE CHARACTERISTICS IPGH vs Temperature t SS vs Temperature tPLLUG and tPHLOG vs Temperature TEMPERATURE (°C) –55 –35 –15 5 25 45 65 85 105 125 IPGH (μA)
425212 G38
VPWRGD = 0V (MS ONLY) TEMPERATURE (°C) –55 –35 –15 5 25 45 65 85 105 125 tSS (μs)
425212 G27
SS PIN FLOATING, VSS RAMPS FROM 0.2V TO 2V TEMPERATURE (°C) –55 DELAY (μs) 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 –15 25 45 125
425212 G24
–35 5 65 85 105 tPLLUG tPHLOG
PIN FUNCTIONS (MS/MS8) VEE (Pin 5/Pin 4): Negative Supply Voltage Input. Connect this pin to the negative side of the power supply. GATE (Pin 6/Pin 5): N-Channel MOSFET Gate Drive Output. This pin is pulled high by a 58μA current source. GATE is pulled low by invalid conditions at V IN (UVLO), UV , OV , or a circuit breaker fault timeout. GATE is actively servoed to control the fault current as measured at SENSE. A compen- sation capacitor at GATE stabilizes this loop. A comparator monitors GATE to ensure that it is low before allowing an initial timing cycle, GATE ramp-up after an overvoltage event or restart after a current limit fault. During GATE start-up, a second comparator detects if GATE is within 2.8V of V IN before PWRGD is set (MS package only). DRAIN (Pin 7/Pin 6): Drain Sense Input. Connecting an external resistor , RD, between this pin and the MOSFET’s drain (VOUT) allows voltage sensing below 6.15V (5V for L TC4252A) and current feedback to TIMER. A comparator detects if DRAIN is below 2.385V and together with the GATE high comparator sets the PWRGD flag. If V OUT is above VDRNCL, DRAIN clamps at approximately V DRNCL. The current through RD is internally multiplied by 8 and added to TIMER’s 230μA pullup current during a circuit breaker fault cycle. This reduces the fault time and MOSFET heating. OV (Pin 8/Pin7): Overvoltage Input. The active high thresh- old at the OV pin is set at 6.15V with 0.6V hysteresis. If OV > 6.15V , GATE pulls low. When OV returns below 5.55V , GATE start-up begins without an initial timing cycle. The L TC4252A OV pin is set at 5.09V with 102mV hysteresis. If OV > 5.09V , GATE pulls low. When OV returns below 4.988V , GATE start-up begins without an initial timing cycle. If an overvoltage condition occurs in the middle of an initial timing cycle, the initial timing cycle is restarted after the overvoltage condition goes away. An overvoltage condition does not reset the PWRGD flag. The internal UVLO at V IN always overrides OV . A 1nF to 10nF capacitor at OV prevents transients and switching noise from affecting the OV thresholds and prevents glitches at the GATE pin. UV (Pin 9/Pin 7): Undervoltage Input. The active low thresh- old at the UV pin is set at 2.925V with 0.3V hysteresis. If UV < 2.925V , PWRGD pulls high, both GATE and TIMER pull low. If UV rises above 3.225V , this initiates an initial timing cycle followed by GATE start-up. The L TC4252A UV pin is set at 3.08V with 324mV hysteresis. If UV < 2.756V , PWRGD pulls high, both GATE and TIMER pull low. If UV rises above 3.08V , this initiates an initial timing cycle followed by GATE start-up. The internal UVLO at V IN always overrides UV . A low at UV resets an internal fault latch. A 1nF to 10nF capacitor at UV prevents transients and switching noise from affecting the UV thresholds and prevents glitches at the GATE pin. TIMER (Pin 10/Pin 8): Timer Input. TIMER is used to generate an initial timing delay at start-up and to delay shutdown in the event of an output overload (circuit breaker fault). TIMER starts an initial timing cycle when the following conditions are met: UV is high, OV is low, V IN clears UVLO, TIMER pin is low, GATE is lower than VGATEL, SS < 0.2V , and VSENSE – VEE < VCB. A pull-up current of 5.8μA then charges C T, generating a time delay. If C T charges to VTMRH (4V), the timing cycle terminates, TIMER quickly pulls low and GATE is activated. If SENSE exceeds 50mV while GATE is high, a circuit breaker cycle begins with a 230μA pull-up current charging C T. If DRAIN is approximately 7V (6V for L TC4252A) dur- ing this cycle, the timer pull-up has an additional current of 8 • I DRN. If SENSE drops below 50mV before TIMER reaches 4V , a 5.8μA pull-down current slowly discharges the C T. In the event that CT eventually integrates up to the VTMRH threshold, the circuit breaker trips, GATE quickly pulls low and PWRGD pulls high. The L TC4252-1 TIMER pin latches high with a 5.8μA pull-up source. This latched fault is cleared by either pulling TIMER low with an external device or by pulling UV below V UVLO. The L TC4252-2 starts a shutdown cooling cycle following an overcurrent fault. This cycle consists of 4 discharging ramps and 3 charging ramps. The charging and discharging currents are 5.8μA and TIMER ramps between its 1V and 4V thresholds. At the completion of a shutdown cooling cycle, the L TC4252-2 attempts a start-up cycle.
– (+) + (–) VIN VIN VEE VEE RSS VEE VEE VEE 0.5V VEE VEE VEE 5.8μA 5.8μA VIN VEE VIN 6.15V (5V) 58μA 230μA VIN 22μA (28μA) 95k (47.5k) TIMER 6.15V (5.09V) 2.925V (3.08V) 2.385V VEE VEE VOS = 10mV VIN 2.8V UV * GATE SENSE VIN VEE 58μA PWRGD ** DRAIN OV * SS VIN CB 50mV FCL 200mV ACL (2.5k) 1× 1× 8× 1× LOGIC *OV AND UV ARE TIED TOGETHER ON THE MS8 PACKAGE. OV AND UV ARE SEPARATE PINS ON THE MS PACKAGE ** ONLY AVAILABLE IN THE MS PACKAGE FOR COMPONENTS, CURRENT AND VOLTAGE WITH TWO VALUES, VALUES IN PARENTHESES REFER TO THE LTC4252A. VALUES WITHOUT PARENTHESES REFER TO THE LTC4252
are provided by the MOSFET . A detailed schematic for the L TC4252A is shown in Figure 2.
- The voltage at UV > VUVHI.
- The voltage at OV < VOVLO.
- The (SENSE – VEE) voltage is < 50mV (VCB).
- The voltage at SS is < 0.2V (20 • VOS).
- The voltage on the TIMER capacitor (CT) is < 1V (VTMRL).
- The voltage at GATE is < 0.5V (VGATEL).
the Applications Information, Timing Waveforms section. within 2.8V of VIN and DRAIN is lower than VDRNL. Figure 1. Basic L TC4252 Hot Swap Topology Figure 2. –48V , 2.5A Hot Swap Controller
425212 F02
T wo modes of operation are possible during the time the MOSFET is first turning on, depending on the values of external components, MOSFET characteristics and nominal design current. One possibility is that the MOSFET will turn on gradually so that the inrush into the load capacitance remains a low value. The output will simply ramp to –48V and the L TC4252 will fully enhance the MOSFET . A second possibility is that the load current exceeds the soft-start current limit threshold of [V SS(t)/20 – VOS]/RS. In this case the L TC4252 will ramp the output by sourcing soft-start limited current into the load capacitance. If the soft-start voltage is below 1.2V , the circuit breaker TIMER is held low. Above 1.2V , TIMER ramps up. It is important to set the timer delay so that, regardless of which start-up mode is used, the TIMER ramp is less than one circuit breaker delay time. If this condition is not met, the L TC4252-1 may shut down after one circuit breaker delay time whereas the L TC4252-2 may continue to autoretry. Board Removal If the board is withdrawn from the card cage, the UV and OV divider is the first to lose connection. This shuts off the MOSFET and commutates the flow of current in the connector . When the power pins subsequently separate, there is no arcing. Current Control Three levels of protection handle short-circuit and over- load conditions. Load current is monitored by SENSE and resistor R S. There are three distinct thresholds at SENSE: 50mV for a timed circuit breaker function; 100mV for an analog current limit loop (60mV for the L TC4252A); and 200mV for a fast, feedforward comparator which limits peak current in the event of a catastrophic short-circuit. If, owing to an output overload, the voltage drop across R S exceeds 50mV , TIMER sources 230μA into CT. CT eventually charges to a 4V threshold and the L TC4252 shuts off. If the overload goes away before C T reaches 4V and SENSE measures less than 50mV , CT slowly discharges (5.8μA). In this way the L TC4252’s circuit breaker function responds to low duty cycle overloads and accounts for fast heating and slow cooling characteristics of the MOSFET . Higher overloads are handled by an analog current limit loop. If the drop across R S reaches VACL, the current limiting loop servos the MOSFET gate and maintains a constant output current of V ACL/RS. In current limit mode, V OUT typically rises and this increases MOSFET heating. If VOUT > VDRNCL, connecting an external resistor , RD, between VOUT and DRAIN allows the fault timing cycle to be shortened by accelerating the charging of the TIMER capacitor . The TIMER pull-up current is increased by 8 • I DRN. Note that because SENSE > 50mV , TIMER charges CT during this time and the L TC4252 will eventually shut down. Low impedance failures on the load side of the L TC4252 coupled with 48V or more driving potential can produce current slew rates well in excess of 50A/μs. Under these conditions, overshoot is inevitable. A fast SENSE com- parator with a threshold of 200mV detects overshoot and pulls GATE low much harder and hence much faster than the weaker current limit loop. The V ACL/RS current limit loop then takes over and servos the current as previously described. As before, TIMER runs and shuts down the L TC4252 when C T reaches 4V . If CT reaches 4V , the L TC4252-1 latches off with a 5.8μA pull-up current source whereas the L TC4252-2 starts a shutdown cooling cycle. The L TC4252-1 circuit breaker latch is reset by either pulling UV momentarily low or dropping the input voltage V IN below the internal UVLO threshold or pulling TIMER momentarily low with a switch. The L TC4252-2 retries after its shutdown cooling cycle. Although short-circuits are the most obvious fault type, several operating conditions may invoke overcurrent protection. Noise spikes from the backplane or load, input steps caused by the connection of a second, higher voltage supply, transient currents caused by faults on adjacent circuit boards sharing the same power bus or the inser- tion of non-hot-swappable products could cause higher than anticipated input current and temporary detection of an overcurrent condition. The action of TIMER and C T rejects these events allowing the L TC4252 to “ride out” temporary overloads and disturbances that could trip a simple current comparator and, in some cases, blow a fuse.
supply transients and contributes a short delay at start-up. return, or secondary-side power and ground planes. 19 cascodes the PWRGD output. IN, CIN, DIN and VEE as short as possible. UV/OV pin(s). These are completely separate functions.
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Figure 3. – 48V/2.5A Application with Different Input Operating Range
resistors are recommended to preserve threshold accuracy. nations are possible with different resistor arrangements. resistors are recommended to preserve threshold accuracy. ing range such as 35.5V to 76V as shown in Figure 4.
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Figure 4. – 48V/2.5A Application with Wider Input Operating Range
conditions are met. A high-to-low transition in the UV comparator immediately shuts down the L TC4252, pulls the MOSFET gate low and resets the latched PWRGD high. Overvoltage conditions detected by the OV compara- tor will also pull GATE low, thereby shutting down the load. However , it will not reset the circuit breaker TIMER, PWRGD flag or shutdown cooling timer . Returning the supply voltage to an acceptable range restarts the GATE pin if all the interlock conditions except TIMER are met. Only during the initial timing cycle does an OV condition reset the TIMER. DRAIN Connecting an external resistor , R D, to the dual function DRAIN pin allows V OUT sensing* without it being dam- aged by large voltage transients. Below 5V , negligible pin leakage allows a DRAIN low comparator to detect V OUT less than 2.385V (V DRNL). This condition, together with the GATE low comparator , sets the PWRGD flag. If V OUT > V DRNCL, the DRAIN pin is clamped at about VDRNCL and the current flowing in RD is given by: IDRN ≈ VOUT -VDRNCL RD (1) This current is scaled up 8 times during a circuit breaker fault and is added to the nominal 230μA TIMER current. This accelerates the fault TIMER pull-up when the MOS- FET’s drain-source voltage exceeds V DRNCL and effectively shortens the MOSFET heating duration. TIMER The operation of the TIMER pin is somewhat complex as it handles several key functions. A capacitor CT is used at TIMER to provide timing for the L TC4252. Four different charging and discharging modes are available at TIMER: 1) A 5.8μA slow charge; initial timing and shutdown cool- ing delay. 2) A (230μA + 8 • I DRN) fast charge; circuit breaker delay. 3) A 5.8μA slow discharge; circuit breaker “cool off” and shutdown cooling. 4) Low impedance switch; resets the TIMER capacitor after an initial timing delay, in UVLO, in UV and in OV during initial timing. For initial start-up, the 5.8μA pull-up is used. The low impedance switch is turned off and the 5.8μA current source is enabled when the interlock conditions are met. C T charges to 4V in a time period given by: t= 4V •CT 5.8μA (2) When CT reaches 4V (VTMRH), the low impedance switch turns on and discharges CT. A GATE start-up cycle begins and both SS and GATE are released. CIRCUIT BREAKER TIMER OPERATION If the SENSE pin detects more than a 50mV drop across RS, the TIMER pin charges CT with (230μA + 8 • IDRN). If CT charges to 4V , the GATE pin pulls low and the L TC4252-1 latches off while the L TC4252-2 starts a shutdown cooling cycle. The L TC4252-1 remains latched off until the UV pin is momentarily pulsed low or TIMER is momentarily discharged low by an external switch or V IN dips below UVLO and is then restored. The circuit breaker timeout period is given by: t= 4V •CT 230μA+8 •IDRN (3) If VOUT < 5V , an internal PMOS device isolates any DRAIN pin leakage current, making I DRN = 0μA in Equation (3). If VOUT > V DRNCLduring the circuit breaker fault period, the charging of CT accelerates by 8 • IDRN of Equation (1). Intermittent overloads may exceed the 50mV threshold at SENSE, but, if their duration is sufficiently short, TIMER will not reach 4V and the L TC4252 will not shut the external MOSFET off. To handle this situation, the TIMER discharges C T slowly with a 5.8μA pull-down whenever the SENSE voltage is less than 50mV . Therefore, any intermittent overload with V OUT > 5V and an aggregate duty cycle of *VOUT as viewed by the MOSFET ; i.e., VDS.
a fair gauge of MOSFET heating. MOSFET’s SOA rating if powering up into an active load. This allows the inrush current to be limited to VACL(t)/RS. when the circuit breaker fault times out. drive to no more than 14.5V .
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Figure 5. Circuit-Breaker Response Time
for the analog current limit loop. tor , sets PWRGD status during GATE startup. overcorrects the current limit loop and GATE undershoots. pacitor) helps the ACL amplifier to recover . ber resistor is typically between 3Ω to 100Ω.
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Figure 6. Output Short-Circuit Behavior of L TC4252
A low impedance short on one card may influence the behavior of others sharing the same backplane. The initial glitch and backplane sag as seen in Figure 6 T race 1, can rob charge from output capacitors on adjacent cards. When the faulty card shuts down, current flows in to refresh the capacitors. If L TC4252s are used by the other cards, they respond by limiting the inrush current to a value of 100mV/R S. If CT is sized correctly, the capacitors will recharge long before CT times out. POWER GOOD, PWRGD PWRGD latches low if GATE charges up to within 2.8V of VIN and DRAIN pulls below VDRNL during start-up. PWRGD is reset in UVLO, in a UV condition or if C T charges up to 4V . An overvoltage condition has no effect on PWRGD status. A 58μA current pulls this pin high during reset. Due to voltage transients between the power module and PWRGD, optoisolation is recommended. This pin provides sufficent drive for an optocoupler . Figure 19 shows an alternative NPN configuration with a limiting base resistor for the PWRGD interface. The module enable input should have protection from the negative input current. MOSFET SELECTION The external MOSFET switch must have adequate safe operating area (SOA) to handle short-circuit conditions until TIMER times out. These considerations take prece- dence over DC current ratings. A MOSFET with adequate SOA for a given application can always handle the required current, but the opposite may not be true. Consult the manufacturer’s MOSFET data sheet for safe operating area and effective transient thermal impedance curves. MOSFET selection is a 3-step process by assuming the absense of a soft-start capacitor . First, R S is calculated and then the time required to charge the load capacitance is determined. This timing, along with the maximum short-circuit current and maximum input voltage defines an operating point that is checked against the MOSFET’s SOA curve. To begin a design, first specify the required load current and Ioad capacitance, I L and CL. The circuit breaker cur- rent trip point (V CB/RS) should be set to accommodate the maximum load current. Note that maximum input current to a DC/DC converter is expected at V SUPPL Y(MIN). RS is given by: RS = VCB(MIN) IL(MAX) (8) where VCB(MIN) = 40mV (45mV for L TC4252A) represents the guaranteed minimum circuit breaker threshold. During the initial charging process, the L TC4252 may oper- ate the MOSFET in current limit, forcing (V ACL) between 80mV to 120mV (VACL is 54mV to 66mV for L TC4252A) across RS. The minimum inrush current is given by: IINRUSH(MIN) = 80mV RS (9) Maximum short-circuit current limit is calculated using the maximum VACL. This gives ISHORTCIRCUIT(MAX) = 120mV RS (10) The TIMER capacitor C T must be selected based on the slowest expected charging rate; otherwise TIMER might time out before the load capacitor is fully charged. A value for C T is calculated based on the maximum time it takes the load capacitor to charge. That time is given by: tCL(CHARGE) = C•V I = CL •VSUPPLY(MAX) IINRUSH(MIN) (11) The maximum current flowing in the DRAIN pin is given by: IDRN(MAX) = VSUPPLY(MAX) –VDRNCL RD (12)
Approximating a linear charging rate as IDRN drops from IDRN(MAX) to zero, the I DRN component in Equation (3) can be approximated with 0.5 • I DRN(MAX). Rearranging equation, TIMER capacitor CT is given by: CT = tCL(CHARGE) • 230μA+4•I DRN(MAX)() 4V (13) Returning to Equation (3), the TIMER period is calcu- lated and used in conjunction with V SUPPL Y(MAX) and ISHORTCIRCUIT(MAX) to check the SOA curves of a prospec- tive MOSFET . As a numerical design example, consider a 30W load, which requires 1A input current at 36V . If V SUPPL Y(MAX) = 72V and CL = 100μF , RD = 1MΩ, Equation (8) gives RS = 40mΩ; Equation (13) gives CT = 441nF . To account for errors in RS, CT, TIMER current (230μA), TIMER threshold (4V), RD, DRAIN current multiplier and DRAIN voltage clamp (VDRNCL), the calculated value should be multiplied by 1.5, giving the nearest standard value of CT = 680nF . If a short-circuit occurs, a current of up to 120mV/40mΩ = 3A will flow in the MOSFET for 5.6ms as dictated by CT = 680nF in Equation (3). The MOSFET must be selected based on this criterion. The IRF530S can handle 100V and 3A for 10ms and is safe to use in this application. Computing the maximum soft-start capacitor value during soft-start to a load short is complicated by the nonlinear MOSFET’s SOA characteristics and the R SSCSS response. An overly conservative but simple approach begins with the maximum circuit breaker current, given by: ICB(MAX) = VCB(MAX) RS (14) where VCB(MAX) = 60mV (55mV for the L TC4252A). From the SOA curves of a prospective MOSFET , determine the time allowed, tSOA(MAX). CSS is given by: CSS = tSOA(MAX) 0.916 •RSS (15) In the above example, 60mV/40mΩ gives 1.5A. tSOA(MAX) for the IRF530S is 40ms. From Equation (15), C SS = 437nF . Actual board evaluation showed that CSS = 100nF was appropriate. The ratio (R SS • CSS) to tCL(CHARGE) is a good gauge as a large ratio may result in the time-out period expiring. This gauge is determined empirically with board level evaluation. SUMMARY OF DESIGN FLOW To summarize the design flow, consider the application shown in Figure 2 with the L TC4252A. It was designed for 80W . Calculate the maximum load current: 80W/43V = 1.86A; allowing for 83% converter efficiency, I IN(MAX) = 2.2A. Calculate RS: from Equation (8) RS = 20mΩ. Calculate ISHORTCIRCUIT(MAX): from Equation (10) ISHORTCIRCUIT(MAX) = 66mV 20mΩ =3.3A Select a MOSFET that can handle 3.3A at 71V: IRF530S. Calculate C T: from Equation (13) C T = 322nF . Select CT = 680nF , which gives the circuit breaker time-out period t = 5.6ms. Consult MOSFET SOA curves: the IRF530S can handle 3.3A at 100V for 8.2ms, so it is safe to use in this application. Calculate C SS: using Equations (14) and (15) select CSS = 68nF . FREQUENCY COMPENSATION The L TC4252A typical frequency compensation network for the analog current limit loop is a series RC (10Ω) and CC connected to VEE. Figure 7 depicts the relationship between the compensation capacitor C C and the MOSFET’s C ISS. The line in Figure 7 is used to select a starting value for CC based upon the MOSFET’s CISS specification. Optimized values for C C are shown for several popular MOSFETs. Differences in the optimized value of CC versus the starting value are small. Nevertheless, compensation values should be verified by board level short-circuit testing. APPLICATIONS INFORMATION
and prevent MOSFET avalanche. optimal sense resistor power dissipation.
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Figure 7. Recommended Compensation Figure 8. Making PCB Connections to the Sense Resistor
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must be satisfied before a GATE ramp-up cycle begins. SS control level and the analog current limit loop activates. load current begins to decline.
GATE reaches its maximum voltage as determined by VIN. TMRH threshold and the initial timing cycle terminates.
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Figure 9. System Power-Up Timing (All Waveforms Are Referenced to VEE)
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Figure 10. Power-Up Timing with a Short Pin (All Waveforms Are Referenced to VEE)
cycle begins followed by a GATE start-up cycle. lockout, the UV and OV comparators are enabled. In Figure 12, both UV and OV pins are connected together . between time points 4 through 7 may occur .
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Figure 11. Undervoltage Timing (All Waveforms Are Referenced to VEE)
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Figure 13. Overvoltage Timing (All Waveforms Are Referenced to VEE) Figure 12. Undervoltage Timing with an Overvoltage Glitch (All Waveforms Are Referenced to VEE)
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Figure 14. Circuit-Breaker Timing Behavior (All Waveforms Are Referenced to VEE) the L TC4252-2 activates a shutdown cooling cycle. pins are released at the same time (see Figure 24).
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Figure 16. Shutdown Cooling Timing Behavior of L TC4252-2 (All Waveforms Are Referenced to VEE) Figure 15. Pushbutton Reset of L TC4252-1’s Latched Fault
prevent SOA damage in a low impedance fault condition. GATE voltage is controlled by the current limit amplifier .
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Figure 17. Current Limit Behavior (All Waveforms Are Referenced to VEE)
- POWERSUPPLY(MIN) =1.064•POWER SUPPLY(MIN) (17) when V SUPPL Y = 0.5 • (VSUPPL Y(MIN) + VSUPPL Y(MAX)) = 57V . The peak power at the fault current limit occurs at the supply overvoltage threshold. The fault current limited power is: POWERFAULT = VSUPPLY RS
- V ACL –V SUPPLY –VZ() • R6 (18) TIMER GATE SENSE SS DRAIN VTMRH VDRNCL VACL VCB VDRNL VGS(th) VIN – VGATEH VTMRL
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Figure 18. Soft-Start Timing (All Waveforms Are Referenced to VEE)
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Figure 19. Power Limit Circuit Breaking Application don’t require short-circut protection from the L TC4252A. where IGATE = 58μA and CL is the total load capacitance. tarily turning on when the power pins first make contact.
- C2+C GD(Q1)() (20) C3 ≈ 35 • C2 for V SUPPL Y(MAX) = 71V where VGS(TH),Q1 is the MOSFET’s minimum gate threshold and VSUPPL Y(MAX) is the maximum operating input voltage. Diode-ORing Figure 22 shows the L TC4252 used as diode-oring with Hot Swap capability in a dual – 48V power supply application. The conventional diode-OR method uses two high power diodes and heat sinks to contain the large heat dissipation of the diodes. With the L TC4252 controlling the external FETs Q2 and Q3 in a diode-OR manner , the small turn-on voltage across the fully enhanced Q2 and Q3 reduces the power dissipation significantly.
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Figure 20. Circuit Breaker with Foldback Current Limit Application Figure 21. Inrush Control Without a Sense Resistor Application a start-up cycle and ramp up the SS and GATE voltage. and Q8 VDS drop is negligible.
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Figure 22. –48V/2.5A Diode-OR Application
Q2 and Q3 are in analog current limit. Q3 to the load module via the Hot Swap section. B supply is equal to the channel A supply. Q3 of channel B diode-OR circuit to turn off. at the output of Q1 is protected by the Hot Swap section. Figure 23. When using a filter , an optoisolator is required
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Figure 23. Typical Application Using a Filter Module
(Reference L TC DWG # 05-08-1660 Rev F) MSOP (MS8) 0307 REV F 0.53 ± 0.152 (.021 ± .006) SEATING PLANE NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 0.18 (.007) 0.254 (.010) 1.10 (.043) MAX 0.22 – 0.38 (.009 – .015) TYP 0.1016 ± 0.0508 (.004 ± .002) 0.86 (.034) REF 0.65 (.0256) BSC 0° – 6° TYP DETAIL “A” DETAIL “A” GAUGE PLANE 12 3 4 4.90 ± 0.152 (.193 ± .006) 8 7 6 5 3.00 ± 0.102 (.118 ± .004) (NOTE 3) 3.00 ± 0.102 (.118 ± .004) (NOTE 4) 0.52 (.0205) REF 5.23 (.206) MIN 3.20 – 3.45 (.126 – .136) 0.889 ± 0.127 (.035 ± .005) RECOMMENDED SOLDER PAD LAYOUT 0.42 ± 0.038 (.0165 ± .0015) TYP 0.65 (.0256) BSC MSOP (MS) 0307 REV E 0.53 ± 0.152 (.021 ± .006) SEATING PLANE 0.18 (.007) 1.10 (.043) MAX 0.17 – 0.27 (.007 – .011) TYP 0.86 (.034) REF 0.50 (.0197) BSC 12 3 45 4.90 ± 0.152 (.193 ± .006) 0.497 ± 0.076 (.0196 ± .003) REF8910 7 6 3.00 ± 0.102 (.118 ± .004) (NOTE 3) 3.00 ± 0.102 (.118 ± .004) (NOTE 4) NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 0.254 (.010) 0° – 6° TYP DETAIL “A” DETAIL “A” GAUGE PLANE 5.23 (.206) MIN 3.20 – 3.45 (.126 – .136) 0.889 ± 0.127 (.035 ± .005) RECOMMENDED SOLDER PAD LAYOUT 0.305 ± 0.038 (.0120 ± .0015) TYP 0.50 (.0197) BSC 0.1016 ± 0.0508 (.004 ± .002) 10-Lead Plastic MSOP (Reference L TC DWG # 05-08-1661 Rev E) PACKAGE DESCRIPTION Please refer to http://www.linear .com/designtools/packaging/ for the most recent package drawings.
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However , no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER C 2/11 Revised Typical Application drawings Revised Figures 2, 3, 4, 19, 20, 21, 22 and 23 Replaced Shunt Regulator section in Applications Information 1, 36 12, 14, 15, 30, 31, 32, 33 D 3/12 Not recommended for new designs 1 (Revision history begins at Rev C)
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Figure 24. – 48V/5A Application