LT4220

LT4220 LINER

Document overview

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Technical content

n –2.7V to –16.5V Operation n Analog Current Limit with Foldback n Allows Safe Board Insertion and Removal from a Live Backplane n Open-Collector Power Good Comparators n Automatic Retry or Latchoff After a Current Fault n Dual Undervoltage Lockout Comparator Inputs n Current Fault Indication n Live Board Insertion n RAID Systems n –5.2V ECL Supplies n Industrial Controls n Split Supply Systems , LTC and LT are registered trademarks of Linear Technology Corporation. The LT 4220 16-pin dual voltage Hot Swap controller allows a board to be safely inserted and removed from a live backplane. The device operates with any combination external N-channel pass transistors, the board supply voltages can be ramped up at an adjustable rate. A select- able tracking mode allows dual supply tracking control for ramping the positive and negative supplies together. The LT4220 features foldback current limit and latches off both gates if either supply remains in current limit longer than an adjustable time period. The IC can be configured for automatic restart after a delay set by the same timer. A power good signal indicates when the output voltages monitored by the two FB comparators are within tolerance, and the gate drive signals are at their full on voltage. The LT4220 is available in a 16-lead narrow SSOP package. Hot Swap is a trademark of Linear Technology Corporation. VCC ON+ 1µF 1µF 4.99k 36.5k 4.99k 36.5k –12V VEE 12V VCC FAULT TIMER GND TRACK ON– PWRGD FB+ R10 4.99k 36.5k 12V VOUT+ R12 4.99k R11 36.5k

4220 TA01

–12V V OUT– 10Ω FB SENSE+ RS+ 0.005Ω RS– 0.005Ω GATE+ 10Ω 10nF 10nF 100nF SUB85N03-04 VEE SENSE–SENSEK LT4220 GATE– SUB85N03-04 CL2 CL1 Z2* R14 10Ω CONNECTOR 1 CONNECTOR 2 100nF Z1* R13 10Ω VIN+ VIN– * 1SMA13AT3 TRANSIENT VOLTAGE SUPPRESSOR 71 6 15 14 12 34 R15 20k R16, 20k 10nF 10nF IN4001 IN4001 –12V 10A Hot Swap Controller 12V VIN+ 12V VOUT+ –12V VIN– –12V VOUT– TIME (10ms/DIV)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VCC VCC Operating Range l 2.7 16.5 V ICC VCC Supply Current l 2.7 4 mA VEE VEE Operating Range l –2.7 –16.5 V IEE VEE Supply Current –1.6 –2.4 mA VPLKO VCC Undervoltage Lockout l 2.35 2.45 2.55 V VMLKO VEE Undervoltage Lockout l –2.4 –2.45 –2.5 V VON+H ON+ ON Threshold ON + Rising l 1.22 1.24 1.26 V VON+HYS ON+ Hysteresis l 25 50 70 mV VON–HYS ON– Hysteresis l 25 50 70 mV VON–H ON– ON Voltage Threshold ON – Falling l –1.22 –1.24 –1.26 V ION+ ON+ Input Current V ON+ = 2V l 0.01 –1 mA ION– ON– Input Current V ON– = GND l 0.01 –1 mA VFB+H FB+ PWRGD Voltage Threshold FB + Rising l 1.22 1.24 1.26 V VFB+HYS FB+ Hysteresis Gate = 5V l 25 50 70 mV VFB–H FB– PWRGD Voltage Threshold FB – Falling l –1.22 –1.24 –1.26 V VFB–HYS FB– Hysteresis Gate = 3V l 25 50 70 mV (Notes 1, 2) Operating Temperature Range ABSOLUTE MAXIMUM RATINGSW WW U PACKAGE/ORDER INFORMATIONW UU ORDER PART NUMBER LT4220CGN LT4220IGN GN PART MARKING 4220 4220I TJMAX = 125°C, qJA = 130°C/W The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 5V, VEE = –5V, unless otherwise noted. Consult LTC Marketing for parts specified with wider operating temperature ranges. GN PACKAGE 16-LEAD PLASTIC SSOP TOP VIEW V EE SENSEK SENSE– GATE– FB– ON– TRACK TIMER VCC SENSE+ GATE+ FB+ ON+ FAULT PWRGD GND DC ELECTRICAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS IINFB+ FB+ Input Current FB + = 3V l 0.09 –1 mA IINFB– FB– Input Current FB – = –3V l 0.08 –1 mA VSENSE+ SENSE+ Trip Voltage (VCC – VSENSE+)V FB+ = 0V, GATE+ – 0.5V l 61 5 2 2 m V VFB+ = 1V, GATE+ – 0.5V 36 48 60 mV VSENSE– SENSE– Trip Voltage (VSENSEK – VSENSE–)V FB– = 0V, GATE– – 0.5V l –10 –15 –22 mV VFB– = –1V, GATE– – 0.5V –43 –52 –61 mV IGATEUP+ GATE+ Pull-Up Current Charge Pump On, V GATE+ = 7V l –9 –13 –17 mA IGATEUP– GATE– Pull-Up Current V GATE– = –3V l –6 –10 –14 mA IGATEDN+ GATE+ Pull-Down Current Any Fault Condition, V GATE+ = 1V l 20 40 60 mA IGATEDN– GATE– Pull-Down Current Any Fault Condition, V GATE– = VEE + 4V l 30 70 130 mA DVGATE+ External N-Channel GATE+ Drive V GATE+ – VCC, VCC = 2.7V, VEE = –2.7V l 3.5 4 6 V VCC = 5V to 16.5V, VEE = –5V to –16.5V 5 6.5 8 V DVGATE– External N-Channel GATE– Drive V GATE– – VEE, VCC = 2.7V, VEE = –2.7V l 3.5 5.2 6 V VCC = 5V to 16.5V, VEE = –5V to –16.5V 7.5 8.5 9 V VTIMERH TIMER High Threshold, Sets FAULT l 1.22 1.24 1.26 V VTIMERL TIMER Low Threshold, Allows Restart l 0.4 0.5 0.6 V ITIMERUP TIMER Pull-Up Current TIMER = 0V l –40 –65 –85 mA ITIMERDN TIMER Pull-Down Current TIMER = 1V l 2 3.3 4.5 mA ITIMER(R) TIMER Current Ratio I TIMERDN/ITIMERUP 57 % VOL PWRGD Output Low Voltage I O = 2mA l 0.3 V IO = 5mA 0.5 V IOH PWRGD Leakage Current V PWRGD = 16.5V l 0.1 2 mA VFOL FAULT Output Low Voltage I O = 2mA l 0.3 V IO = 5mA 0.5 V IFPH FAULT Leakage Current V FAULT = 16.5V l 0.06 2 mA VTRKTHR TRACK Input Threshold l 0.3 0.8 1.1 V ITRK TRACK Input Current TRACK = 16.5V l 0.05 2 mA VTRKFB+ TRACK Mode FB+ Threshold I GATE+ = 0mA, TRACK = VCC (Note 3) l 40 70 mV VTRKFB– TRACK Mode FB– Threshold I GATE– = 0mA, TRACK = VCC (Note 3) l 40 80 mV DC ELECTRICAL CHARACTERISTICSThe l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 5V, VEE = –5V, unless otherwise noted.

The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 5V, VEE = –5V, unless otherwise noted. AC ELECTRICAL CHARACTERISTICS TYPICAL PERFOR A CE CHARACTERISTICS UW SUPPLY VOLTAGE (V) SUPPLY CURRENT (mA)

4220 G01

FB+ VOLTAGE (V) –1.5 VCC-SENSE+ VOLTAGE (mV) –1.0 –0.5 0 0.5

4220 G02

FB– VOLTAGE (V) SENSEK-SENSE– VOLTAGE (mV)

4220 G03

TA = 25°C ICC IEE VCC = 5V VEE = –5V ON+ = 2V ON– = –2V TA = 25°C VCC = 5V VEE = –5V ON+ = 2V ON– = –2V TA = 25°C Positive Circuit Breaker Sense Voltage vs FB+ Voltage Negative Circuit Breaker Sense Voltage vs FB– VoltageSupply Current vs Supply Voltage SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS tPHLON+ ON+ Low to GATE+ Low 5k Pull-Up to GATE +, 1nF Load Capacitor l 0.6 0.8 1.2 ms tPLHON+ ON+ High to GATE+ High 5k Pull-Up to GATE +, 1nF Load Capacitor l 0.6 1.5 3 ms tPHLFB+ FB+ Low to PWRGD Low 5k Pull-Up to PWRGD l 0.5 0.8 1.2 ms tPLHFB+ FB+ High to PWRGD High 5k Pull-Up to PWRGD l 0.6 1.25 3 ms tPHLON– ON– Low to GATE– Low 5k Pull-Up to GATE –, 1nF Load Capacitor l 0.6 1 1.5 ms tPLHON– ON– High to GATE– High 5k Pull-Up to GATE –, 1nF Load Capacitor l 1 2.1 3.5 ms tPHLFB– FB– Low to PWRGD Low 5k Pull-Up to PWRGD l 0.6 1 1.5 ms tPLHFB– FB– High to PWRGD High 5k Pull-Up to PWRGD l 0.8 1.25 2 ms tSENSE+ SENSE+ to GATE+ Low 1nF On GATE +, 100mV Step, 5k Pull-Up l 146 ms tSENSE– SENSE– to GATE– Low 1nF On GATE –, 100mV Step, 5k Pull-Up l 146 ms Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: All currents into device pins are positive; all currents out of device pins are negative. All voltages referenced to ground (GND) unless specified. Note 3: The absolute voltage difference between FB+ and FB– required to force either the GATE+ or GATE– current to 0mA.

GATE+ Pull-Down Current vs GATE+ Voltage TYPICAL PERFOR A CE CHARACTERISTICS UW GATE+ Drive vs VCC VCC (V) 306 9 1 2 1 5 1 8

4220 G04

GATE+ DRIVE (VGATE+ – VCC) (V) VEE = –5V VEE = –2.7V TA = 25°C VCC (V) 306 9 1 2 1 5 1 8

4220 G11

TIMER PULL-UP CURRENT (µA) TA = 25°C VEE (V) 306 9 1 2 1 5 1 8

4220 G05

GATE– DRIVE (VGATE– – VEE) (V) VCC = 5V TA = 25°C GATE+ VOLTAGE (VGATE+ – VCC) (V) GATE+ PULL-UP CURRENT (µA)

4220 G06

+ VOLTAGE (V) GATE+ PULL-DOWN CURRENT (mA)

4220 G07

– VOLTAGE (VGATE– – VEE) (V) GATE– PULL-DOWN CURRENT (mA)

4220 G09

VCC = 5V VEE = –5V ON– = 0V FB– = –2V TA = 25°C GATE– VOLTAGE (VGATE– – VEE) (V) GATE– PULL-UP CURRENT (µA)

4220 G08

VCC = 5V VEE = –5V SENSE+ = VCC SENSE– = VEE TA = 25°C VOL (mV) SINK CURRENT (mA)

4220 G10

VCC = 5V VEE = –5V TA = 25°C PWRGD FAULT TEMPERATURE (°C) –40 45.0 44.5 44.0 43.5 43.0 42.5 42.0 41.5 41.0 20 60

4220 G12

–20 0 40 80 HYSTERESIS VOLTAGE (mV) VCC = 5V VEE = –5V VSENSE+ = VCC VSENSE– = VEE TA = 25°C VCC = 5V VEE = –5V ON+ = 0V FB+ = 2V TA = 25°C VCC = 2.7V PWRGD and FAULT VOL vs Sink Current GATE– Pull-Up Current vs GATE– Voltage GATE+ Pull-Up Current vs GATE+ VoltageGATE– Drive vs VEE GATE– Pull-Down Current vs GATE– Voltage TIMER Pull-Up Current vs VCC ON+, ON– and FB+, FB– Hysteresis vs Temperature

TYPICAL PERFOR A CE CHARACTERISTICS UW FB+ and ON+ Threshold Voltage vs Temperature TEMPERATURE (°C) –40 1.241 1.240 1.239 1.238 1.237 1.236 1.235 20 60

4220 G13

–20 0 40 80 –40 20 60–20 0 40 80 –40 20 60–20 0 40 80 –40 20 60–20 0 40 80 THRESHOLD VOLTAGE (V) TEMPERATURE (°C) –1.241 –1.240 –1.239 –1.238 –1.237 –1.236 –1.235

4220 G14

THRESHOLD VOLTAGE (V) TEMPERATURE (°C)

4220 G15

TIMER PULL-UP CURRENT (µA) TEMPERATURE (°C)

4220 G16

GATE+, GATE– PULL-UP CURRENT (µA) GATE+ GATE– FB– and ON– Threshold Voltage vs Temperature TIMER Pull-Up Current vs Temperature GATE+, GATE– Pull-Up Current vs Temperature

VEE (Pin 1): Negative Supply. The negative supply input ranges from –2.7V to –16.5V for normal operation. IEE is typically –1.6mA. An internal undervoltage lockout circuit disables the device for inputs greater than –2.45V. A 10W , 1mF RC bypass network from VIN– to the VEE pin decouples transients from the device. SENSEK (Pin 2): Negative Supply Current Limit Kelvin Sense Pin. Connect to VIN–. SENSE– (Pin 3): Negative Supply Current Limit Sense Pin. A sense resistor is placed in the supply path between SENSEK and SENSE –. The current limit circuit will regulate the voltage across the sense resistor to –50mV (SENSEK – SENSE–) when the FB– voltage is less than –0.7V. If VFB– goes above –0.7V, the voltage across the sense resistor decreases linearly and stops at –15mV when VFB– is 0V. If current limit is not used, connect to SENSEK. GATE– (Pin 4): Gate Drive for the External Negative Supply N-Channel FET. An internal 10mA current source drives the pin. An external capacitor connected from the GATE– pin to VOUT– will control the rising slope of the VOUT– signal. The voltage is clamped to 9V above VEE. When the current limit is reached, the GATE– pin voltage will be adjusted to maintain a constant voltage across the RS– resistor while the timer capacitor starts to charge. If the TIMER pin voltage exceeds 1.24V, the fault latch will be set and both GATE– and GATE+ pins will be pulled low. The GATE– pin is pulled to V EE whenever the ON+ pin is below 1.24V, the ON– pin is above –1.24V, or either supply is in the undervoltage lockout voltage range, or the fault latch is set by the TIMER pin rising above 1.24V. FB– (Pin 5): Negative Power Good Comparator Input. This pin monitors the negative output voltage (VOUT–) with an external resistive divider. When the voltage on FB – is below –1.24V and the initial GATE – drive voltage has reached a maximum (indicated by setting the internal GATE– good latch) and the FB+ release conditions are met, the PWRGD pin is released. PWRGD is pulled low when the FB– pin is above –1.185V. Note the PWRGD pin is wire- ORed with the FB+ pin conditions. FB– also controls the negative supply current limit sense amplifier input offset to provide foldback current limit. The FB– pin linearly reduces the negative supply sense ampli- fier offset from –52mV to –15mV for FB – in the range –0.75V < FB– < 0V. To disable VEE PWRGD and foldback current limit, the FB– pin should be set to a voltage in the range: –1.3V > FB– > VEE + 0.5V but should never be more negative then –5.8V for normal operation. ON– (Pin 6): The Negative Supply Good Comparator Input. This pin monitors the negative input voltage (VEE) with an external resistive divider for undervoltage lockout. When the voltage at the ON– pin is below the VON–H high-to-low threshold (–1.24V), the negative supply is considered good. If the ON – pin rises above –1.185V, both GATE– and GATE+ are pulled low. If ON – is not used, the ON – pin should be set to –1.3V > ON– > VEE + 0.5V. TRACK (Pin 7): Supply Tracking Mode Control. If the TRACK pin is pulled high, the internal supply tracking circuit will be enabled during start-up. The TRACK circuit monitors the FB + and the FB– pins to keep their magnitude within a small voltage range by controlling the GATE+ and GATE– charge currents. The tracking is disabled when either FB comparator indicates the output is good. Tracking is re- enabled if ON+ is pulled below 1.185V, ON– is pulled above –1.185V or either supply is below the internal undervoltage lockout. Typically, the TRACK pin is tied to GND or to V CC. If left floating, tracking is enabled. TIMER (Pin 8): Fault Time Out Control. An external timing capacitor at this pin programs the maximum time the part is allowed to remain in current limit before issuing a fault and turning off the external FETs. Additionally, for autorestart, this pin controls the time before an autorestart is initiated. When the part goes into current limit, a 65 mA pull-up current source starts to charge the timing capacitor. When the voltage reaches V TIMERH (1.24V), the internal fault latch is set, FAULT pulls low and both GATE pins are pulled low; the pull-up current will be turned off and the capacitor is discharged by a 3.3 mA pull-down current. When the TIMER pin falls below 0.5V, the part is allowed to restart if the ON + pin is pulsed below 1.185V, thereby resetting internal fault latch—typically done by connecting the

FAULT pin to the ON + pin, otherwise the part remains latched off. To disable the timeout circuit breaker, connect the TIMER pin to GND. GND (Pin 9): Supply Ground Pin. PWRGD (Pin 10): Open-Collector Output to GND. PWRGD goes to high impedance after the initial GATE – and final GATE+ pins have reached their maximum voltage and after the FB+ pin goes above 1.24V low-to-high threshold and after the FB– pin falls below –1.24V high-to-low threshold. An external pull-up resistor can pull the pin to a voltage higher or lower than VCC. If not used, PWRGD can be left floating or tied to GND. FAULT (Pin 11): Open-Collector Output to GND. The FAULT pin is pulled low whenever the TIMER pin rises above V TIMERH (1.24V) threshold, thereby setting the internal fault latch. It goes to high impedance whenever the internal fault latch is reset. The fault latch is reset with either internal undervoltage lockout conditions, or by the ON comparators if the TIMER pin is also below 0.5V. If not used, the FAULT pin can be left floating or tied to GND. ON + (Pin 12): Positive Supply Good Comparator Input. It monitors the positive input voltage (VCC) with an external resistive divider for undervoltage lockout. When the volt- age on ON + is above the V ON+H high-to-low threshold (1.24V) the positive supply is considered good. If ON + drops below 1.185V, both GATE – and GATE + are pulled low. If ON+ is pulled low after a current limit fault and when the TIMER pin is below 0.5V, the fault latch is reset allowing the part to turn back on. Typically the FAULT pin is tied back to the ON + pin for autorestart. If not used, the ON+ pin should be set to a voltage in the range of 1.3V < ON+ < VCC + 0.3V. The ON+ pin requires a bypass capacitor connected to ground. FB+ (Pin 13): Positive Power Good Comparator Input. This pin monitors the positive output voltage (VOUT+) with an external resistor divider. When the voltage on FB+ is above the VFB+H low-to-high threshold (1.24V) and the GATE + drive voltage has reached a maximum, the PWRGD is released. PWRGD is pulled low when the FB+ pin is below 1.185V. The PWRGD pin is wire-ORed with the FB – pin conditions. FB+ also controls the positive current limit sense amplifier input offset to provide foldback current limit. The FB+ pin linearly reduces the positive sense amplifier offset from 48mV to 15mV for FB+ in the range 0.85V > FB+ > 0V. If PWRGD and foldback current limit are not used, the FB+ pin should be set to a voltage in the range of 1.3V < FB+ < VCC + 0.3V. GATE+ (Pin 14): High Side Gate Drive for the External Positive Supply N-Channel FET. An internal charge pump guarantees at least 3.5V above VCC, for supply voltages at –2.7V increasing to a minimum of 5V above VCC for supply voltages greater than –5V. A 10mA pull-up current source drives the pin. An external capacitor connected from the GATE + pin to GND will control the rising slope of the GATE+ signal. The voltage is clamped to 7V above VCC. When the current limit is reached, the GATE+ pin voltage will be adjusted to maintain a constant voltage across the RS+ resistor while the timer capacitor starts to charge. If the TIMER pin voltage exceeds 1.24V, the GATE+ pin will be pulled low. The GATE+ pin is pulled to GND whenever the ON+ pin is below 1.24V, the ON– pin is above –1.24V, either supply is in the undervoltage lockout voltage range, or the TIMER pin rises above 1.24V. SENSE+ (Pin 15): Positive Supply Current Limit Sense Pin. A sense resistor must be placed in the supply path be- tween V CC and SENSE +. The current limit circuit will regulate the voltage across the sense resistor to 50mV CC – SENSE +) when the FB + voltage is greater than 0.85V. If VFB+ goes below 0.85V, the voltage across the sense resistor decreases linearly and stops at 15mV when V FB+ is 0V. VCC (Pin 16): Positive Supply. The positive supply input ranges from 2.7V to 16.5V for normal operation. I CC is typically 2.7mA. An internal undervoltage lockout circuit disables the chip for inputs less than 2.45V. Place a 0.1mF bypass capacitor next to the VCC pin.

1.24V –1.24V UVLO VCC AND VEE GOOD FB+ ON– 1.24V 0.5V 1.24V ON+ FB– –1.24V P GATE GOOD N GATE GOOD TRACK VEE VCC VCC

1 GND9 16

S R Q S R Q S R Q Q Q Q S R R Q Q

10 PWRGD

11 FAULT

15 SENSE+

3µA 10µA 10µAON ON EN TRACK FB+ 60µACURRENT LIMIT FROM SENSE AMPS GATE–4 SENSEK 4220 BD SENSE–3

8 TIMER

+ – + – 53mV 52mV

4220 F01

Figure 1. ON+-to-GATE+ Timing Figure 2. FB +-to-PWRGD Timing

4220 F02

4220 F04

Figure 3. ON–-to-GATE– Timing Figure 4. FB –-to-PWRGD Timing

4220 F05

4220 F06

Figure 5. SENSE+-to-GATE+ Timing Figure 6. SENSE–-to-GATE– Timing currents from the backplane power bus as they charge up. are ready or if an overcurrent time-out fault has occurred.

FB– pins within 50mV of each other.

4220 F07

Figure 7. Hot Swap Controller on Daughter Board with Tracking Disabled voltage tracking when TRACK is enabled.

fully on, the PWRGD pin will go high impedance. lockout thresholds are exceeded. the N-channel FET threshold voltage. N-channel FET due to C2 slew rate control. 5) GATE+ internal gate good signal threshold is reached. transient loads with small capacitive loads. tarily turning on when the power pins first make contact. ensure tracking over temperature.

4220 F08

Figure 8. Typical Timing Sequence

APPLICATIO S I FOR ATIOWU UU Current Limit/Electronic Circuit Breaker The LT4220 features foldback current limit with an elec- tronic circuit breaker that protects against short-circuits or excessive supply currents. The current limit is set by placing sense resistors between V CC (Pin 16) and SENSE+ (Pin 15) and between SENSEK (Pin 2) and SENSE– (Pin 3). An adjustable timer will trip an electronic circuit breaker if the part remains in current limit for too long. To prevent excessive power dissipation in the pass tran- sistors and to prevent voltage spikes on the input supply during overcurrent conditions at the output, the current folds back as a function of the output voltage, which is sensed at the feedback pins FB + and FB– . When the voltage at the FB+ (or FB–) pin is 0V, the sense amplifier offset is 15mV (–15mV), and limits the current to ILIMIT = 15mV/ RS+ (–15mV/RS–). As the output voltage increases, the sense amplifier offset increases until the FB + (or FB –) voltage reaches 0.85V (–0.75V), At which point the cur- rent limit reaches a maximum of I LIMIT = 48mV/R S+ (– 52mV/RS–). Timer Function and Autorestart The TIMER pin (Pin 8) provides a method for setting the maximum time the LT4220 is allowed to operate in current limit. When the current limit circuitry is not active, the TIMER pin is pulled to GND by a 3.3 mA current sink. Whenever the current limit circuit becomes active, by either a positive or negative sense amplifier operating in current limit, a 65mA pull-up current source is connected to the TIMER pin and the voltage rises with a slope equal to dV/dt = 65mA/CTIMER. The desired current limit time (t) can be set with a capacitor value of: CTIMER = t • 65mA/1.24V (4) If the current limit circuit turns off, the TIMER pin will be discharged to GND at a rate of: dV/dt = 3.3mA/CTIMER (5) Whenever the TIMER pin ramps up and reaches the 1.24V threshold, the internal fault latch is set and the FAULT pin (Pin 11) is pulled low. GATE + is pulled down to ground, GATE– is pulled down to V EE, and the TIMER pin starts ramping back to GND by the 3.3mA current sink. After the fault latch is set, the LT4220 can be restarted by pulling the ON+ pin low after the TIMER pin falls below 0.5V. The LT4220 can also be restarted by cycling either supply beyond its UVLO. Otherwise the part remains latched off. For autorestart, the FAULT pin can be tied to the ON+ pin. The autorestart will occur after the TIMER pin falls below 0.5V. Undervoltage Detection The ON+ and ON– pins can be used to detect an undervoltage condition at the power supply inputs. The ON + and ON– pins are connected to analog comparators with 50mV of hysteresis. If the ON+ pin falls below its threshold voltage or the ON– pin rises above its threshold voltage, the GATE pins are pulled low and held low until the ON+ and ON– pins exceed their turn-on thresholds (1.24V and –1.24V). Ex- ternal capacitance at the ON pins may be required to filter supply ringing from crossing the ON comparator thresh- old. Additionally there is an internal undervoltage lockout on both supplies of approximately V CC < 2.45V and V EE > –2.45V. If either supply is in UVLO, both GATE pins will be pulled low and all internal latches will be reset. ON– Protection If the ON– pin is driven directly and not connected to the negative supply through a resistor divider, a 10k resistor must be connected between the driver and the ON – pin. Power Good Detection The LT4220 includes two comparators for monitoring the output voltages. The FB+ and the FB– pins are compared against 1.24V and –1.24V internal references respectively. The comparators exhibit 50mV of hysteresis. The com- parator outputs are wire-ORed to the open collector PWRGD pin that is enabled once both GATE + and GATE– pins have reached their maximum gate drive voltage as indicated by the internal gate good latches. The PWRGD pin goes high impedance when both FB + and FB– inputs exceed VFB+H and VFB–H thresholds, GATE+ is fully on and Gate– initially has been fully on.

APPLICATIO S I FOR ATIOWU UU Supply Tracking If the TRACK pin (Pin 7) is high the supply power-up tracking mode is enabled. This feature forces both sup- plies to reach their final value at the same time, during power-up and for faults that drive the output supplies to zero. During this mode the GATE pins are controlled to keep the differential magnitude of the FB pins to within 50mV. The FB pins are scaled versions of the output voltages. Therefore, control of the FB pins, via the GATE pins, will control the output voltages at the same scale. |DV FB(TRK)| = |VFB+ – VFB–| (6) Supply tracking will continue until: either FB pin reaches the associated PWRGD threshold. If any fault condition occurs that turns the GATE pins off, supply tracking will be reenabled. The GATE off conditions include: (1) either ON pin detects undervoltage, (2) internal undervoltage lock- out, (3) the fault latch is set by a current limit time-out. V EE Bypassing The VEE supply pin should be filtered with an RC network to reduce high dV/dt slew rates from disturbing internal circuits. Typical RC bypassing sufficient to prevent circuit misbehavior is R14 = 10 W and C5 = 1 mF. The GATE –, SENSEK and SENSE– pins have been designed such that they can be pulled below or above VEE for short periods of time while the VEE pin is reaching its steady state voltage. If desired, a higher R14 • C5 time constant may be used to prevent short circuit transients from tripping the V EE undervoltage lockout circuit at –2.45V. R14 should be sufficient to decouple C5 from causing transients on VIN– during live insertion. Under the condition of a short circuit on VOUT–, parasitic inductance and resistance in the VIN– path will cause VIN– to collapse toward 0V causing the VEE pin voltage to also discharge toward 0V before the external FET can be turned off (typically 7ms to 10ms). To prevent a UVLO condition from occurring, the R14 • C5 time constant should be sufficient to hold the V EE pin voltage out of the VEE UVLO voltage range. If the V EE pin reaches its UVLO voltage, GATE+ will also be pulled low. For the case where C3 is large, causing an even slower N-channel FET turnoff, higher RC bypassing may be necessary to prevent tripping the V EE UVLO. ON+, ON– Bypass Capacitors Bypass capacitors are required from ON+ to ground and ON– to ground. A typical time constant is: TC (ON+) = (R1||R2)C7 = 44ms TC (ON–) = (R3||R4)C8 = 44ms Supply Ringing Normal circuit design practice calls for capacitive bypass- ing of the input supply to active devices. The opposite is true for Hot Swap circuits that are connected into a backplane, where capacitive loading would cause tran- sients during an abrupt connection to the backplane. With little or no capacitive decoupling on the powered side of the N-channel FETs, connection transients or load tran- sients will typically cause ringing on the supply leads due to parasitic inductance. It is recommended to use a snubber circuit comprising of a series 10 W and 0.1 mF capacitor to dampen transient ringing. The supply decoupling circuit on the V EE pin also provides a snubber for VIN–. Additionally, if the supply voltage overshoot can exceed the –22V maximum rating on the part, a transient voltage suppressor is recommended. Voltage transients can oc- cur during load short-circuit conditions, where parasitic inductance in the supply leads can build up energy before the external N-channel FET can be turned off. This is especially true for the negative side FET where a large C3 value slows the turn off of the N-channel FET. Subsequent overshoot when the FET is finally turned off can be as much as 2 · the supply voltage even with the snubber circuit. Additional protection using a transient suppressor may be needed to prevent exceeding the maximum supply voltage rating. Supply Reversal Protection A variety of conditions on V OUT+ and VOUT– may result in supply reversal. To protect devices connected to V OUT+ and V OUT– protection diodes should be used. 1N4001 diodes can be used for most aplications. Connection of these diodes (D1, D2) are shown in the front page Typical Application.

16-Lead Plastic SSOP (Narrow .150 Inch) (Reference LTC DWG # 05-08-1641) GN16 (SSOP) 0502 12 3 4 5 6 7 8 .229 – .244 (5.817 – 6.198) .150 – .157** (3.810 – 3.988) 16 15 14 13 .189 – .196* (4.801 – 4.978) 12 11 10 9 .016 – .050 (0.406 – 1.270) .015 – .004 (0.178 – 0.249) .053 – .068 (1.351 – 1.727) .008 – .012 (0.203 – 0.305) .004 – .0098 (0.102 – 0.249) .0250 (0.635) BSC .009 (0.229) REF .254 MIN RECOMMENDED SOLDER PAD LAYOUT .150 – .165 .0250 TYP.0165 – .0015 .045 –.005 *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE INCHES (MILLIMETERS) NOTE: 1. CONTROLLING DIMENSION: INCHES 2. DIMENSIONS ARE IN 3. DRAWING NOT TO SCALE Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

4220 F09

Figure 9. Hot Swap Controller on Mainboard with Tracking