LT3957A Datasheet | DigiCamel IC Datasheet

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Technical content

n Wide Input Voltage Range: 3V to 40V n Single Feedback Pin for Positive or Negative Output Voltage n Internal 5A/40V Power Switch n Current Mode Control Provides Excellent T ransient Response n Programmable Operating Frequency (100kHz to 1MHz) with One External Resistor n Synchronizable to an External Clock n Low Shutdown Current < 1μA n Internal 5.2V Low Dropout Voltage Regulator n Programmable Input Undervoltage Lockout with Hysteresis n Programmable Soft-Start n Thermally Enhanced QFN (5mm × 6mm) Package TYPICAL APPLICATION

DESCRIPTION

Boost, Flyback, SEPIC and Inverting Converter with 5A, 40V Switch The L T®3957A is a wide input range, current mode DC/DC converter which is capable of generating either positive or negative output voltages. It can be configured as either a boost, flyback, SEPIC or inverting converter. It features an internal low side N-channel power MOSFET rated for 40V at 5A and driven from an internal regulated 5.2V supply. The fixed frequency, current-mode architecture results in stable operation over a wide range of supply and output voltages. The operating frequency of LT3957A can be set with an external resistor over a 100kHz to 1MHz range, and can be synchronized to an external clock using the SYNC pin. A minimum operating supply voltage of 3V, and a low shutdown quiescent current of less than 1μA, make the LT3957A ideally suited for battery-powered systems. The LT3957A features soft-start and frequency foldback functions to limit inductor current during start-up. The LT3957A has improved load transient performance com- pared to the LT3957. L, L T, L TC, L TM, Linear Technology and the Linear logo are registered trademarks and No RSENSE and ThinSOT are trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 7825665. High Efficiency Output Boost Converter

FEATURES

APPLICATIONS

Efficiency vs Output Current SENSE2 SENSE1 LT3957A 10μH VIN SW GND FBX RT SS INTVCC EN/UVLO SYNC SGND 95.3k VC 3957A TA01a 200k 41.2k 300kHz 4.7μF0.33μF 6.8k 22nF 226k 15.8k 10μF VOUT 24V 600mA V IN 4.5V TO 16V 10μF OUTPUT CURRENT (mA) EFFICIENCY (%) 100 100 200 300 400 500 3957A TA01b 600 VIN = 12V

PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS Operating Junction Temperature Range (Note 1) 12 13 14 TOP VIEW SGND SW UHE PACKAGE 36-LEAD (5mm w 6mm) PLASTIC QFN 15 16 17 36 35 34 33 32 31 30 1 NC NC SENSE2 SGND SENSE1 SW SW NC INTV CC VIN EN/UVLO SGND SGND SW SW NC NC SYNC RT SS FBX V C GND GND GND GND GND GND 209 TJMAX = 125°C, θJA = 42°C/W, θJC = 3°C/W EXPOSED PAD (PIN 37) IS SGND, MUST BE SOLDERED TO SGND PLANE EXPOSED PAD (PIN 38) IS SW, MUST BE SOLDERED TO SW PLANE ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LT3957AEUHE#PBF LT3957AEUHE#TRPBF 3957A 36-Lead (5mm × 6mm) Plastic QFN –40°C to 125°C LT3957AIUHE#PBF LT3957AIUHE#TRPBF 3957A 36-Lead (5mm × 6mm) Plastic QFN –40°C to 125°C Consult L TC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temp- erature range, otherwise specifications are at TA ≈ TJ = 25°C. VIN = 24V, EN/UVLO = 24V, SENSE2 = 0V, unless otherwise noted. PARAMETER CONDITIONS MIN TYP MAX UNITS VIN Operating Range 34 0 V VIN Shutdown IQ EN/UVLO = 0V EN/UVLO = 1.15V 0.1 1 μA μA V IN Operating IQ VC = 0.3V, RT = 41.2k 1.7 2.3 mA VIN Operating IQ with Internal LDO Disabled V C = 0.3V, RT = 41.2k, INTVCC = 5.5V 350 400 μA SW Pin Current Limit l 5 5.9 6.8 A SW Pin On Voltage ISW = 3A 100 mV SENSE2 Input Bias Current Current Out of Pin –65 μA Error Amplifier FBX Regulation Voltage (VFBX(REG)) FBX > 0V (Note 3) FBX < 0V (Note 3) l l 1.569 –0.816 1.6 –0.800 1.631 –0.784 V V FBX Overvoltage Lockout FBX > 0V (Note 4) FBX < 0V (Note 4) FBX Pin Input Current FBX = 1.6V (Note 3) FBX = –0.8V (Note 3) –10 70 100 nA nA T ransconductance g m (ΔIVC /ΔFBX) (Note 3) 230 μS VC Output Impedance (Note 3) 5 MΩ VFBX Line Regulation (ΔVFBX/[ΔVIN • VFBX(REG)]) FBX > 0V, 3V < VIN < 40V (Notes 3, 6) FBX < 0V, 3V < VIN < 40V (Notes 3, 6) 0.04 0.03 0.06 0.06 %/V %/V V C Current Mode Gain (ΔVVC /ΔVSENSE) 10 V/V VC Source Current VC = 1.5V, FBX = 0V, Current Out of Pin –15 μA VC Sink Current FBX = 1.7V FBX = –0.85V μA μA V C Low Side Clamp Voltage FBX = 1.65V 0.8 V Oscillator Switching Frequency RT = 140k to SGND, FBX = 1.6V, VC = 1.5V RT = 41.2k to SGND, FBX = 1.6V, VC = 1.5V RT = 10.5k to SGND, FBX = 1.6V, VC = 1.5V 270 850 100 300 1000 120 330 1200 kHz kHz kHz RT Voltage FBX = 1.6V 1.2 V SW Minimum Off-Time 220 275 ns SW Minimum On-Time 240 320 ns SYNC Input Low 0.4 SYNC Input High 1.5 SS Pull-Up Current SS = 0V, Current Out of Pin –10 μA Low Dropout Regulator INTV CC Regulation Voltage l 5 5.2 5.45 V INTVCC Undervoltage Lockout Threshold Falling INTVCC UVLO Hysteresis 2.6 2.7 0.15 2.85 V V

ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temp- erature range, otherwise specifications are at TA ≈ TJ = 25°C. VIN = 24V, EN/UVLO = 24V, SENSE2 = 0V, unless otherwise noted. PARAMETER CONDITIONS MIN TYP MAX UNITS INTVCC Current Limit VIN = 40V VIN = 15V 32 40 55 mA mA INTVCC Load Regulation (ΔVINTVCC /V INTVCC) 0 < IINTVCC < 20mA, VIN = 8V –1 –0.5 % INTVCC Line Regulation (ΔVINTVCC /[ ΔVIN • VINTVCC]) 6V < VIN < 40V 0.02 0.05 %/V Dropout Voltage (VIN – VINTVCC)V IN = 5V, IINTVCC = 20mA, VC = 0V 450 mV INTVCC Current in Shutdown EN/UVLO = 0V, INTVCC = 6V 17 μA INTVCC Voltage to Bypass Internal LDO 5.5 V Logic Inputs EN/UVLO Threshold Voltage Falling VIN = INTVCC = 6V l 1.17 1.22 1.27 V EN/UVLO Voltage Hysteresis 20 mV EN/UVLO Input Low Voltage IVIN Drops Below 1μA 0.4 V EN/UVLO Pin Bias Current Low EN/UVLO = 1.15V 1.7 2 2.5 μA EN/UVLO Pin Bias Current High EN/UVLO = 1.33V 20 100 nA Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LT3957AE is guaranteed to meet performance specifications from the 0°C to 125°C operating junction temperature. Specifications over the –40°C to 125°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LT3957AI is guaranteed over the full –40°C to 125°C operating junction temperature range. Note 3: The LT3957A is tested in a feedback loop which servos V FBX to the reference voltages (1.6V and –0.8V) with the VC pin forced to 1.3V. Note 4: FBX overvoltage lockout is measured at VFBX(OVERVOL TAGE) relative to regulated VFBX(REG). Note 5: For 3V ≤ VIN < 6V, the EN/UVLO pin must not exceed VIN. Note 6: EN/UVLO = 1.33V when VIN = 3V. TYPICAL PERFORMANCE CHARACTERISTICS Positive Feedback Voltage vs Temperature, VIN Negative Feedback Voltage vs Temperature, V IN Quiescent Current vs Temperature, V IN TA ≈ TJ = 25°C, unless otherwise noted. TEMPERATURE (°C) –50 1580REGULATED FEEDBACK VOLTAGE (mV) 1590 1600 1605 0 50 75 1585 –25 25 100 125 3957A G01 VIN = 40V VIN = 24V VIN = 8V VIN = INTVCC = 3V , SHDN/UVLO = 1.33V TEMPERATURE (°C) –50 –804REGULATED FEEDBACK VOLTAGE (mV)–802 –800 –796 –798 –794 –788 –790 0 50 75 –792 –25 25 100 125 3957A G02 VIN = 40VVIN = 24V VIN = 8V VIN = INTVCC = 3V SHDN/UVLO = 1.33V TEMPERATURE (°C) –50

1.4 QUIESCENT CURRENT (mA)

1.6 1.8 0 50 75 1.5 1.7 –25 25 100 125 3957A G03 VIN = 40V VIN = 24V VIN = INTVCC = 3V

TYPICAL PERFORMANCE CHARACTERISTICSTA ≈ TJ = 25°C, unless otherwise noted. Dynamic Quiescent Current vs Switching Frequency RT vs Switching Frequency Normalized Switching Frequency vs FBX SWITCHING FREQUENCY (kHz) 100 IQ(mA) 300 500 600 700 200 400 900 8001000 3957A G04 SWITCHING FREQUENCY (kHz)

10 RT (kΩ)100

300 500 600 700100 200 400 900 8001000 3957A G05 FBX VOL TAGE (V) –0.8 NORMALIZED FREQUENCY (%)20 120 –0.4 0 0.4 0.8 3957A G06 1.2 1.6 100 Switching Frequency vs Temperature SW Pin Current Limit vs Temperature TEMPERATURE (°C) –50 275 SWITCHING FREQUENCY (kHz) 280 285 290 295 300 305 310 325 –25 02 5 7 5 50 3957A G07 100 125 315 320 RT = 41.2k TEMPERATURE (°C) –50 5.4 SW PIN CURRENT LIMIT (A) 6.0 5.8 6.2 6.4 6.6 0 50 75 5.6 –25 25 100 125 3957A G08 SW Pin Current Limit vs Duty Cycle DUTY CYCLE (%) 5.4 5.6 5.8 SW PIN CURRENT LIMIT (A) 6.2 20 40 80 60 6.6 6.0 6.4 100 3957A G09 EN/UVLO Threshold vs Temperature EN/UVLO Current vs Voltage EN/UVLO Hysteresis Current vs Temperature TEMPERATURE (°C) –50 1.18 1.22 1.24 1.28 0 50 75 1.20 –25 25 100 125 1.26 3957A G10 EN/UVLO VOLTAGE (V) EN/UVLO RISING EN/UVLO FALLING EN/UVLO VOL TAGE (V) EN/UVLO CURRENT (μA) 10 30 20 3957A G11 TEMPERATURE (°C) –50 1.6 IEN/UVLO (μA) 1.8 2.0 2.2 2.4 0 50 75–25 25 100 125 3957A G12

vs Current, Temperature INTVCC vs Temperature INTVCC Minimum Output Current Limit vs VIN INTVCC Load Regulation TYPICAL PERFORMANCE CHARACTERISTICSTA ≈ TJ = 25°C, unless otherwise noted. TEMPERATURE (°C) –50 5.0 INTVCC (V) 5.1 5.2 5.3 5.4 0 50 75–25 25 100 125 3957A G13 10 100 TJ = 125°C INTVCC = 3V VIN (V) 3957A G14 INTVCC CURRENT (mA) INTVCC LOAD (mA) 4.8 5.0 5.1 5.2 5.3 30 50 60 4.9 10 20 40 3957A G15 INTVCC VOLTAGE (V) VIN = 6V VIN (V) INTVCC VOL TAGE (V) 5.25 5.20 10 15 255 20 30 35 40 5.15 5.10 5.30 3957A G16 INTVCC LOAD (mA) DROPOUT VOL TAGE (mV) 600 400 500 200 300 5 1 01 52 0 100 700 3957A G17 125°C 25°C 0°C –40°C 75°C VIN = 5V Internal Switch On-Resistance vs Temperature TEMPERATURE (°C) –50 ON-RESISTANCE (mΩ) –25 25 0 50 75 100 125 3957A G18 Internal Switch On-Resistance vs INTVCC SEPIC Typical Start-Up Waveforms SEPIC FBX Frequency Foldback Waveforms During Overcurrent INTVCC (V) ON-RESISTANCE (mΩ) 27.8 28.0 27.6 27.4 27.2 45 7 68 27.0 26.8 26.6 28.2 3957A G19 5ms/DIV SEE TYPICAL APPLICATION: 5V TO 16V INPUT , 12V OUTPUT SEPIC CONVERTER VOUT 5V/DIV IL1A + IL1B 2A/DIV 3957A G20 VIN = 12V 50μs/DIV VOUT 10V/DIV VSW 20V/DIV IL1A + IL1B 5A/DIV 3957A G21 VIN = 12V SEE TYPICAL APPLICATION: 5V TO 16V INPUT , 12V OUTPUT SEPIC CONVERTER

NC (Pins 1, 2, 10, 35, 36): No Internal Connection. Leave these pins open or connect them to the adjacent pins. SENSE2 (Pin 3): The Current Sense Input for the Control Loop. Connect this pin to SENSE1 pin directly or through a low pass filter (connect this pin to SENSE1 pin through a resistor, and to SGND through a capacitor). SGND (Pins 4, 23, 24, Exposed Pad Pin 37): Signal Ground. All small-signal components should connect to this ground. SGND is connected to GND inside the IC to ensure Kelvin connection for the internal switch current sensing. Do not connect SGND and GND externally. SENSE1 (Pin 6): The Current Sense Output of the Inter- nal N-channel MOSFET. Connect this pin to SENSE2 pin directly or through a lowpass filter (connect this pin to SENSE1 pin through a resistor, then connect SENSE2 to SGND through a capacitor). SW (Pins 8, 9, 20, 21, Exposed Pad Pin 38): Drain of Internal Power N-channel MOSFET. GND (Pins 12, 13, 14, 15, 16, 17): Ground. These pins connect to the source terminal of internal power N-channel MOSFET through an internal sense resistor. GND is con- nected to SGND inside the IC to ensure Kelvin connection for the internal switch current sensing. Do not connect GND and SGND externally. EN/UVLO (Pin 25): Shutdown and Undervoltage Detect Pin. An accurate 1.22V (nominal) falling threshold with externally programmable hysteresis detects when power is okay to enable switching. Rising hysteresis is generated by the external resistor divider and an accurate internal 2μA pull-down current. An undervoltage condition resets soft-start. Tie to 0.4V, or less, to disable the device and reduce V IN quiescent current below 1μA. VIN (Pin 27): Input Supply Pin. The VIN pin can be locally bypassed with a capacitor to GND (not SGND). INTVCC (Pin 28): Regulated Supply for Internal Loads and Gate Driver. Supplied from V IN and regulated to 5.2V (typical). INTVCC must be bypassed to SGND with a minimum of 4.7μF capacitor placed close to pin. INTVCC can be connected directly to V IN, if V IN is less than 8V. INTVCC can also be connected to a power supply whose voltage is higher than 5.5V, and lower than VIN, provided that supply does not exceed 8V. VC (Pin 30): Error Amplifier Compensation Pin. Used to stabilize the voltage loop with an external RC network. Place compensation components between the VC pin and SGND. FBX (Pin 31): Positive and Negative Feedback Pin. Re- ceives the feedback voltage from the external resistor divider between the output and SGND. Also modulates the switching frequency during start-up and fault conditions when FBX is close to SGND. SS (Pin 32): Soft-Start Pin. This pin modulates compen- sation pin voltage (V C) clamp. The soft-start interval is set with an external capacitor between SS pin and SGND. The pin has a 10μA (typical) pull-up current source to an internal 2.5V rail. The soft-start pin is reset to SGND by an undervoltage condition at EN/UVLO, an INTV CC undervolt- age or overvoltage condition or an internal thermal lockout. RT (Pin 33): Switching Frequency Adjustment Pin. Set the frequency using a resistor to SGND. Do not leave this pin open. SYNC (Pin 34): Frequency Synchronization Pin. Used to synchronize the switching frequency to an outside clock. If this feature is used, an R T resistor should be chosen to program a switching frequency 20% slower than the SYNC pulse frequency. Tie the SYNC pin to SGND if this feature is not used. SYNC is bypassed when FBX is close to SGND.

Figure 1. LT3957A Block Diagram Working as a SEPIC Converter

The LT3957A uses a fixed frequency, current mode con- trol scheme to provide excellent line and load regulation. Operation can be best understood by referring to the Block Diagram in Figure 1. The start of each oscillator cycle sets the SR latch (SR1) and turns on the internal power MOSFET switch M1 through driver G2. The switch current flows through the internal current sensing resistor R SENSE and generates a voltage proportional to the switch current. This current sense voltage V ISENSE (amplified by A5) is added to a stabilizing slope compensation ramp and the resulting sum (SLOPE) is fed into the positive terminal of the PWM comparator A7. When SLOPE exceeds the level at the negative input of A7 C pin), SR1 is reset, turning off the power switch. The level at the negative input of A7 is set by the error amplifier A1 (or A2) and is an amplified version of the difference between the feedback voltage (FBX pin) and the reference voltage (1.6V or –0.8V, depending on the configuration). In this manner, the error amplifier sets the correct peak switch current level to keep the output in regulation. The LT3957A has a switch current limit function. The cur- rent sense voltage is input to the current limit comparator A6. If the SENSE2 pin voltage is higher than the sense current limit threshold V SENSE(MAX) (48mV, typical), A6 will reset SR1 and turn off M1 immediately. The LT3957A is capable of generating either positive or negative output voltage with a single FBX pin. It can be configured as a boost, flyback or SEPIC converter to gen- erate positive output voltage, or as an inverting converter to generate negative output voltage. When configured as a SEPIC converter, as shown in Figure 1, the FBX pin is pulled up to the internal bias voltage of 1.6V by a volt- age divider (R1 and R2) connected from V OUT to SGND. Comparator A2 becomes inactive and comparator A1 performs the inverting amplification from FBX to V When the LT3957A is in an inverting configuration, the FBX pin is pulled down to –0.8V by a voltage divider connected from V OUT to SGND. Comparator A1 becomes inactive and comparator A2 performs the noninverting amplification from FBX to V The LT3957A has overvoltage protection functions to protect the converter from excessive output voltage overshoot during start-up or recovery from a short-circuit condition. An overvoltage comparator A11 (with 20mV hysteresis) senses when the FBX pin voltage exceeds the positive regulated voltage (1.6V) by 8% and provides a reset pulse. Similarly, an overvoltage comparator A12 (with 10mV hysteresis) senses when the FBX pin voltage exceeds the negative regulated voltage (–0.8V) by 11% and provides a reset pulse. Both reset pulses are sent to the main RS latch (SR1) through G6 and G5. The power MOSFET switch M1 is actively held off for the duration of an output overvoltage condition. Programming Turn-On and Turn-Off Thresholds with the EN/UVLO Pin The EN/UVLO pin controls whether the LT3957A is enabled or is in shutdown state. A micropower 1.22V reference, a comparator A10 and a controllable current source I allow the user to accurately program the supply voltage at which the IC turns on and off. The falling value can be accurately set by the resistor dividers R3 and R4. When EN/UVLO is above 0.4V, and below the 1.22V threshold, the small pull-down current source I S1 (typical 2μA) is active. The purpose of this current is to allow the user to program the rising hysteresis. The Block Diagram of the comparator and the external resistors is shown in Figure 1. The typical falling threshold voltage and rising threshold voltage can be calculated by the following equations: VVIN,FALLING = 1.22 • (R3+R4) VVIN,RISING = 2μA • R3+ VIN,FALLING For applications where the EN/UVLO pin is only used as a logic input, the EN/UVLO pin can be connected directly to the input voltage V IN for always-on operation. INTVCC Regulator Bypassing and Operation An internal, low dropout (LDO) voltage regulator produces the 5.2V INTV CC supply which powers the gate driver, as shown in Figure 1. The LT3957A contains an undervoltage lockout comparator A8 for the INTV CC supply. The INTVCC

be turned off and the soft-start operation will be triggered. enough to turn off the internal LDO regulator. (around 16μA) will load the INTVCC in shutdown mode. Figure 2. Connecting INTVCC to VOUT Table 1. Timing Resistor (RT) Value

The operating frequency of the LT3957A can be synchro- nized to an external clock source. By providing a digital clock signal into the SYNC pin, the LT3957A will operate at the SYNC clock frequency. The LT3957A detects the rising edge of each clock cycle. If this feature is used, an R T resistor should be chosen to program a switching frequency 20% slower than SYNC pulse frequency. It is recommended that the SYNC pin has a minimum pulse width of 200ns. Tie the SYNC pin to SGND if this feature is not used. Duty Cycle Consideration Switching duty cycle is a key variable defining converter operation. As such, its limits must be considered. Minimum on-time is the smallest time duration that the LT3957A is capable of turning on the power MOSFET. This time is typically about 240ns (see Minimum On-Time in the Electrical Characteristics table). In each switching cycle, the LT3957A keeps the power switch off for at least 220ns (typical) (see Minimum Off-Time in the Electrical Characteristics table). The minimum on-time, minimum off-time and the switching frequency define the minimum and maximum switching duty cycles a converter is able to generate: Minimum duty cycle = minimum on-time • frequency Maximum duty cycle = 1 – (minimum off-time • frequency) Programming the Output Voltage The output voltage V OUT is set by a resistor divider, as shown in Figure 1. The positive and negative VOUT are set by the following equations: VOUT,POSITIVE = 1.6V • 1 + R2 ⎝⎜ ⎞ VOUT,NEGATIVE = –0.8V • 1 + R2 ⎝⎜ ⎞ The resistors R1 and R2 are typically chosen so that the error caused by the current flowing into the FBX pin during normal operation is less than 1% (this translates to a maximum value of R1 at about 158k). Soft-Start The LT3957A contains several features to limit peak switch currents and output voltage (V OUT) overshoot during start-up or recovery from a fault condition. The primary purpose of these features is to prevent damage to external components or the load. High peak switch currents during start-up may occur in switching regulators. Since V OUT is far from its final value, the feedback loop is saturated and the regulator tries to charge the output capacitor as quickly as possible, resulting in large peak currents. A large surge current may cause inductor saturation or power switch failure. The LT3957A addresses this mechanism with the SS pin. As shown in Figure 1, the SS pin reduces the power MOSFET current by pulling down the V C pin through Q2. In this way the SS allows the output capacitor to charge gradually toward its final value while limiting the start-up peak currents. The typical start-up waveforms are shown in the Typical Performance Characteristics section. The inductor current I L slewing rate is limited by the soft-start function. Besides start-up (with EN/UVLO), soft-start can also be triggered by the following faults: 1. INTV CC < 2.85V 2. Thermal lockout (TLO > 165°C) Any of these three faults will cause the LT3957A to stop switching immediately. The SS pin will be discharged by Q3. When all faults are cleared and the SS pin has been discharged below 0.2V, a 10μA current source I S2 starts charging the SS pin, initiating a soft-start operation. The soft-start interval is set by the soft-start capacitor selection according to the equation: TSS = CSS • 1.25V 10μA FBX Frequency Foldback When VOUT is very low during start-up, or an output short- circuit on a SEPIC, an inverting, or a flyback converter, the switching regulator must operate at low duty cycles to keep the power switch current below the current limit, since

graph in the Typical Performance Characteristics section). regulate the output which simplifies loop compensation. Note 76 is a good reference on loop compensation. (10% or higher is recommended). SENSE immediately after M1 is turned on. Figure 3. The Switch Current During a Switching Cycle

Figure 4. The RC Filter on SENSE1 Pin and SENSE2 Pin tics section. VSW(PEAK) is the peak switch off-state voltage. J(MAX) does not exceed 125°C. protective actions. The power switch will be turned off. in continuous conduction mode (CCM). efficiencies and higher switching currents.

5 A − 0.5 •ΔISW() The inductor ripple current ΔISW has a direct effect on the choice of the inductor value and the converter’s maximum output current capability. Choosing smaller values of APPLICATION CIRCUITS The LT3957A can be configured as different topologies. The first topology to be analyzed will be the boost converter, followed by the flyback, SEPIC and inverting converters. Boost Converter: Switch Duty Cycle and Frequency The LT3957A can be configured as a boost converter for the applications where the converter output voltage

having sufficient saturation and RMS current ratings. ringing across its anode-to-cathode during the on-time. safety margin is usually sufficient). not exceed the diode maximum junction temperature rating. Figure 5. The Output Ripple Waveform of a Boost Converter

continuous and the discontinuous operation) should be.

Lower MOSFET RMS current I SW(RMS), but higher MOSFET VSW peak voltage
Lower diode peak reverse voltage, but higher diode RMS current ID(RMS)
Higher transformer turns ratio (N P/NS) It is recommended to choose a duty cycle between 20% and 80%. Flyback Converter: Maximum Output Current Capability and T ransformer Design The maximum output current capability and transformer design for continuous conduction mode (CCM) is chosen as presented here. The maximum duty cycle (D MAX) occurs when the converter has the minimum VIN: DMAX = VOUT • NP NS VOUT • NP NS ⎠⎟+ VIN(MIN) Due to the current limit of its internal power switch, the LT3957A should be used in a flyback converter whose maximum output current (I O(MAX)) is less than the maximum output current capability by a sufficient margin (10% or higher is recommended): IO(MAX) < VIN(MIN) VOUT
DMAX •5 A − 0.5 •ΔISW() The transformer ripple current ΔISW has a direct effect on the design/choice of the transformer and the converter’s output current capability. Choosing smaller values of ΔI SW increases the output current capability, but requires large primary and secondary inductances and reduce the current loop gain (the converter will approach voltage mode). Accepting larger values of ΔI SW allows the use of low primary and secondary inductances, but results in higher input current ripple, greater core losses, and reduces the output current capability. Given an operating input voltage range, and having chosen the operating frequency and ripple current in the primary winding, the primary winding inductance can be calculated using the following equation: L = VIN(MIN) ΔISW •ƒ •DMAX

Figure 7. Waveforms of the Flyback Converter

The primary winding peak current is the switch current limit (typical 5.9A). The primary and secondary maximum RMS currents are: ILP(RMS) ≈ POUT(MAX) DMAX •VIN(MIN) • η ILS(RMS) ≈ IOUT(MAX) 1−DMAX where η is the converter efficiency. Based on the preceding equations, the user should design/ choose the transformer having sufficient saturation and RMS current ratings. Flyback Converter: Snubber Design T ransformer leakage inductance (on either the primary or secondary) causes a voltage spike to occur after the MOSFET turn-off. This is increasingly prominent at higher load currents, where more stored energy must be dissi- pated. In some cases a snubber circuit will be required to avoid overvoltage breakdown at the MOSFET’s drain node. There are different snubber circuits (such as RC snubber, RCD snubber, Zener clamp, etc.), and Application Note 19 is a good reference on snubber design. An RC snubber circuit can be connected between SW and GND to damp the ringing on SW pins. The snubber resistor values should be close to the impedance of the parasitic resonance. The snubber capacitor value should be larger than the circuit parasitic capacitance, but be small enough to keep the snubber resistor power dissipation low. If the RC snubber is insufficient to prevent SW pins over- voltage, the RCD snubber can be used to limit the peak voltage on the SW pins, which is shown in Figure 6. The snubber resistor value (R SN) can be calculated by the following equation: RSN = 2• V2SN − VSN •V OUT • NP NS I2SW(PEAK) •L LK •ƒ LLK is the leakage inductance of the primary winding, which is usually specified in the transformer characteristics. LLK can be obtained by measuring the primary inductance with the secondary windings shorted. The snubber capacitor value (C SN) can be determined using the following equation: CCN = VSN ΔVSN •RSN •ƒ where ΔVSN is the voltage ripple across CSN. A reasonable ΔVSN is 5% to 10% of VSN. The reverse voltage rating of DSN should be higher than the sum of VSN and VIN(MAX). A Zener clamp can also be connected between SW and GND to ensure SW voltage does not exceed 40V. Flyback Converter: Output Diode Selection The output diode in a flyback converter is subject to large RMS current and peak reverse voltage stresses. A fast switching diode with a low forward drop and a low reverse leakage is desired. Schottky diodes are recommended if the output voltage is below 100V. Approximate the required peak repetitive reverse voltage rating V RRM using: VRRM > NS NP

VIN(MAX) + VOUT The power dissipated by the diode is: P D = IO(MAX) • VD and the diode junction temperature is: T J = TA + PD • RθJA The RθJA to be used in this equation normally includes the RθJC for the device, plus the thermal resistance from the board to the ambient temperature in the enclosure. TJ must not exceed the diode maximum junction temperature rating. Flyback Converter: Output Capacitor Selection The output capacitor of the flyback converter has a similar operation condition as that of the boost converter. Refer to the Boost Converter: Output Capacitor Selection section for the calculation of C OUT and ESRCOUT.

The RMS ripple current rating of the output capacitors in continuous operation can be determined using the following equation: IRMS(COUT),CONTINUOUS ≈ IO(MAX) • DMAX 1−DMAX Flyback Converter: Input Capacitor Selection The input capacitor in a flyback converter is subject to a large RMS current due to the discontinuous primary current. To prevent large voltage transients, use a low ESR input capacitor sized for the maximum RMS current. The RMS ripple current rating of the input capacitors in continuous operation can be determined using the following equation: IRMS(CIN),CONTINUOUS ≈ POUT(MAX) VIN(MIN) • η • 1−DMAX DMAX SEPIC CONVERTER APPLICATIONS The LT3957A can be configured as a SEPIC (single-ended primary inductance converter), as shown in Figure 1. This topology allows for the input to be higher, equal, or lower than the desired output voltage. The conversion ratio as a function of duty cycle is: VOUT + VD VIN = D 1−D in continuous conduction mode (CCM). In a SEPIC converter, no DC path exists between the input and output. This is an advantage over the boost converter for applications requiring the output to be disconnected from the input source when the circuit is in shutdown. Compared to the flyback converter, the SEPIC converter has the advantage that both the power MOSFET and the output diode voltages are clamped by the capacitors (C IN, CDC and C OUT), therefore, there is less voltage ringing across the power MOSFET and the output diodes. The SEPIC converter requires much smaller input capacitors than those of the flyback converter. This is due to the fact that, in the SEPIC converter, the current through inductor L1 (which is series with the input) is continuous. SEPIC Converter: Switch Duty Cycle and Frequency For a SEPIC converter operating in CCM, the duty cycle of the main switch can be calculated based on the output voltage (V OUT), the input voltage (V IN) and the diode forward voltage (VD). The maximum duty cycle (DMAX) occurs when the converter has the minimum input voltage: DMAX = VOUT + VD VIN(MIN) + VOUT + VD SEPIC Converter: The Maximum Output Current Capability and Inductor Selection As shown in Figure 1, the SEPIC converter contains two inductors: L1 and L2. L1 and L2 can be independent, but can also be wound on the same core, since identical voltages are applied to L1 and L2 throughout the switching cycle. For the SEPIC topology, the current through L1 is the converter input current. Based on the fact that, ideally, the output power is equal to the input power, the maximum average inductor currents of L1 and L2 are: IL1 (MAX)=IIN(MAX) =IO(MAX) • DMAX 1−DMAX IL2(MAX) =IO(MAX) Due to the current limit of its internal power switch, the LT3957A should be used in a SEPIC converter whose maximum output current (I O(MAX)) is less than the output current capability by a sufficient margin (10% or higher is recommended): IO(MAX) < 1−DMAX() •5 A − 0.5 •ΔISW() The inductor ripple currents ΔIL1 and ΔIL2 are identical: ΔIL1 = ΔIL2 = 0.5 • ΔISW The inductor ripple current ΔISW has a direct effect on the choice of the inductor value and the converter’s maximum output current capability. Choosing smaller values of ΔISW requires large inductances and reduces the current loop gain (the converter will approach voltage mode). Accepting larger values of ΔI SW allows the use of low inductances,

but results in higher input current ripple and greater core losses and reduces output current capability. Given an operating input voltage range, and having chosen the operating frequency and ripple current in the inductor, the inductor value (L1 and L2 are independent) of the SEPIC converter can be determined using the following equation: L1 = L2 = VIN(MIN) 0.5 •ΔISW •ƒ •DMAX For most SEPIC applications, the equal inductor values will fall in the range of 1μH to 100μH. By making L1 = L2, and winding them on the same core, the value of inductance in the preceding equation is replaced by 2L, due to mutual inductance: L = VIN(MIN) ΔISW •ƒ •DMAX This maintains the same ripple current and energy storage in the inductors. The peak inductor currents are: I L1(PEAK) = IL1(MAX) + 0.5 • ΔIL1 I L2(PEAK) = IL2(MAX) + 0.5 • ΔIL2 The maximum RMS inductor currents are approximately equal to the maximum average inductor currents. Based on the preceding equations, the user should choose the inductors having sufficient saturation and RMS cur- rent ratings. SEPIC Converter: Output Diode Selection To maximize efficiency, a fast switching diode with a low forward drop and low reverse leakage is desirable. The average forward current in normal operation is equal to the output current. It is recommended that the peak repetitive reverse voltage rating V RRM is higher than V OUT + V IN(MAX) by a safety margin (a 10V safety margin is usually sufficient). The power dissipated by the diode is: P D = IO(MAX) • VD where VD is diode’s forward voltage drop, and the diode junction temperature is: T J = TA + PD • RθJA The RθJA used in this equation normally includes the RθJC for the device, plus the thermal resistance from the board, to the ambient temperature in the enclosure. TJ must not exceed the diode maximum junction temperature rating. SEPIC Converter: Output and Input Capacitor Selection The selections of the output and input capacitors of the SEPIC converter are similar to those of the boost converter. Please refer to the Boost Converter: Output Capacitor Selection and Boost Converter: Input Capacitor Selection sections. SEPIC Converter: Selecting the DC Coupling Capacitor The DC voltage rating of the DC coupling capacitor (C DC, as shown in Figure 1) should be larger than the maximum input voltage: V CDC > VIN(MAX) CDC has nearly a rectangular current waveform. During the switch off-time, the current through CDC is IIN, while approximately –I O flows during the on-time. The RMS rating of the coupling capacitor is determined by the fol- lowing equation: IRMS(CDC) >IO(MAX) • VOUT + VD VIN(MIN) A low ESR and ESL, X5R or X7R ceramic capacitor works well for CDC. INVERTING CONVERTER APPLICATIONS The LT3957A can be configured as a dual-inductor inverting topology, as shown in Figure 8. The VOUT to VIN ratio is: VOUT − VD VIN =− D 1−D in continuous conduction mode (CCM).

Figure 8. A Simplified Inverting Converter OUT) and the input voltage (VIN).

Table 2. Recommended Component Manufacturers General Semiconductor Diodes generalsemiconductor.

4.5V to 16V Input, 24V Output Boost Converter Efficiency vs Output Current SENSE2 SENSE1 LT3957A 10μH VIN SW GND FBX RT SS INTVCC EN/UVLO SYNC SGND 95.3k VC 3957A TA02a 200k RT 41.2k 300kHz CVCC 4.7μF 10V X5R CSS 0.33μF RC 6.8k CC 22nF 226k 15.8k COUT 10μF 50V X5R V OUT 24V 600mA V IN 4.5V TO 16V CIN 10μF 25V X5R CIN: MURATA GRM31ER61H106KA12 COUT: TAIYO YUDEN UMK325BJ106MM D1: VISHAY SILICONIX 10BQ040 L1: VISHAY SILICONIX IHLP-5050CE-1 OUTPUT CURRENT (mA) EFFICIENCY (%) 100 100 200 300 400 500 3957A TA02b 600 VIN = 12V

5V to 16V Input, 12V Output SEPIC Converter Efficiency vs Output Current Load Step Waveforms Start-Up Waveforms Frequency Foldback Waveforms When Output Short-Circuit SENSE2 SENSE1 LT3957A L1A L1BVIN SW GND FBX RT SS INTVCC EN/UVLO SYNC SGND 82.5k VC 3957A TA03a 200k 41.2k 300kHz CVCC 4.7μF 10V X5R 0.47μF 10k 10nF 105k 15.8k CDC 4.7μF, 25V X5R VOUT 12V V IN 5V TO 16V CIN 4.7μF 25V X5R C OUT 22μF 16V X5R t t CIN, CDC: MURATA GRM21BR61E475KA12L COUT: MURATA GRM32ER61C226KE20 D1: VISHAY SILICONIX 30BQ040 L1A, L1B: COILTRONICS DRQ127-100 OUTPUT CURRENT (mA) EFFICIENCY (%) 100 200 400 600 800 3957A TA03b 1000 VIN = 12V 5ms/DIV VOUT 5V/DIV IL1A + IL1B 2A/DIV 3957A TA03d VIN = 12V 50μs/DIV VOUT 10V/DIV VSW 20V/DIV IL1A + IL1B 5A/DIV 3957A TA03e VIN = 12V 2ms/DIV VOUT 1V/DIV (AC) IOUT 0.5A/DIV

3957 TA03c

VIN = 12V

5V to 16V Input, –12V Output Inverting Converter Efficiency vs Output Current Load Step Waveforms Start-Up Waveforms Frequency Foldback Waveforms When Output Short-Circuit SENSE2 SENSE1 LT3957A L1A L1B VIN SW GND FBX RT SS INTVCC EN/UVLO SYNC SGND 82.5k VC 395A7 TA04a D1200k 41.2k 300kHz CVCC 4.7μF 10V X5R 0.47μF 10k 10nF 105k 7.5k CDC 4.7μF, 50V X7R VOUT –12V V IN 5V TO 16V CIN 4.7μF 25V X5R C OUT 22μF 16V X5R t t CIN: MURATA GRM21BR61E475KA12L CDC: TAIYO YUDEN UMK316BJ475KL COUT: MURATA GRM32ER61C226KE20 D1: VISHAY SILICONIX 30BQ040 L1A, L1B: COILTRONICS DRQ127-100 OUTPUT CURRENT (mA) EFFICIENCY (%) 100 200 400 600 800 3957A TA04b 1000 VIN = 12V 5ms/DIV VOUT 5V/DIV IL1A + IL1B 2A/DIV 3957A TA04d VIN = 12V 50μs/DIV VOUT 10V/DIV VSW 20V/DIV IL1A + IL1B 5A/DIV 3957A TA04e VIN = 12V 2ms/DIV VOUT 1V/DIV (AC) IOUT 0.2A/DIV 0.6A 3957A TA04c VIN = 12V

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. 5.00 t 0.10 6.00 t 0.10 NOTE: 1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE PIN 1 TOP MARK (NOTE 6) 0.40 t 0.10 36 3530 31 32 33 34 27 2 12 13 14 15 16 17 BOTTOM VIEW—EXPOSED PAD

2.00 REF

1.50 REF

0.75 t 0.05 R = 0.125 TYP R = 0.10 TYP PIN 1 NOTCH R = 0.30 OR 0.35 w 45s CHAMFER 0.25 t 0.05

0.50 BSC

0.200 REF

0.00 – 0.05 (UHE36(28)MA) QFN 0112 REV D RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 0.70 t0.05 4.10 t 0.05 5.50 t 0.05 PACKAGE OUTLINE 1.88 t 0.10 1.53 t 0.10 5.10 t 0.05 6.50 t 0.05 Variation: UHE36(28)MA 36(28)-Lead Plastic QFN (5mm w 6mm) (Reference LTC DWG # 05-08-1836 Rev D) 3.00 t 0.10 3.00 t 0.10 0.12 t 0.10 1.88 t 0.05 1.53 t 0.05 3.00 t 0.05 3.00 t 0.05 0.48 t 0.05 0.12 t 0.05 0.48 t 0.10 0.25 t0.05

Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

REVISION HISTORY

REV DATE DESCRIPTION PAGE NUMBER A 10/12 V C Low Side Clamp Voltage line item added 3

Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear .com © LINEAR TECHNOLOGY CORPORATION 2012 LT 1012 REV A • PRINTED IN USA TYPICAL APPLICATIONS PART NUMBER DESCRIPTION COMMENTS LT3957 Boost, Flyback, SEPIC and Inverting Converter with 5A/40V Switch 3V ≤ VIN ≤ 40V, Current Mode Control, 100kHz to 1MHz Programmable Operation Frequency, 5mm × 6mm QFN-36 Package LT3958 High Input Voltage, Boost, Flyback, SEPIC and Inverting Converter with 3.5A/80V Switch 5V ≤ VIN < 80V, Current Mode Control, 100kHz to 1MHz Programmable Operation Frequency, 5mm × 6mm QFN-36 Package LT3757 Boost, Flyback, SEPIC and Inverting Controller 2.9V ≤ V IN ≤ 40V, Current Mode Control, 100kHz to 1MHz Programmable Operation Frequency, 3mm × 3mm DFN-10 and MSOP-10E Package LT3758 Boost, Flyback, SEPIC and Inverting Controller 5.5V ≤ V IN ≤ 100V, Current Mode Control, 100kHz to 1MHz Programmable Operation Frequency, 3mm × 3mm DFN-10 and MSOP-10E Package LT3759 Boost, SEPIC and Inverting Controller 1.6V ≤ V IN ≤ 42V, Current Mode Control, 100kHz to 1MHz Programmable Operation Frequency, MSOP-12E Package RELATED PARTS 4V to 6V Input, 180V Output Flyback Converter SENSE2 FBX SENSE1LT3957A 1:10 VIN SW GND RT SS INTVCC EN/UVLO SYNC SGND 37.4k VC 3957A TA05 DANGER! HIGH VOLTAGE! 75k 22Ω 220pF 140k 100kHz 4.7μF 10V X5R 10nF 0.1μF 10k 10nF 100pF 22Ω 15.8k 1.80M COUT 68nF V OUT 180V 15mA V IN 4V TO 6V CIN 100μF 6.3V T1: TDK DCT15EFD-U44S003 C IN: GRM31CR60J107ME39L COUT: GRM43QR72J683KW01L D1: VISHAY SILICONIX GSD2004S DUAL DIODE CONNECTED IN SERIES D2: DIODES MMSZ5258B t t

Summary

Boost, Flyback, SEPIC and Inverting Converter with 5A, 40V Switch

Description