LT3952

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For more information www.linear.com/LT3952 TYPICAL APPLICATION FEATURES DESCRIPTION 60V LED Driver with 4A Switch Current The LT®3952 is a current mode step-up DC/DC converter with an internal, 60V, 80m/uni03A9 DMOS power switch. The LT3952 is specifically designed to drive high power LEDs in multiple configurations. It combines input and output current regulation loops with output voltage regulation to operate as a flexible current/voltage source. Programmable switching frequency with optional spread- spectrum modulation provides EMI reduction, while still allowing optimization of the external components for efficiency or component size. The LED current is program- mable with an external sense resistor , and can be adjusted from zero to full scale with a voltage at the CTRL pin. The external PWM input provides LED ON/OFF control and 4000:1 dimming ratio, and an internal PWM generator delivers the efficiency of PWM dimming to standalone or I/O limited applications. The LT3952 is available in the thermally enhanced 28-lead TSSOP package.

APPLICATIONS

n4000:1 T rue Color PWM™ Dimming n4A, 60V Internal DMOS Switch nWide Input Voltage Range: 3V to 42V n0V to 60V Output Current Regulation with Monitor nPMOS Switch Driver for PWM and Output Disconnect nLED Short-Circuit Protection and SHORTLED Flag nInternal Spread Spectrum Frequency Modulation nConstant-Current and Constant-Voltage Regulation nInput Current Limit and Monitor nAdjustable Frequency: 200kHz to 3MHz, Synchronizable to an External Clock n10:1 Analog Dimming nProgrammable Open-LED Protection with OPENLED Flag nProgrammable VIN Undervoltage and Overvoltage Lockout nAvailable in a 28-Lead TSSOP Package nDisplay Backlighting nAutomotive and Avionic Lighting nAccurate Current-Limited Voltage Regulators L, L T , L TC, L TM, Linear Technology and the Linear logo are registered trademarks and T rue Color PWM is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents including, 7199560, 7321203, 7746300. Patents pending IVINP L T3952 VIN VC SHORTLED OPENLED SHORTLED OPENLED SYNC/SPRD INTVCC TG ISN ISP FB GND INTVCC 750m/uni03A9 EN/UVLO OVLO CTRL VREF PWM ISMON DIM IVINCOMP RT SS 2.2µF

3952 TA01a

2.2µF 100V 1µF8.2nF 90.9k 1MHz 21.5k 100k100k INTVCC PWM ISMON 3.6k IVINN 4A INPUT LIMIT 15m/uni03A9 10µH SW 4.7µF VIN 7V TO 42V

16 LED (50V)

Short-Circuit Robust Boost LED Driver with Spread Spectrum Frequency Modulation VIN (V) EFFICIENCY (%)

3952 TA01b

Efficiency vs Input Voltage

For more information www.linear.com/LT3952 PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS VIN, IVINP , IVINN, SHORTLED, OPENLED, Operating Junction Temperature Range (Notes 2, 3) (Note 1) TOP VIEW FE PACKAGE 28-LEAD PLASTIC TSSOP GND SW SW SW IVINN IVINP V IN EN/UVLO OVLO INTVCC SYNC/SPRD GND VC RT GND ISP ISN TG ISMON IVINCOMP OPENLED SHORTLED PWM SS V REF CTRL FB DIM GND θJA = 30°C/W EXPOSED PAD (PIN 29) IS GND, MUST BE SOLDERED TO PCB ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LT3952EFE#PBF LT3952EFE#TRPBF LT3952FE 28-Lead Plastic TSSOP –40°C to 125°C LT3952IFE#PBF LT3952IFE#TRPBF LT3952FE 28-Lead Plastic TSSOP –40°C to 125°C LT3952HFE#PBF LT3952HFE#TRPBF LT3952FE 28-Lead Plastic TSSOP –40°C to 150°C Consult L TC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container . For more information on lead free part marking, go to: http://www.linear .com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear .com/tapeandreel/. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix

For more information www.linear.com/LT3952

ELECTRICAL CHARACTERISTICS

The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = IVINP = IVINN = 12V, ISP = ISN = 24V, EN/UVLO = PWM = 3V, CTRL = 2V, OVLO = 0V unless otherwise noted PARAMETER CONDITIONS MIN TYP MAX UNITS Minimum Operating Voltage 3 V Supply Current FB = 1.3V, RT = 40.2k, CTRL = 0V EN/UVLO = 0V, CTRL = 0V EN/UVLO = 1.15V, CTRL = 0V 1.5 2.2 mA µA µA Internal Regulator INTV CC Output Voltage CTRL = 0V 2.90 3.00 3.10 V INTVCC Dropout Voltage VIN = 3V, CTRL = 0V 150 mV INTVCC Undervoltage Lockout INTVCC Rising, CTRL = 0V 2.62 2.68 2.74 V INTVCC UVLO Hysteresis CTRL = 0V 200 mV Reference Voltage Output V REF Voltage IVREF = –100/uni03BCA , CTRL = 0V l 1.955 2.000 2.045 V VREF Line Regulation 3V < VIN < 42V , CTRL = 0V 0.01 %/V VREF Load Regulation 0µA < IVREF < –100µA , CTRL = 0V 0.6 % Current Feedback CTRL Range for Current Sense Threshold Adjustment 0.2 1.2 V CTRL PWM Shutdown Threshold CTRL Falling 100 125 mV CTRL PWM Threshold Hysteresis 12.5 mV CTRL Zero-Scale Offset 200 mV CTRL Input Bias Current CTRL = 0V, Current Out of Pin 20 100 nA Current Sense Common Mode Input Range CTRL = 1.5V 0 60 V Full-Scale Current Sense Accuracy (V ISP-VISN) ISP = 60V, CTRL = 1.5V l 245 250 255 mV Midrange Current Sense Accuracy (VISP-VISN) ISP = 60V, CTRL = 0.7V 115 125 135 mV 1/10th Scale Current Sense Accuracy (VISP-VISN) ISP = 60V, CTRL = 0.3V 10 25 40 mV Low Side Current Sense Accuracy (VISP-VISN) ISP = 0V, CTRL = 1.5V l 240 250 260 mV Overcurrent Sense Threshold l 350 375 390 mV ISP to VC T ransconductance CTRL = 1.5V 275 µS ISP/ISN Input Bias Current PWM = 5V (Active), ISP = 60V PWM = 0V (Standby), ISP = 60V 250 0.1 µA µA Current Sense Monitor Ratio (V ISMON)/(VISP-VISN) CTRL = 0.4V, 0.8V 4 V/V Current Sense Monitor Accuracy (VISMON) CTRL = 1.5V , ISP = 60V 0.950 1.000 1.050 V Input Current Sense Amplifier Amplifier Supply Current (From IVINP) IVINP = IVINN = 42V 35 60 µA IVIN Regulation Threshold (VIVINP-IVINN) l 55 60 65 mV IVINCOMP to VC T ransconductance 1650 µS Input Common Mode Minimum Voltage 3 V IVINP/IVINN to Monitor Voltage Gain VIVINP-IVINN = 30mV 20 V/V

For more information www.linear.com/LT3952 The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = IVINP = IVINN = 12V, ISP = ISN = 24V, EN/UVLO = PWM = 3V, CTRL = 2V, OVLO = 0V unless otherwise noted PARAMETER CONDITIONS MIN TYP MAX UNITS TG Gate Driver PWM Input High Threshold PWM Rising l 1.15 1.2 1.25 V PWM Hysteresis 20 mV TG On Voltage VISP-TG, VISP > 10V 7.5 9.5 V TG Off Voltage VISP-TG, PWM = 0V 0 0.3 V TG Turn-On Time CLOAD = 470pF, PWM Rising 100 ns TG Turn-Off Time CLOAD = 470pF, PWM Falling 150 ns Output Voltage Feedback FB Voltage Regulation Threshold (V FB) CTRL = 1.5V l 1.188 1.182 1.200 1.200 1.212 1.218 V V FB Open-LED Threshold FB Rising V FB – 65mV VFB – 45mV VFB – 25mV V FB Open-LED Threshold Hysteresis 15 mV FB Overvoltage Threshold FB Rising VFB + 15mV VFB + 30mV VFB + 40mV V FB Overvoltage Threshold Hysteresis 15 mV FB Pin Bias Current l 20 100 nA Feedback Line Regulation 3V < VIN < 42V 0.0003 %/V FB to VC T ransconductance 450 µS VC Output Impedance 5000 k/uni03A9 Soft-Start Soft-Start Sourcing Current Current Out of Pin, SS = 0.1V 18 25 37 µA Soft-Start Sinking Current SS = 1.8V 1.5 2.5 4.1 µA Soft-Start Hiccup Retry Threshold 200 mV Soft-Start Strong Pull-Down On-Resistance 120 /uni03A9 Oscillator RT Voltage 1.20 V Switching Frequency R T = 470k RT = 90.9k RT = 40.2k RT = 25.5k l 180 0.95 1.90 2.75 215 1.0 2.0 3.0 250 1.05 2.10 3.25 kHz MHz MHz MHz Maximum Duty Cycle R T = 470k SYNC = 300kHz Clock Signal, RT = 470k RT = 90.9k RT = 40.2k RT = 25.5k l Minimum Off-Time 50 ns Minimum On-Time 75 ns SYNC/SPRD Pin Resistance to GND V SYNC = 2V 100 k/uni03A9 SYNC/SPRD Input High Threshold 1.5 V SYNC/SPRD Input Low Threshold 0.4 V Spread Spectrum Minimum Step as Percentage of fSW 1 % Spread Spectrum Maximum Step as Percentage of fSW 31 %

For more information www.linear.com/LT3952 The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = IVINP = IVINN = 12V, ISP = ISN = 24V, EN/UVLO = PWM = 3V, CTRL = 2V, OVLO = 0V unless otherwise noted PARAMETER CONDITIONS MIN TYP MAX UNITS PWM Generator PWM Pin Pull-Up/Pull-Down Current PWM = 1.2V, DIM = 0.7V l 5 10 15 µA PWM Generator Lower Threshold Offset 0.2V < DIM < 1.2V VDIM – 15 V DIM + 0 V DIM + 15 mV PWM Generator Upper Threshold Offset 0.2V < DIM < 1.2V VDIM + 825 VDIM + 950 VDIM + 1075 mV PWM Generator Frequency DIM = 0.7V, CPWM = 22nF 230 Hz DIM Pin Output Current DIM = 0.7V l 10 20 30 µA TG Duty Cycle Using PWM Generator DIM = 0.345V DIM = 0.535V DIM = 0.725V DIM = 1.105V 42.5 57.5 Power Switch Switch On-Resistance I SW = 500mA 80 m/uni03A9 Switch Leakage Current SW = 60V, CTRL = 0V 2 µA VC to Current Threshold T ransconductance 7.5 S Maximum Power Switch Current Limit VC = 2V 4 4.5 5 A Logic Inputs/Outputs EN/UVLO Disable Threshold EN/UVLO Falling l 1.191 1.230 1.269 V EN/UVLO Threshold Internal Hysteresis 75 mV EN/UVLO Hysteresis Current EN/UVLO = 1.25V, Device in Shutdown EN/UVLO = 1.5V, Device in Operation 0.4 µA µA OVLO Threshold OVLO Rising l 1.191 1.230 1.269 V OVLO Threshold Hysteresis 25 mV OVLO Input Bias Current OVLO = 1V 15 100 nA SHORTLED On-Resistance ISHORTLED = 1mA 60 /uni03A9 SHORTLED Output Low Voltage ISHORTLED = 2mA 0.3 V SHORTLED Off-State Leakage SHORTLED = 42V 1 µA OPENLED On-Resistance IOPENLED = 1mA 60 /uni03A9 OPENLED Output Low Voltage IOPENLED = 2mA 0.3 V OPENLED Off-State Leakage OPENLED = 42V 1 µA Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LT3952E is guaranteed to meet specified performance from 0°C to 125°C. Specifications over the –40°C to 125°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LT3952I is guaranteed to meet performance specifications over the –40°C to 125°C operating junction temperature range. The LT3952H is guaranteed to meet performance specifications over the full –40°C to 150°C operating junction temperature range. High junction temperatures degrade operating lifetimes. Operating lifetime is derated at junction temperatures greater than 125°C. Note 3: The LT3952 includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed the maximum operating junction temperature when overtemperature is active. Continuous operating above the specified maximum operating junction temperature may impair device reliability. Note 4: INTV CC is an output and is not meant to be externally driven.

For more information www.linear.com/LT3952 TYPICAL PERFORMANCE CHARACTERISTICS INTVCC Voltage vs Temperature INTVCC Dropout vs Load and Temperature Shutdown Current vs Temperature EN/UVLO Bias Current above Threshold INTVCC vs Input Voltage INTVCC vs Input Voltage, Dropout Quiescent Current vs Input Voltage EN/UVLO Thresholds vs Temperature EN/UVLO Hysteresis Current vs Temperature TEMPERATURE (°C) –50 SUPPLY CURRENT (µA) VEN = 1.15V 0 50 100 150

3952 G01

TEMPERATURE (°C) –50

1.10 THRESHOLD (V)

1.15 1.20 1.25 1.30 1.35 1.40 EN/UVLO RISING EN/UVLO FALLING 0 50 100 150

3952 G02

TEMPERATURE (°C) –50 CURRENT (µA) 1.75 2.00 150

3952 G03

1.50 1.25 0 50 100 2.25 VEN = 1.25V EN/UVLO VOL TAGE (V) EN/UVLO CURRENT (µA) 1.00 –0.80 0.80 0.40 0.00 –0.40 0.60 0.20 –0.20 –0.60 –1.00

3925 G04

VIN (V) QUIESCENT CURRENT (mA) 1.25 1.5

3952 G05

0.75 0.5 10 20 30 0.25 1.75 TEMPERATURE (°C) –50

2.90 INTVCC (V)

2.95 3.00 3.05 0 50

3952 G06

VIN (V) INTVCC (V) 2.75 3.00 3.25

3952 G07

2.50 2.00 10 20 30 2.25 3.50 VIN (V) 1.5

2.00 INTVCC (V)

2.25 2.50 2.75 3.00 3.25 3.50 2 2.5 3 3.5

3952 G08

INTVCC (V) VIN (V) LOAD (mA) INTVCC DROPOUT (V) 0.3 0.4 0.5

3952 G09

0.2 0.1 3 6 9 15 VIN = 2.9V 150°C 25°C –50°C

For more information www.linear.com/LT3952 TYPICAL PERFORMANCE CHARACTERISTICS FB Thresholds vs Temperature Switching Frequency vs TemperatureSwitching Frequency vs RT SW Current Limit vs Temperature ISP/ISN Full-Scale Threshold vs Temperature ISP/ISN Mid-Scale Threshold (CTRL = 0.7V) vs Temperature INTV CC Current Limit vs Temperature VREF Voltage vs Temperature Reference Voltage vs Input Voltage TEMPERATURE (°C) –50 INTVCC CURRENT LIMIT (mA) NORMAL: INTVCC = 2.5V FOLDBACK: INTVCC = 0V 0 50 100 150

3952 G10

TEMPERATURE (°C) –50 VREF (V)2.000 2.025 150

3952 G11

1.975 1.950 0 50 100 2.050 IREF = 100µA VIN (V) VREF (V) 2.00 2.02 2.04

3952 G12

1.98 1.96 1.92 10 20 30 1.94 2.08 2.06 TEMPERATURE (°C) –50

1.12 FB THRESHOLDS (V)

1.14 1.16 1.18 1.20 1.22 1.24 0 50 100 150

3952 G13

RT (k/uni03A9) 0.1 SWITCHING FREQUENCY (MHz) 100 1000

3952 G14

TEMPERATURE (°C) –50 SWITCHING FREQUENCY (MHz) 1.000 1.025 150

3952 G15

0.975 0.950 0 50 100 1.050 RT = 90.9k TEMPERATURE (°C) –50 SW CURRENT LIMIT (A) 4.4 4.6 150

3952 G16

4.2 4.0 0 50 100 5.0 4.8 TEMPERATURE (°C) –55 ISP-ISN (mV) 250 251 252 150

3952 G17

254 CTRL = 2V

VISP = 60V253 TEMPERATURE (°C) –50

122 ISP-ISN (mV)

3952 G18

For more information www.linear.com/LT3952 TYPICAL PERFORMANCE CHARACTERISTICS VISP-ISN Threshold vs FB Voltage VISP-ISN Threshold vs CTRL ISP-ISN Threshold vs Output Voltage TG Rise/Fall Time vs Capacitance TG Driver Turn-On TG Driver Turn-Off ISP/ISN 1/10th Scale Threshold (CTRL = 0.3V) vs Temperature ISP/ISN Overcurrent Threshold vs Temperature ISMON Voltage vs ISP-ISN Voltage TEMPERATURE (°C) –50 ISP-ISN (mV) 0 50 100 150

3952 G19

TEMPERATURE (°C) –50 ISP/ISN OVERCURRENT THRESHOLD (mV) 375 385 150

3952 G20

ISP-ISN (mV) ISMON (V) 0.2 0.4 0.6 0.8 1.0 1.2 50 100 150 200

3952 G21

FB (V) 1.1 ISP-ISN (mV) 100 150 200 250 300 1.15 1.2 1.25 1.3

3952 G22

VCTRL = 2V VOUT (V)

245.0 ISP-ISN (mV)

247.5 250.0 252.5 255.0 10 20 30 40

3952 G23

CTRL (V) ISP-ISN (mV) 100 150 200 250 300 0.5 1 1.5 2

3952 G24

CLOAD (nF) tRISE/FALL (ns)500 600 700

3952 G25

2.5 5 7.5 100 900 tRISE (ns) tFALL (ns) 800 PWM 2V/DIV TG 5V/DIV 200ns/DIV 3952 G26 PMOS: VISHAY SILICONIX Si7309 PWM 2V/DIV TG 5V/DIV

3952 G27

PMOS: VISHAY SILICONIX Si7309

For more information www.linear.com/LT3952 TYPICAL PERFORMANCE CHARACTERISTICS PWM Generator Duty Cycle vs DIM Voltage PWM Generator Currents vs Temperature PWM Generator Frequency vs PWM Capacitor PWM Generator Thresholds vs Temperature PWM Generator Operation and Step IVINP-IVINN Threshold vs Temperature IVINCOMP vs IVINN-IVINP OVLO Thresholds vs Temperature 10ms/DIV PWM 0.5V/DIV DIM 0.5V/DIV ILED 200mA/DIV

3952 G35

1.2V PWM THRESHOLD IVINP-IVINN (mV) IVINCOMP (V) 0.8 1.2

3952 G29

0.4 20 40 60 1.6 TEMPERATURE (°C) –50 IVINP-IVINN (mV) 150

3954 G28

TEMPERATURE (°C) –50

1.125 OVLO THRESHOLDS (V)

1.150 1.175 1.200 1.225 1.250 1.275 OVLO RISING OVLO FALLING 0 50 100 150

3952 G30

DIM VOLTAGE (V) PWM GENERATOR DUTY CYCLE (%)

3952 G31

0.5 1 1.5 120 100 PWM CAPACITOR (nF) PWM FREQUENCY (Hz) 10000 1000 100 0 100 100010

3952 G32

TEMPERATURE (°C) –50 CURRENT (µA) 150

3952 G33

–15 0 50 100 –10 DIM PULLUP CURRENT PWM PULLUP CURRENT PWM PULLDOWN CURRENT TEMPERATURE (°C) –50 THRESHOLD (V) 0.8 1.2 150

3952 G34

0.4 0 50 100 1.6 0.6 0.2 1.4 DIM = 0.5V UPPER THRESHOLD LOWER THRESHOLD

For more information www.linear.com/LT3952 PIN FUNCTIONS GND (1, 12, 28, Exposed Pad Pin 29): Ground Pins. The exposed pad of the LT3952 acts as both GND and heat sink. It must be connected to a large copper area for proper operation. SW (Pins 2, 3, 4): Switch Pins. Minimize copper area at these pins to increase efficiency and reduce EMI. IVINN (Pin 5): Input Current Sense Amplifier Negative Input. The input current sense amplifier reduces the switching current in the case of an overload. VC is reduced when the IVINP-IVINN voltage exceeds the 60mV built-in potential. Tie IVINP-IVINN across an external sense resistor to set auxiliary current limit. If unused, tie to V IN. IVINP (Pin 6): Auxiliary Current Sense Amplifier Posi - tive Input. Also acts as the bias supply for the amplifier to provide a function independent from the V IN pin. The IVINP/IVINN amplifier can operate from voltages either above or below V IN. Tie this pin to the positive terminal of a sense resistor , and do not use resistance in series with this pin. If unused, tie to V IN. VIN (Pin 7): Input Supply Pin. Bypass this pin with a ca - pacitor to GND as close to the IC as possible. EN/UVLO (Pin 8): Master Enable and V IN Undervoltage Lockout. When low, the IC is put into shutdown mode and the Q current is reduced to <1/uni03BCA. This pin utilizes a 1.23V comparator with hysteresis, as well as a hysteresis current source for programming additional hysteresis externally. Drive with a digital signal greater than 1.5V for simple on/off control. Tie to a resistor divider between V IN and GND to set an external UVLO threshold. OVLO (Pin 9): Overvoltage Lock Out Comparator . This pin disables switching and TG in the case of an overvoltage. This pin utilizes a 1.23V comparator with hysteresis. When the voltage at OVLO exceeds the threshold, the switching is disabled until the voltage at OVLO falls 25mV below the threshold. Tie to GND if unused. INTV CC (Pin 10): Internal Low Dropout Regulator Output. INTVCC is regulated to 3V, and must be bypassed with an external capacitor of at least 2.2µF. INTVCC is the power supply for the internal DMOS gate driver and control circuitry. Users may apply <5mA loads to INTV CC. Over- loading INTVCC can cause unintentional device shutdown from INTVCC falling below the 2.68V UVLO threshold. SYNC/SPRD (Pin 11): Frequency Synchronization and Spread Spectrum Enable Pin. Tie low for fixed internal clock, tie to INTV CC for spread spectrum internal clock, or drive with an external clock for frequency synchronization with no spread spectrum. When using an external clock for frequency synchronization, R T resistor should be chosen to program a switching frequency 20% lower than the SYNC pulse frequency. Synchronization (switch turn-on) occurs 50ns after the rising edge of SYNC. VC (Pin 13): g m Amplifier Output for External Loop Compensation. Stabilize the loop with a C or series RC network. This pin is set to a high impedance state during PWM dimming off-time. RT (Pin 14): Switching Frequency Adjustment Pin. Set switching frequency using a resistor to GND (see Typical Performance Characteristics for values). For SYNC func- tion, set the frequency 20% slower than the SYNC pulse frequency. Do not leave this pin open. PCB layout must have this component close to the IC. DIM (Pin 15): PWM Generator Control Voltage. This pin outputs a fixed 20/uni03BCA current, and controls a triangle wave generator on the PWM pin to determine the PWM duty cycle. 0.2V to 1.2V range on DIM adjusts PWM duty from 0% to 100%. Float this pin or tie to INTV CC if unused, tie a resistor from DIM to GND to set a fixed voltage, or apply an external voltage to DIM for adjustable PWM duty cycle. FB (Pin 16): Output Voltage Loop Feedback Pin. Connect to a resistor divider from V OUT. In constant-voltage ap- plications, FB sets the output voltage. In constant-current applications, the FB divider is set higher than the expected output voltage to act as open-LED protection. As the volt- age at FB rises to within 45mV of the regulation point, the OPENLED flag is asserted if the output current also falls below one-tenth the full-scale value. If the FB voltage exceeds the regulation point by 30mV, the switching is terminated and the TG pin pulls high in order to discon - nect the LED load.

For more information www.linear.com/LT3952 PIN FUNCTIONS CTRL (Pin 17): Output Current Sense Adjust Pin. Sets voltage regulation threshold across ISP/ISN current sense resistor . 0.2V to 1.2V range on CTRL adjusts ISP/ISN threshold from 0mV to 250mV. Tie to V REF or INTVCC for fixed 250mV threshold. Below 100mV, the CTRL pin acts as an auxiliary PWM input for combination PWM/analog dimming on a single pin. V REF (Pin 18): Reference Voltage Output. This pin outputs a fixed 2V reference, and supplies up to 100/uni03BCA for use in generating a reference voltage for the CTRL pin. When using a resistor divider , bypass this pin with 100nF to GND. SS (Pin 19): Soft-Start and Hiccup Control Pin. This pin modulates oscillator frequency and VC voltage clamp when it is below 1.7V. A capacitor on the pin sets the soft-start interval as well as hiccup retry timing in fault mode. The SS pin has a 25/uni03BCA pull-up current in normal mode, a 2.5/uni03BCA pull-down current in hiccup mode, and a 120/uni03A9 pull-down resistance in start-up mode. Optional latchoff mode is set with a 750k pull-up resistor from INTV CC to SS. PWM (Pin 20): On/Off Control. Used for TG on/off control and PWM dimming of the LED. Logic low idles regulator to a lower Q current, makes the TG pin drive to I SP level, and makes the VC pin high impedance. Logic high turns on error amplifier , enables switching and TG. The PWM threshold is 1.2V. Tie to V REF or INTVCC for continuous operation. The PWM pin also supplies ±10µA switched current sources to generate a triangle wave on external capacitor for the PWM dimming generator . It is safe to overdrive these currents with an external signal. SHORTLED (Pin 21): Open-Drain Short-Circuit Indicator . SHORTLED pulls low in the case of an LED overcurrent fault, and releases during the start-up phase of the next soft-start cycle. The state of SHORTLED is only updated when the PWM pin is high. Tie this pin to desired logic high voltage with an external resistor . The maximum recommended sink current is 2mA to limit excess power dissipation. Leave the pin open if unused. OPENLED (Pin 22): Open-Drain Open-LED Indicator . OPENLED pulls low when the voltage at the FB pin is within 45mV of the regulation point and the LED current has dropped to 10% of the full-scale output. OPENLED releases when the FB voltage falls below the threshold. The state of OPENLED is only updated when the PWM pin is high. Tie this pin to desired logic high voltage with an external resistor . The maximum recommended sink current is 2mA to limit excess power dissipation. Leave the pin open if unused. IVINCOMP (Pin 23): Auxiliary Current Sense Amplifier Monitor Output. The voltage at IVINCOMP is a 20× ampli- fied and buffered version of the IVINP-IVINN differential voltage, and the VC voltage will be reduced when IVIN - COMP reaches its 1.2V threshold. A 1µF capacitor to GND is suggested to filter inductor ripple and compensate the input current loop. During PWM dimming, the IVINCOMP pin stores the input current regulation loop value on the capacitor during the PWM off time. Do not load this pin. If the input current regulation loop is not used, this pin may be connected to GND. ISMON (Pin 24): Output Current Monitor Pin. The volt - age at ISMON is a 4× amplified and buffered version of the ISP, ISN differential voltage. During PWM dimming, the ISMON voltage continues to reflect the instantaneous output current, falling during the PWM low time. TG (Pin 25): Top Gate Driver Output. An inverted and level- shifted version of the PWM input signal. Drives the gate of an external PMOS transistor between V ISP and VISP – 7.5V to provide load-side on/off control, PWM dimming, and fault mode disconnect. Leave TG unconnected if not used. ISN (Pin 26): Output Current Sense Amplifier Negative Input. Connect this pin to the load side of the output cur- rent sense resistor . If unused, tie to output voltage. ISP (Pin 27) : Output Current Sense Amplifier Positive Input. Also serves as the positive rail for the TG driver . Limit impedance in series with this pin.If unused, tie to output voltage.

For more information www.linear.com/LT3952 BLOCK DIAGRAM 1.23V1.155V –++ 2627 – + – +–+ –+– + 0.3V PWM 1.2V 0.1V 1.2V VMODE FBOV LEDOC x20 0.375V ISN ISMON VREF INTVCC 140µA 2, 3, 4 VC SW 0.1V OCP 22m/uni03A9 3952 BD ISP CTRL FB IVINN IVINP VIN INTVCC UV CTRPWM SS C/100.2V +1.23V SHDN 2µA LDO OSC + SSFM SSFM OFF TSD (165°C) SS/FL T SHDN 2.5µA 25µA LEDOCTSD FBOV S R Q G PWMON QD PWMON C/10 VMODE TSD INTVCC 1.2V SS RT GND SYNC/SPRD SS IVINCOMP EN/UVLO +1.23V OVSHDN OVLO9 SHORTLED21 x1 – OPENLED22 Q LEDOC OVP OTP PWM R S UV SSFM ON R 950mV INTVCC 10µA INTVCC 20µA 1.2V CTRPWM PWMON ISP ISP – 7.5V 10µA DIM S Q Q PWM TG 1, 12, 28, 29

For more information www.linear.com/LT3952 OPERATION The LT3952 is a fixed-frequency, current mode boost con- verter with a feature set ideal for driving high power LED lamps. It provides input and output current regulation, as well as output voltage regulation and fault handling. The operation of the LT3952 is best understood by referring to the Block Diagram. In normal operation, with the PWM pin low, the switching is disabled, the TG pin is pulled high to ISP to turn off the PMOS disconnect switch, the VC pin is high impedance to store the previous switching state on the external compensation capacitor , and the ISP/ISN pin bias currents are reduced to leakage levels. When the PWM pin transitions high, the TG pin transitions low after a short delay. At the same time, the internal os- cillator wakes up and generates a pulse to set the PWM latch, turning on the internal NMOS power switch. The switch current is sensed and added to a stabilizing slope compensation ramp, and the resultant signal is compared to the VC voltage. The inductor current increases linearly during the switch on-time. When the current sense signal exceeds the VC value, the latch is reset and the internal NMOS power switch is turned off. During the switch off-time, energy is transferred from the inductor and the inductor current decreases. At the completion of each oscillator cycle, internal signals such as slope compensa- tion return to their starting points and a new cycle begins with the set pulse from the oscillator. Through this repetitive action, the IC establishes a switch- ing duty cycle to regulate a current or voltage in the load. The VC signal is integrated over many switching cycles, and is an amplified version of the difference between the LED current sense voltage, measured between ISP and ISN, and the target difference voltage set by the CTRL pin. In this manner , the error amplifier sets the correct peak switch current level to keep the LED current in regulation. If the error amplifier output increases, more current is demanded in the switch; if it decreases, less current is demanded. If the switch current exceeds the internal 4.5A current limit, the latch is reset regardless of the state of the PWM comparator . Likewise, in any fault condition; i.e., FB overvoltage (V FB > 1.23V), LED overcurrent (VISP-ISN > 375mV), overvoltage lockout or INTV CC undervoltage the switching is immediately disabled. In addition to the V ISP-ISN to CTRL feedback loop, the LT3952 also provides additional loops to control input current and output voltage. The loops are connected in a wired-OR configuration, where the auxiliary loops are only allowed to reduce the value of VC in the event that one or more exceeds its threshold. This means that even if one or more of the auxiliary loops is below its regulation point, VC will not rise unless the output (LED) current sense is also below its regulation point. The first auxiliary loop is the output voltage feedback loop using the FB pin. It is typically used to prevent the output voltage from exceeding a safe value. The voltage at the FB pin is compared to an internal reference voltage of 1.2V, and the amplified difference pulls down the VC pin in the case that FB exceeds 1.2V. As VC drops, the switching current reduces and in this manner the output voltage is regulated so that FB = 1.2V.

For more information www.linear.com/LT3952 OPERATION The second auxiliary loop is the input current limit us - ing the IVINN, IVINP , and IVINCOMP pins. Similar to the output (LED) current loop, the input current is sensed as the differential voltage across a sense resistor . As the average IVINP/IVINN differential voltage exceeds 60mV, IVINCOMP reaches its 1.2V threshold, and VC is reduced in order to limit the input current to the 60mV threshold. INTV CC Bypass Capacitor INTVCC is the internal power supply for the IC, and sup- plies the gate drive to the internal power switch. A bypass capacitor is required from INTV CC to GND for stability and filtering of the switching noise. For best results, use a ceramic capacitor of 2.2µF or greater , and place the capacitor as close to the IC as possible. V REF Bypass Capacitor VREF is the 2V reference output and can be bypassed with 100nF to GND. For best results, place the bypass capacitor close to the IC and away from the noisy switching nodes. Programming the Turn-On/Turn-Off Thresholds with the EN/UVLO Pin The LT3952 provides an adjustable VIN undervoltage lock- out (UVLO) function using the EN/UVLO pin. The EN/UVLO function provides a precision 1.23V falling threshold with 75mV internal hysteresis as well as a 2/uni03BCA pull-down current in the off state to provide additional, user-programmable hysteresis. This pin can also be driven with a logic level greater than 1.5V or tied to V IN for always-on operation. In order to program an external UVLO, tie the EN/UVLO pin to a resistor divider between V IN and GND. The divider ratio determines the baseline turn-off/turn-on thresholds and the value of the upper resistor determines the ad - ditional hysteresis. VIN EN/UVLO L T3952

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The most important (and precise) threshold is the turn- off threshold from V IN falling. The following equations determine the resistor values: VUV(FALLING) = 1.23• 1+ R1 ⎝⎜ ⎞ VUV(RISING) = 1.305• 1+ R1 ⎝⎜ ⎞ ⎠⎟ +2µA • R1 For example, a 12V falling UVLO with roughly 10% total hysteresis requires 185k for R1. The closest standard value is 187k, therefore: R1 = 187k R2 = 21.5k V UV(FALLING) = 11.93V V UV(RISING) = 13.03V

For more information www.linear.com/LT3952 OPERATION Programming the Overvoltage Disable with the OVLO Pin It is also possible to program a disable threshold if the input voltage rises too high. The OVLO pin has a 1.23V comparator with 25mV internal hysteresis. If the voltage at OVLO exceeds the 1.23V threshold, the switching is disabled, TG pulls high, and the SS pin pulls low. The device begins a new soft-start sequence when the voltage at OVLO has fallen 25mV below the threshold. Although it is possible to connect this pin with an indepen- dent resistor divider , the component count is minimized by splitting the bottom resistance of the standard EN/UVLO divider to generate an additional tap point. Continuing the previous equation, the desired value of R3 is 8k for an OVLO threshold of 32V. Subtract this from the previous value of R2 in order to find the value of R2A. In our case, R3 = 8.06k and the closest 1% resistor for the new R2A value is 13.3k. The thresholds are recalculated if desired from the expanded divider ratios: VUV(FALLING) = 1.23• 1+ R1 R2A +R3 ⎝⎜ ⎞ VUV(RISING) = 1.305• 1+ R1 R2A +R3 ⎝⎜ ⎞ ⎠⎟ +2µA • R1 VOV(RISING) = 1.23• 1+ R1+R2A ⎝⎜ ⎞ VOV(FALLING) = 1.205• 1+ R1+R2A ⎝⎜ ⎞ In our example: R1 = 187k, R2A = 13.3k, R3 = 8.06k VUV(FALLING) = 11.998V V UV(RISING) = 13.104V V OV(RISING) = 31.796V V OV(FALLING) = 31.151V Figure 2 VIN EN/UVLO R2A L T3952 0VLO

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Using the previous values of R1 and R2 from the UVLO section, the new R3 value is computed using the desired rising threshold by: R3= 1.23• R1+R2 VOV(RISING) The middle resistor will be designated R2A. To obtain the value for R2A, subtract the calculated value of R3 from the old R2 value.

For more information www.linear.com/LT3952 OPERATION LED Current Control and Monitor The LED current is programmed through the combination of an external sense resistor and a voltage on the CTRL pin. The CTRL voltage adjusts the setpoint of the current sense amplifier on the ISP and ISN pins from 0mV to 250mV, and the external sense resistor defines the output current for a given setpoint. The current sense resistor is typically placed at the top of the LED strand, although the rail-to-rail ISP/ISN inputs allow placement at the bottom of the strand as well. The required CTRL voltage for a desired analog setpoint is computed by: V CTRL = 0.2 + 4 • VISP-ISN As the CTRL voltage nears 1.2V, a crossover from adjustable threshold to a precision internal 250mV setpoint takes place and some nonlinearity occurs as shown in the ISP-ISN vs CTRL graph in the Typical Performance Characteristics. It is therefore desirable to drive the CTRL pin well above 1.2V when the 250mV setpoint is desired. Tying CTRL to the 2V V REF output is an excellent method of doing so. LED Current Monitoring The ISMON pin provides a buffered output representing the differential voltage on ISP-ISN for current monitoring applications. The normal working range of ISMON is from 0V to 1V, and the gain from ISP-ISN to ISMON is 4. This corresponds to a 1V output at ISMON when the ISP-ISN differential voltage has reached the 250mV maximum. ISP RLED SENSED CURRENTL T3952 ISN

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The required sense resistor for a desired output current is computed by: RLED = VISP-ISN IOUT In the case of the fixed 250mV setpoint: RLED = 0.25 IOUT For example, a 500mA output requires a 0.5/uni03A9 sense resis- tor when using the fixed 250mV setpoint. In adjustable mode, the working range of CTRL is from 0.2V to 1.2V and adjusts the setpoint of ISP and ISN from 0mV to 250mV. In this manner , analog dimming is achieved. CTRL (V) ISP-ISN (mV) 100 150 200 250 300 0.5 1 1.5 2

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and PWM dimming of the LED current. output driving CTRL also gives excellent results.

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frequency is defined by the external capacitor . Figure 6. Lower DIM Voltage Figure 7. Higher DIM Voltage

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ferent points, changing the PWM duty cycle.

response for high dimming ratios. A common selection is 39nF for roughly 133Hz. be applied at the DIM pin using a DAC or external supply. from dark to full brightness, only a capacitor is required. in parallel with the DIM resistor .

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Figure 8. Fade on to Full Brightness, or to Preset Duty

For more information www.linear.com/LT3952 Figure 9 IVINCOMP IVINP IVINN RIVIN SENSED CURRENT L T3952

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The LT3952 provides adjustable input current limiting through the IVINP/IVINN/IVINCOMP amplifier. Connect the IVINP and IVINN sensing terminals across a resistor in series with the input. A 20x amplified version of the IVINP–IVINN differential is generated at IVINCOMP. A capacitor at IVINCOMP provides filtering and averaging of the input ripple. As the average IVINP–IVINN differential reaches 60mV, the IVINCOMP voltage will reach its 1.2V regulation threshold and the cycle-by-cycle switch current will be reduced. In this manner, the input current is regulated to 60mV differential between IVINP and IVINN. RSENSE m Ω() = 60mV IIN LIM() A() For example, a 2.4A input current limit is programmed with a 25m/uni03A9 sense resistor . Be aware that input current on start-up and PWM dim - ming is larger than steady state due to the output current required to fill the output capacitor . It is recommended to set the input limit appropriately to prevent interruption of the regulated output. Input Current Monitor An input current monitor is available as the voltage on IVINCOMP, which reflects a voltage equal to 20× the IVINP-IVINN differential voltage and has a working range of 0V to 1.2V as the IVINP-IVINN voltage varies from 0mV to 60mV. IVINCOMP is a high impedance output and should not be loaded. Averaging of current sense ripple, and compensa- tion of the feedback loop is achieved using a 1µF capacitor from IVINCOMP to GND. Output Voltage Regulation/Limiting The LT3952 provides a voltage-feedback error amplifier through the FB pin to provide output voltage regulation and limiting for open-LED protection. In the case of an open-LED strand, the current commanded by CTRL is never achieved and the device continues to drive the output voltage higher . If left unchecked, this could result in overvoltage damage to the external components and the power switch itself, and therefore an output volt- age limit is required. By connecting FB to a resistor divider between V OUT and GND, the maximum output voltage regulates at the 1.2V threshold of the FB pin. The maximum output voltage is computed as follows: VOUT V() = 1.2• 1+ R4 ⎝⎜ ⎞ Figure 10 Figure 11 IVINP IVINN RIVIN CF LT RF LT L T3952

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In some cases, such as deep discontinuous conduction, a large input ripple current may cause the input current limit to activate early, cutting into the typical regulation profile. In this situation, it is possible to filter the ripple down to a smoother level using an external RC network.

For more information www.linear.com/LT3952 OPERATION A simple method to determine the proper resistor values is to choose a value of R5 that draws a tolerable amount of current at the 1.2V regulation point, and to compute R4 by using: R4 = VOUT –1.2() • R5 1.2 For example, R5 = 24k draws 50/uni03BCA at the regulation point, and for a 24V output limit, the desired value of R4 is 456k. The closest standard value to this is 453k, providing 23.85V output voltage limit. It is necessary to set the regulation point slightly higher than the worst-case voltage drop of the LEDs to avoid cut-in of the voltage limit during normal regulation. Open LED Flag and Overvoltage Protection The LT3952 provides an indicator of the open-LED condition on the OPENLED pin, as well as an internal overvoltage detection to prevent output overshoot if the LED strand goes open under load. Both of these features are based on the voltage at the FB pin. The OPENLED pin consists of an open-drain NMOS pull down to be connected with an external pull-up resistor to the user’s desired voltage. This pin tolerates up to 42V, and has a pull-down strength of 60/uni03A9. Please be aware of power dissipation and keep the OPENLED current to a few mA maximum. The OPENLED pin pulls low when the following two condi- tions are met: 1. The voltage at FB rises to within 45mV of the 1.2V regulation point. 2. The output current is detected to be less than one-tenth of the value commanded by CTRL. The OPENLED pin releases when the voltage at FB falls to 65mV below the 1.2V regulation point. This sequence prevents false OPENLED flags from momentary overshoot. An overvoltage condition is detected by the voltage at FB rising to 30mV above the 1.2V regulation point. Upon detection of an overvoltage condition, the switching is disabled and TG is pulled high to disconnect and protect the load. Switching is re-enabled when the FB voltage falls by 15mV. An overvoltage condition does not affect the state of the OPENLED pin. Switching Frequency The switching frequency is programmed with a resistor from the RT pin to GND. The RT pin is regulated to 1.2V, and the output current of R T adjusts the oscillator frequency. RT L T3952 RT

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Table 1 provides some commonly used values. Table 1. Switching Frequency vs RT Value transition to the external frequency. suppression from the frequency variation itself.

during standard EMI test dwell times. of 25% of the switch current limit. Table 2 provides some recommended inductor vendors. Table 2. Inductor Manufacturers Figure 13. Average Conducted EMI – 1MHz

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the expense of increased switching loss. appropriately for the 4A current limit of the device.

For more information www.linear.com/LT3952 OPERATION Output Capacitor Selection In the case of driving LEDs, their exponential current/ voltage characteristic dictates that output voltage ripple translates almost directly to LED current ripple. Although the effect is not visible to the eye, large LED current ripple may affect the output current accuracy and color spectrum and it is therefore advisable to keep the output voltage ripple below a few percent. For the boost and buck-boost topologies, output cur - rent is delivered in pulses and the filtering requirement is higher than for the buck topology with its continuous output current. Assuming a low ESR ceramic capacitor and 25% inductor current ripple, use the following equations to compute the required output capacitance for a desired output ripple voltage, ∆V LED. Boost, Buck-Boost: COUT = ILED •V LED –VIN() VLED • ∆VLED •f SW Buck: COUT = 0.3•ILED 8• ∆VLED •fSW Input Capacitor Selection The input capacitor is also selected based on desired voltage ripple. Complementary to output capacitor selec- tion, the discontinuous input current of the buck topology requires more filtering than the continuous input current of the boost or buck-boost. Use the following equations to determine the input capacitance required for a desired input ripple voltage, ∆V IN. Boost, Buck-Boost: CIN = 0.3•ILED • VLED VIN 8• ∆VIN •f SW Buck: CIN = VIN •ILED •V IN –VLED() ∆VIN •VIN2 •fSW Schottky Rectifier Selection The power Schottky diode conducts the switching current during the switch off-time. Select a diode rated for at least 1.5 • I LED to account for current variation from efficiency and inductor ripple. The reverse-breakdown voltage should be at least 20% greater than the maximum reverse voltage expected in circuit. Loop Compensation The LT3952 uses an internal transconductance error amplifier whose VC output compensates the control loop. The external inductor , output capacitor and the compen- sation resistor and capacitor determine the loop stability. The inductor and output capacitor are chosen based on performance, size and cost. The compensation resistor and capacitor at VC are selected to optimize control loop response and stability. For typical LED applications, a 6.8nF to 10nF compensation capacitor at VC is adequate, and a series resistor increases the slew rate on the VC pin to maintain tighter regulation of LED current during fast transients on the input supply of the converter . External PMOS Disconnect/PWM Switch A high side PMOS disconnect switch with a minimum V TH of –2V is recommended in most LT3952 applications. This switch is enabled and disabled during PWM dimming, and disconnects the output in shutdown and during fault conditions. Select a PMOS transistor with a V DS rating greater than the open-LED regulation voltage set by FB, and with a continuous current rating greater than I LED. Soft-Start The LT3952 incorporates flexible soft-start and the option of hiccup or latchoff mode for customizing fault response. The SS pin provides a 25/uni03BCA pull-up current for charging, a 2.5/uni03BCA pull-down current for discharging, and a 120/uni03A9 NMOS pull-down switch for clearing an external soft- start capacitor . The state of each of these components is determined by the soft-start/fault sequence, and will be described herein. Shutdown Mode: During shutdown mode, all SS cur - rents and the pull-down switch are disabled, effectively

initial voltage at SS can be considered approximately 0V. charge sequence as described. at which point switching and the TG driver are enabled. ated with an 8.2nF capacitor . detail in the Fault Handling section.

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Figure 14. PWM Latched Startup even as the soft-start voltage rises.

For more information www.linear.com/LT3952 OPERATION Once SS has discharged to the 0.2V level, the sequence of clearing SS with the 120/uni03A9 NMOS pull-down and restarting the 25/uni03BCA charge phase reoccurs as previously described. Switching and TG are not re-enabled until SS again climbs to the 0.2V threshold. If at this point an overcurrent is still detected, then SW and TG are again disabled as SS continues to climb to the 1.7V threshold before reversing direction. In this manner , a hiccup retry cycle is obtained with a maximum switching duty cycle of 10%, the ratio of 25/uni03BCA pull-up to 2.5/uni03BCA pull-down currents. This low hiccup duty cycle reduces input power during sustained overload conditions. 1.7V 0.2V

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SHORTLEDFigure 15. SS in Sustained Hiccup Mode If a latched-off response is desired, a user simply sets a pull-up resistor from INTVCC to SS with a value low enough to prevent SS from discharging to the 0.2V level. For the low pull-down current of 2.5/uni03BCA, even a relatively large value of 750k to INTV CC prevents SS from reaching the automatic retry threshold and effectively provides a fault latchoff. At this point, a manual retry is obtained by entering and exiting shutdown mode, upon which the 120/uni03A9 NMOS pull-down clears the SS voltage in preparation for retry. SHORTLED Flag: The LT3952 provides an open-drain SHORTLED pin to flag the overcurrent detection. This pin is connected with a pull-up resistor to the user’s voltage (up to 42V), and has a pull-down strength of 60/uni03A9. Please be aware of power dissipation and keep the pull-up current to a few mA maximum. The SHORTLED pull-down activates immediately upon detection of a fault and stays on throughout the charge/ discharge phase of the hiccup cycle. The pull-down releases as the SS capacitor is cleared to 0V during the restart phase and stays released as SS re-charges to the 0.2V retry threshold. If at this point a fault is again detected, the pin is again pulled down as the hiccup retry cycle continues. For the user detecting fault with an IRQ, this falling edge is used to count a desired number of faults before full system shutdown, or the rising edge is used to prepare the system for a new start-up cycle. Board Layout The high speed operation of the LT3952 demands careful attention to board layout and component placement. The exposed pad of the package is the GND terminal of the IC and is also important for thermal management of the IC. It is crucial to achieve a good electrical and thermal contact between the exposed pad and the ground place of the board. To reduce electromagnetic interference (EMI), it is important to minimize the area of the high dV/ dt switching node between the inductor , SW pins, and anode of the Schottky rectifier . Use a ground plane under the switching node to eliminate interplane coupling to sensitive signals. The length of the high dI/dt trace from the SW pin through the Schottky recti- fier and filter capacitor to GND should be minimized, and the IC GND pins should be connected to the large copper area beneath the IC. The GND terminal of the INTV CC capacitor should be placed near the GND of the switching path. The ground for the V REF capacitor , the IVINCOMP capacitor , the compensation network, and other DC control signals should be star connected to the underside of the IC. Do not route high impedance signals such as FB, DIM, IVINN, RT and VC near the switching nodes, and minimize the length of their routes to avoid picking up switching noise. Since there is a small, but variable, DC bias current on the ISP/ISN/IVINP/IVINN inputs, minimize resistance in series with these pins to avoid creating an offset. Kelvin connecting these lines to the terminals of their respective sense resistors provides best performance.

For more information www.linear.com/LT3952 TYPICAL APPLICATIONS Short-Circuit Robust Boost LED Driver with Spread Spectrum Frequency Modulation IVINP L T3952 VIN VC SHORTLED OPENLED SHORTLED OPENLED SYNC/SPRD INTVCC TG ISN ISP FB GND INTVCC 750m/uni03A9 EN/UVLO OVLO CTRL VREF PWM ISMON DIM IVINCOMP RT SS 2.2µF

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1µF8.2nF 90.9k 1MHz 21.5k 57V OPEN LED REGULATION 100k100k INTVCC PWM ISMON 3.6k IVINN 4A INPUT LIMIT 15m/uni03A9 10µH D1 SW 4.7µF VIN 7V TO 42V 2.2µF 100V D1: VISHAY VS-10BQ060 L1: WURTH WE-LHMI74437349100 M1: VISHAY Si7415DN ILED 1A/DIV SHORTLED 2V/DIV

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VIN (V) LED CURRENT (mA)

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37961 TA02c100ms/DIV

FREQUENCY (MHz) AMPLITUDE (dBµV)

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Short LED Protection without RSS: Hiccup Mode LED Current vs Input Voltage Short LED Protection with RSS: Latchoff Mode Average Conducted EMI Comparison

For more information www.linear.com/LT3952 TYPICAL APPLICATIONS SEPIC LED Driver with Input Current Limit IVINP L T3952 VIN VC SHORTLED OPENLED SHORTLED D1: VISHAY VS-10BQ060 L1: WURTH WE-DD744874100 M1: VISHAY Si7309DN OPENLED SYNC/SPRD INTV CC TG ISN ISP FB GND INTVCC 620m/uni03A9 EN/UVLO OVLO CTRL VREF PWM ISMON DIM IVINCOMP RT SS 2.2µF

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4.7µF 35VL1B 2.2µF 100V D1 1µF10nF 90.9k 1MHz 49.9k 100k 39.2k 4.75k 100k100k INTVCC PWM ISMON IVINN 3A INPUT LIMIT 20m/uni03A9 • L1A 10µH SW 4.7µF VIN 5V TO 35V 42V TRANSIENT 4V UVLO FALLING 36.5V OVLO RISING

6 LED (17V)

SEPIC Efficiency vs Input VoltageLED Current vs Input Voltage VIN (V) LED CURRENT (mA)

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VIN (V) EFFICIENCY (%)

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For more information www.linear.com/LT3952 SHORTLED 2V/DIV

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1.67µs 4000:1 2.22µs 3000:1 3.33µs 2000:1PWM 1V/DIV 1.67µs 1.67µs 1.67µs 4000:1 2.22µs 2.22µs 2.22µs 3000:1 3000:1 3.33µs 3.33µs 3.33µs 2000:1 2000:1 2000:1 LED Dead Short Response LED Current vs Input Voltage Efficiency Over Working Range High PWM Dimming Ratio TYPICAL APPLICATIONS 2MHz Boost LED Driver with 4000:1 PWM Dimming and Overvoltage Protection IVINP L T3952 VIN VC SHORTLED OPENLED SHORTLED D1: PMEG4010 L1: WURTH WE-LHMI 74437346033 M1: VISHAY Si7309DN OPENLED SYNC/SPRD INTV CC TG ISN ISP FB GND INTVCC 1.65/uni03A9 26V OPEN LED REGULATION EN/UVLO OVLO CTRL V REF PWM ISMON DIM IVINCOMP RT SS 2.2µF

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8.2nF 4.7µF 50V 3.3µH 1µF10nF 37.4k 2.15MHz 12.1k 143k 24.3k 12.1k 100k100k INTVCC PWM ISMON 249k 2.2k IVINN 3A INPUT LIMIT 20m/uni03A9 SW 4.7µF VIN 7V TO 16V 40V TRANSIENT 6.1V UVLO FALLING 18.3V OVLO RISING

8 LED (22V)

VIN (V) LED CURRENT (mA)

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VIN (V) EFFICIENCY (%)

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For more information www.linear.com/LT3952 TYPICAL APPLICATIONS 3MHz Buck-Boost LED Driver with Internal PWM Dimming and Fade Start IVINP L T3952 VIN VC SHORTLED OPENLED SHORTLED OPENLED SYNC/SPRD INTVCC TG ISN ISP FB GND INTVCC 0.75/uni03A9 EN/UVLO PWM OVLO CTRL VREF DIM IVINCOMP RT SS 2.2µF

3952 TA05a

1µF 100V 1µF10nF 25.5k 3MHz 21.5k 31.6k 100k100k 75k INTVCC 2.4k D1: VISHAY VS-10BQ060 L1: WURTH WE-LHMI74437346025 M1: VISHAY Si7309DN IVINN 15m/uni03A9 2.5µH SW 4.7µF VIN 5V TO 35V 42V TRANSIENT 39V OVLO RISING 2.2µF 0.25s FADE 39nF 130Hz

8 LED

D1 4.7µF 50V 57V LIMIT DIM (V) PERCENT (%)

3952 TA05c

2.5 21 0.5 1.5 PWM DUTY CYCLE EFFICIENCY VIN = 12V 100 VIN (V) EFFICIENCY (%)

3952 TA05b

PWM Duty Cycle and Efficiency vs DIM VoltageEfficiency vs Input Voltage Power On – Fade Start

3952 TA05d

For more information www.linear.com/LT3952 PACKAGE DESCRIPTION Please refer to http://www.linear .com/product/LT3952#packaging for the most recent package drawings. FE28 (EB) TSSOP REV K 0913 0.09 – 0.20 (.0035 – .0079) 0° – 8° 0.25 REF 0.50 – 0.75 (.020 – .030) 4.30 – 4.50* (.169 – .177) 1 34 5 6 7 8 9 10 11 12 13 14 19 20 22 21 15 16 18 17 9.60 – 9.80* (.378 – .386) 4.75 (.187) 2.74 (.108) 28 27 26 2524 23 1.20 (.047) MAX 0.05 – 0.15 (.002 – .006) 0.65 (.0256) BSC 0.195 – 0.30 (.0077 – .0118) TYP 2RECOMMENDED SOLDER PAD LAYOUT EXPOSED PAD HEAT SINK ON BOTTOM OF PACKAGE0.45 ±0.05

0.65 BSC

4.50 ±0.10 6.60 ±0.10 1.05 ±0.10 4.75 (.187) 2.74 (.108) MILLIMETERS (INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.150mm (.006") PER SIDE NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS 2. DIMENSIONS ARE IN 3. DRAWING NOT TO SCALE SEE NOTE 4 4. RECOMMENDED MINIMUM PCB METAL SIZE FOR EXPOSED PAD ATTACHMENT 6.40 (.252) BSC 28-Lead Plastic TSSOP (4.4mm) (Reference LTC DWG # 05-08-1663 Rev K) Exposed Pad Variation EB

For more information www.linear.com/LT3952 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However , no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

REVISION HISTORY

REV DATE DESCRIPTION PAGE NUMBER A 01/16 Replaced reference to Note 5 to Note 4 in Absolute Maximum Table Removed Note 4 from INTVCC Dropout Voltage specification Replaced Note 5 with Note 4 Clarified SS (Pin 19) description – replaced “shutdown mode” with “start-up mode” Clarified the Block Diagram pin designators Clarified Figure 11 Clarified Open LED Flag and Overvoltage section 60mV becomes 65mV Clarifed LED Dead Short Response graph Clarifed Power On – Fade Start graph Clarifed Related Parts table B 01/17 Clarified T ypical Application UVLO/OVLO 27

For more information www.linear.com/LT3952  LINEAR TECHNOLOGY CORPORATION 2015 LT 0117 REV B • PRINTED IN USA Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LT3952 RELATED PARTS TYPICAL APPLICATION 3A Buck Mode LED Driver PART NUMBER DESCRIPTION COMMENTS LT3795 110V High Side LED Controller with Spread Spectrum and Boost Short-Circuit Protection VIN: 4.5V to 110V, VOUT(MAX) = 110V, PWM Dimming = 3000:1, ISD < 10mA, TSSOP-28 Package LT3518 2.3A, 2.5MHz High Current LED Driver with 3000:1 Dimming with PMOS Disconnect FET Driver V IN: 3V to 30V, VOUT(MAX) = 45V, 3000:1 PWM Dimming, ISD < 1/uni03BCA, 4mm × 4mm QFN-16 and TSSOP-16E Packages LT3755/LT3755-1/ LT3755-2 High Side 40V, 1MHz LED Controllers with T rue Color 3000:1 PWM Dimming V IN: 4.5V to 40V, VOUT(MAX) = 75V, 3000:1 PWM Dimming, ISD < 1/uni03BCA, 3mm × 3mm QFN-16 and MSOP-16E Packages LT3956 High Side 80V, 3.3A, 1MHz LED Driver with T rue Color 3000:1 PWM Dimming V IN: 6V to 80V, VOUT(MAX) = 80V, PWM Dimming = 3000:1, ISD < 1/uni03BCA, 5mm × 6mm QFN-36 Package LT3761 High Side 80V, 1MHz LED Controller with 3000:1 PWM Dimming and Internal PWM Generator V IN: 4.5V to 60V, VOUT(MAX) = 80V, 3000:1 T rue Color PWM Dimming, Analog, ISD/uni00A0</uni00A01/uni03BCA, MSOP-16E Package LT3478/LT3478-1 4.5A, 2MHz High Current LED Drivers with 3000:1 Dimming V IN: 2.8V to 36V, VOUT(MAX) = 40V, 3000:1 PWM Dimming, ISD < 1/uni03BCA, LT3954 High Side 40V, 5A 1MHz LED Driver with 3000:1 PWM Dimming and Internal PWM Generator V IN: 4.5V to 40V, VOUT(MAX) = 40V, T rue Color PWM Dimming = 3000:1, Analog, ISD < 1/uni03BCA, 5mm × 6mm QFN-36 Package L T3952 VIN VC SHORTLED OPENLED SHORTLED SYNC/SPRD TG IVINP IVINN IVINCOMP ISN EN/UVLO OVLO INTVCC ISMON GND SW FB CTRL VREF PWM DIM RTSS 2× 4.7µF 50V 4.7µF 50V

3952 TA06a

100nF6.8nFD1: DIODES, INC SBR3A40SA L1: WURTH WE-LHMI74437346047 M1: VISHAY Si7309DN 90.9k 1MHz 78.7k 12.4k 100k INTVCC PWM

3 TO 9 LED

(3V TO 30V) 220/uni03A9 82m/uni03A9 4.7µH ISP 1µF 50V V IN 12V TO 40V 9.6V FALLING UVLO 2.2µF Efficiency vs VINLED Current vs Input Voltage VIN (V) EFFICIENCY (%)

3952 TA06c

3 LED (30W)

5 LED (50W)

7 LED (70W)

9 LED (90W)

VIN (V) LED CURRENT (A)

3952 TA06b

3.25 3.10 3.15 3.00 3.20 3.05 2.95

3 LED