LTC4366 LINER
Document overview
- Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 24
Technical content
For more information www.linear .com/L TC4366 TYPICAL APPLICATION FEATURES DESCRIPTION High Voltage Surge Stopper The LT C®4366 surge stopper protects loads from high voltage transients. By controlling the gate of an external N-channel MOSFET, the LTC4366 regulates the output during an overvoltage transient. The load may remain operational while the overvoltage is dropped across the MOSFET. Placing a resistor in the return line isolates the LTC4366 and allows it to float up with the supply; therefore, the upper limit on the output voltage depends only on the availability of high valued resistors and MOSFET ratings. An adjustable overvoltage timer prevents MOSFET dam- age during the surge while an additional 9-second timer provides for MOSFET cool down. A shutdown pin reduces the quiescent current to less than 14µA during shutdown. After a fault the LTC4366-1 latches off while the LTC4366 will auto-retry. Overvoltage Protected 1.5A, 28V Supply Overvoltage Protector Regulates Output at 43V During T ransient
APPLICATIONS
n Rugged Floating Topology n Wide Operating Voltage Range: 9V to >500V n Adjustable Output Clamp Voltage n Controls N-Channel MOSFET n Adjustable Protection Timer n Internal 9-Second Cool-Down Timer n Shutdown IQ < 14µA n 8-Lead TSOT and 3mm × 2mm DFN Packages n Industrial, Automotive and Avionic Surge Protection n High Voltage DC Distribution n 28V Vehicle Systems L, LT, LT C, LT M, Linear Technology and the Linear logo are registered trademarks and ThinSOT is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Patents pending. VDD OUT 2nF GATE IXTK90N25L2 SD FB 1µF 0.47µF 12.4k VOUT 1.5A VIN 28V 422k
436612 TA01a
46.4k 10/uni03A9 324k L TC4366-2 TIMER BASEVSS 28V 100ms/DIV
436612 TA01b
For more information www.linear .com/L TC4366 ABSOLUTE MAXIMUM RATINGS Input Voltages Output Voltages (Notes 1, 2) All voltages relative to VSS, unless otherwise noted. VDD 1 SD 2 TIMER 3 VSS 4
8 GATE
7 OUT
5 BASE
TJMAX = 150°C, θJA = 195°C/W TOP VIEW DDB PACKAGE 8-LEAD (3mm × 2mm) PLASTIC DFN 1 V SS TIMER SD VDD BASE FB OUT GATE TJMAX = 150°C, θJA = 75°C/W IF VSS IS SOLDERED TO PCB, θJA = 135°C/W IF VSS IS NOT SOLDERED TO PCB EXPOSED PAD (PIN 9), PCB VSS CONNECTION OPTIONAL PIN CONFIGURATION Currents Operating Ambient Temperature Range (Note 4) Lead Temperature (Soldering, 10 sec)
For more information www.linear .com/L TC4366 ORDER INFORMATION Lead Free Finish TAPE AND REEL (MINI) TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC4366CTS8-1#TRMPBF LTC4366CTS8-1#TRPBF L TFMC 8-Lead Plastic TSOT-23 0°C to 70°C LTC4366ITS8-1#TRMPBF LTC4366ITS8-1#TRPBF L TFMC 8-Lead Plastic TSOT-23 –40°C to 85°C LTC4366HTS8-1#TRMPBF LTC4366HTS8-1#TRPBF L TFMC 8-Lead Plastic TSOT-23 –40°C to 125°C LTC4366CDDB-1#TRMPBF LTC4366CDDB-1#TRPBF LFMD 8-Lead (3mm × 2mm) Plastic DFN 0°C to 70°C LTC4366IDDB-1#TRMPBF LTC4366IDDB-1#TRPBF LFMD 8-Lead (3mm × 2mm) Plastic DFN –40°C to 85°C LTC4366HDDB-1#TRMPBF LTC4366HDDB-1#TRPBF LFMD 8-Lead (3mm × 2mm) Plastic DFN –40°C to 125°C LTC4366CTS8-2#TRMPBF LTC4366CTS8-2#TRPBF L TFMF 8-Lead Plastic TSOT-23 0°C to 70°C LTC4366ITS8-2#TRMPBF LTC4366ITS8-2#TRPBF L TFMF 8-Lead Plastic TSOT-23 –40°C to 85°C LTC4366HTS8-2#TRMPBF LTC4366HTS8-2#TRPBF L TFMF 8-Lead Plastic TSOT-23 –40°C to 125°C LTC4366CDDB-2#TRMPBF LTC4366CDDB-2#TRPBF LFMG 8-Lead (3mm × 2mm) Plastic DFN 0°C to 70°C LTC4366IDDB-2#TRMPBF LTC4366IDDB-2#TRPBF LFMG 8-Lead (3mm × 2mm) Plastic DFN –40°C to 85°C LTC4366HDDB-2#TRMPBF LTC4366HDDB-2#TRPBF LFMG 8-Lead (3mm × 2mm) Plastic DFN –40°C to 125°C LTC4366MPTS8-1#TRMPBF LTC4366MPTS8-1#TRPBF L TFMC 8-Lead Plastic TSOT-23 –55°C to 125°C LTC4366MPTS8-2#TRMPBF LTC4366MPTS8-2#TRPBF L TFMF 8-Lead Plastic TSOT-23 –55°C to 125°C LTC4366MPDDB-1#TRMPBF LTC4366MPDDB-1#TRPBF LFMD 8-Lead (3mm × 2mm) Plastic DFN –55°C to 125°C LTC4366MPDDB-2#TRMPBF LTC4366MPDDB-2#TRPBF LFMG 8-Lead (3mm × 2mm) Plastic DFN –55°C to 125°C TRM = 500 pieces. *Temperature grades are identified by a label on the shipping container. Consult L TC Marketing for parts specified with wider operating temperature ranges. Consult L TC Marketing for information on lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
For more information www.linear .com/L TC4366 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. All voltages relative to VSS, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VDD Regulator VZ(VDD) VDD Shunt Regulator Voltage I = 1mA l 11.5 12 12.5 V ∆VZ(VDD) VDD Shunt Regulator Load Regulation I = 1mA to 5mA LTC4366C/I/H LTC4366MP l l 130 mV mV V DD VDD Supply Voltage (Note 3) l 4.5 VZ(VDD) V IVDD(STLO) VDD Pin Current – Start-Up, Gate Low GATE = 0V, VDD = 7V, OUT = 0V l 15 23 µA IVDD(STHI) VDD Pin Current – Start-Up, Gate High GATE Open, VDD = 7V, OUT = 0V l 9 13 µA IVDD(SD) VDD Pin Current – Shutdown VDD = 7V, OUT = 0V l 5 8 µA OUT Regulator VZ(OUT) OUT Shunt Regulator Voltage I = 1mA, BASE = 0V l 5.0 5.7 6.0 V ∆VZ(OUT) OUT Shunt Regulator Load Regulation I = 1mA to 5mA l 30 70 mV OUT OUT Supply Voltage (Note 3) l 3.0 VZ(OUT) V VUVLO1 OUT Undervoltage Lockout 1 Rising LTC4366C/I/H LTC4366MP l l 2.42 2.42 2.55 2.55 2.75 2.80 V V UVH1 OUT Undervoltage Lockout 1 Hysteresis l 0.2 0.28 0.4 V VUVLO2 OUT Undervoltage Lockout 2 Rising l 4.5 4.75 4.9 V ∆VUVH2 OUT Undervoltage Lockout 2 Hysteresis l 0.3 0.4 0.5 V IOUT(AMP) OUT Pin Current – Regulation Amplifier On l 37 54 µA IOUT(CP) OUT Pin Current – Charge Pump On l 150 220 µA IOUT(SD) OUT Pin Current – Shutdown l 3 6 µA BASE, VSS VZ(BASE) BASE Shunt Regulator Voltage (OUT – BASE) I = –10µA, OUT = 4.5V l 5.5 6.2 6.6 V ∆VZ(BASE) BASE Shunt Regulator Load Regulation I = –10µA to –80µA, OUT = 4.5V l 125 200 mV IVSS(AMP) VSS Pin Current – Regulation Amplifier On l –30 –45 –72 µA IVSS(CP) VSS Pin Current – Charge Pump On l –108 –160 –230 µA IVSS(SD) VSS Pin Current – Shutdown l –7 –12 µA GATE Drive ∆VGATE External N-Channel Gate Drive (GATE – OUT) OUT = 4.9V, I = 0, –1µA l 11.2 12 12.5 V IGATE(ST) GATE Pin Current – Start-Up GATE = OUT = 0V LTC4366C/I/H LTC4366MP l l –4.5 –3.2 –7.5 –7.5 –11 –11 µA µA I GATE(CP) GATE Pin Current – Charge Pump On GATE = 5V, OUT = 4.9V l –14 –20 –28 µA IGATE(FD) GATE Pin Current – Fast Discharge GATE = 10V, OUT = 4.9V l 122 200 300 mA IGATE(F LT) GATE Pin Current – Fault GATE = 10V, OUT = 4.9V l 0.3 0.7 1.2 mA
For more information www.linear .com/L TC4366 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. All voltages relative to VSS, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS FB, SD, TIMER VFB(REG) 3% FB pin Regulation Threshold (OUT – FB) l 1.193 1.23 1.267 V IFB FB Pin Leakage Current OUT – FB = 1.2V l 0 ±1 µA VSD(TH) SD Pin Threshold Voltage (VDD – SD) Falling l 1.0 1.5 2.3 V VSD(HYST) SD Pin Hysteresis LTC4366C/I/H LTC4366MP l l 147 129 280 280 530 530 mV mV I SD SD Pin Input Pull-Up Current VDD – SD = 0.7V LTC4366C/I/H LTC4366MP l l –0.7 –0.5 –1.6 –1.6 –3.5 –3.5 µA µA V TIMER(H) TIMER Pin Threshold TIMER Rising, VDD = 7V, OUT = VZ(OUT) l 2.6 2.8 3.1 V ITIMER(UP) TIMER Pin Pull-Up Current TIMER = 1V LTC4366C/I/H LTC4366MP l l –5.1 –13 –13 µA µA I TIMER(DN) TIMER Pin Pull-Down Current TIMER = 1V LTC4366C/I/H LTC4366MP l l 0.9 0.7 1.8 1.8 2.8 2.8 µA µA I TIMER(RATIO) TIMER Pin Current Ratio ITIMER(DN)/ITIMER(UP) l 15 20 25 % AC Characteristics tDL Y – SD SD Low to Gate Low Filter Time Step VDD – SD from 0V to 3V l 420 700 1200 µs tDL Y – FAST FB Low to Gate Low Delay Time Step OUT – FB from 0V to 1.3V l 60 150 300 ns tD(COOL) Cool-Down Timer (Internal) VDD = VZ(VDD) LTC4366C/I/H LTC4366MP l l 5.9 5.9 Seconds Seconds Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All currents into pins are positive. Note 3: Limits on the maximum rating is defined as whichever limit occurs first. An internal clamp limits the GATE pin to a maximum of 12V above source. Driving this pin to voltages beyond the clamp may damage the device. Note 4: T J is calculated from the ambient temperature, TA, and power dissipation, PD, according to the formula: TJ = TA + (PD • θJA)
For more information www.linear .com/L TC4366 VSS Current (Regulation AMP On) vs Temperature VDD Shunt Regulator vs VDD Current VDD Shunt Regulator vs Temperature VDD Start-Up Current vs Temperature (Gate High) OUT Shunt Regulator vs OUT Current OUT Shunt Regulator vs Temperature IVDD (mA) VZ(VDD) (V) 13.0 12.5 12.0 11.5
436612 G01
TEMPERATURE (°C) –50 VZ(VDD) (V) 13.0 11.0 500 10025–25 75
436612 G02
12.5 12.0 11.5 TEMPERATURE (°C) IVDD(STHI) (µA)
436612 G03
–50 500 10025–25 75 125 IOUT (mA) VZ(OUT) (V) 5.9 5.8 5.7 5.6 5.5
436612 G04
0 5 10 15 20 –50 500 10025–25 75 125 TEMPERATURE (°C) VZ(OUT) (V)
436612 G05
TEMPERATURE (°C) IVSS(AMP) (µA)
436612 G10
–50 500 10025–25 75 125 TYPICAL PERFORMANCE CHARACTERISTICS VSS Current (Charge Pump On) vs Temperature Gate Drive vs Gate Pull-Up Current Gate Current (Charge Pump On) vs Temperature IGATE(CP) (µA) –40 –30 –20 –10
436612 G14
TEMPERATURE (°C) –50 500 10025–25 75 125 TEMPERATURE (°C) IVSS(CP) (µA) –300 –200 –100
436612 G11
–50 500 10025–25 75 125 IGATE (µA) ∆VGATE (V) –10 –20
436612 G12
–30
For more information www.linear .com/L TC4366 TYPICAL PERFORMANCE CHARACTERISTICS Gate Start-Up Current vs Temperature IGATE(ST) (µA) –12 –10
436612 G15
TEMPERATURE (°C) –50 500 10025–25 75 125 Base Shunt Regulator vs Base Current Timer Pull-Up Current vs Temperature ITIMER(UP) (µA) –12 –10
436612 G18
TEMPERATURE (°C) –50 500 10025–25 75 125 IBASE (µA) VZ(BASE) (V) 7.0 6.5 6.0 5.5 –100
436612 G16
–200 –300 –400 –500 SD Pull-Up Current vs Temperature TEMPERATURE (°C) ISD (µA)
436612 G21
–50 500 10025–25 75 125 FB Regulation Threshold vs Temperature Cool-Down Time vs Temperature VFB(REG) (V) 1.24 1.23 1.22 1.21
436612 G22
TEMPERATURE (°C) –50 500 10025–25 75 125 TEMPERATURE (°C) tD(COOL) (s)
436612 G23
–50 500 10025–25 75 125
For more information www.linear .com/L TC4366 PIN FUNCTIONS BASE: Base Driver Output for External PNP Shunt Regula- tor. This pin is connected to the anode of an internal 6.2V Zener with the cathode tied to OUT. In cases where lower Zener (Z3) clamp current is desired but a large V SS resis- tor is prohibited, connect an external PNP base to this pin (PNP collector is grounded, emitter is tied to VSS). Tie this pin to VSS if unused. Exposed Pad: The exposed pad may be left open or con- nected to VSS. FB: Overvoltage Regulation Amplifier Feedback Input. Connect this pin to an external resistive divider from OUT to ground. The overvoltage regulation amplifier controls the gate of the external N-channel MOSFET to regulate the FB pin voltage at 1.23V below OUT. The overvoltage amplifier will activate a 200mA pull-down on the GATE pin during a fast overvoltage event. GATE: Gate Drive for External N-Channel MOSFET . Dur- ing start-up an internal 7.5µA current source charges the gate of the external N-channel MOSFET from the V DD pin. Once the OUT voltage is above VSS by 4.75V, the charge pump will finish charging the GATE to 12V above OUT . During a fast overvoltage event, a 200mA pull-down cur- rent source between GATE and OUT is activated, followed by regulation of the GATE pin voltage by the overvoltage regulation amplifier. OUT: Charge Pump and Overvoltage Regulation Amplifier Supply Voltage. Supply input for floating circuitry powered from the MOSFET source. Once the OUT voltage is 4.75V (UVLO2) above V SS, the charge pump will turn on and draw power from this pin. When OUT exceeds 2.55V (UVLO1) it is used as a power supply and reference input for over- voltage regulation amplifier. This pin is clamped at 5.7 V and requires a 0.22µF or greater bypass to the VSS pin. SD: Shutdown Comparator Input . Tie to V DD if unused . Connect pin to a limited current pull down created by adding a resistor in series with an open-drain or open-collector pull-down transistor. Activating the external pull down overcomes the internal 1.6µA pull-up current source and allows the SD pin to cross the shutdown threshold. This threshold is defined as 1.5V below V DD with a 280mV hysteresis. To prevent false triggers this pin must stay below the threshold for 700µs to activate the shutdown state. The shutdown state lowers the total quiescent cur- rent (I VDD plus IOUT) below 20µA. This quiescent current does not include shunt current in the VDD, OUT and BASE regulators. After a fault on the LTC4366, putting the part in shutdown will clear the fault and allow operation to resume. Clearing the fault during the 9-second cool-down period will shorten the timeout for the LTC4366-2 (auto- retry) version. TIMER: Timer Input. Leave this pin open for a 1µs overvolt- age regulation period before fault off. Connect a capacitor between this pin and VSS to set a 311ms/µF duration for overvoltage regulation before the switch is turned off . The LTC4366-2 version will restart after a nine second cool-down period. VDD: Start-Up Supply. Supply input for 7.5µA start-up cur- rent source that charges the gate of the external N-channel MOSFET. Also provides supply for timer and logic circuits active when the external MOSFET is off. This pin is clamped at 12 V above VSS. Do not bypass this pin with a capacitor. VSS: Device Return and Substrate. The capacitors on the TIMER and OUT pins should be returned to this pin.
For more information www.linear .com/L TC4366 SIMPLIFIED DIAGRAM FUNCTIONAL DIAGRAM RFB1 RFB2
436612 SDRSSRSSRSS
7.5µA 20µA Z3 5.7V 5.7V RIN 1.23V +– CHARGE PUMP f = 2MHz UVLO2 4.75V OUT FB GATE OUTVDD SD D17.5µA 20µA OVERVOL TAGE AMPLIFIER LOGIC SUPPL Y VCC OUT 12V LOGIC AND TIMER SHUTDOWN COMPARATOR TIMER COMPARATOR UVLO1 2.55V 6.2V 5.7V 12V 2.8V VCC VCC VDD 9µA TIMER BASE VSS 1.8µA 1.6µA CG VOUT CT RFB1 RGRIN VIN RFB2 RSS 436612 FD 1.5V+– 1.23V +– Start Run Regulate
For more information www.linear .com/L TC4366 OPERATION The Simplified Diagram shows three states of operation: the start, run and regulate mode. Previous surge stopper parts are powered off the input supply, therefore the surge voltage is limited to the breakdown voltage of the input pins of the part. As demonstrated in run and regulate modes, the majority of this part is powered off the output, so the MOSFET isolates the surge from the power pins of the part. This allows surge voltages up to the breakdown of the external MOSFET. In the start mode a 15µA trickle current flows through R IN, half is used to charge the gate with the other half used as bias current. As the GATE pin charges, the external MOSFET brings up the OUT pin. This leads to the run mode where the output is high enough to become a supply voltage for the charge pump. The charge pump is then used to fully charge the gate 12V above the source. With the output voltage equal to the input voltage, it is necessary to protect the load from an input supply over- voltage. In the regulate mode, the overvoltage regulation amplifier is referenced to the output through a 1.23V reference. If the voltage drop across the upper feedback resistor, R FB1, exceeds 1.23V the regulation amplifier pulls the gate down to regulate the RFB1 voltage back to 1.23V. Therefore, the output voltage is clamped by setting the proper ratio between R FB1 and RFB2. For example, if the output voltage is regulated at 100V then the voltage drop across the RFB2 is 98.77V. If the Zener Z3 is 5.7V then the voltage drop across RSS is 94.3V. There- fore, when the output is at a high voltage, the majority of the voltage is dropped across the two resistors RFB2 and RSS. This demonstrates how the LTC4366 floats up with the supply. The adjustable 3-terminal regulators , such as the L T®1085 and LM117, are also based on this idea. The Functional Diagram shows the actual circuits . An external RIN resistor on the V DD pin powers up the 12V shunt regulator which then powers up logic supply, VCC. After verifying that the shutdown input is not active , the GATE pin is charged with a 7.5µA current from VDD. This is the start mode. Once the OUT to V SS voltage exceeds the 2.55V UVLO1 threshold, the overvoltage amplifier is enabled. Next, the UVLO2 threshold of 4.75V is crossed and the charge pump turns on. The charge pump charges the GATE pin with 20µA to its final value 12V above OUT (clamped by Z 4). This allows the capacitor between OUT and V SS to charge until clamped by Z3 to 5.7V. In this run mode the MOSFET is configured as a low resistance pass transistor with little voltage drop and power dissipation in the MOSFET. The powered up LTC4366 is now ready to protect the load against an overvoltage transient. The overvoltage regula- tion amplifier monitors the load voltage between OUT and ground by sensing the voltage on the FB pin with respect to the OUT pin (drop across R FB1). In an overvoltage condition the OUT rises until the amplifier drives the M1 gate to regulate and limit the output voltage . This is the regulate mode. During regulation the excess voltage is dropped across the MOSFET. To prevent overheating the MOSFET, the LTC4366 limits the overvoltage regulation time using the TIMER pin. The TIMER pin is charged with 9µA until the pin exceeds 2.8V. At that point an overvoltage fault is set, the MOSFET is turned off, and the part enters a cool-down period of 9 seconds. The logic and timer block are active during cool down while the GATE pin is pulled to OUT. The latched-off version, LTC4366-1, will remain in fault until the SD pin is toggled low and then high. Once the fault is cleared, the GATE is permitted to turn the MOSFET on again. The auto-retry version, LTC4366-2, waits 9 seconds then clears the fault and restarts.
generate internal supply rails at the V DD and OUT pins . voltage rating of the LTC4366’s internal circuitry. OUT pins to be pulled to ground by output load and RSS. SS and finally the RIN current. greatly exceeds the typical OUT (160µA) bias current. MOSFET, M1, is allowed to turn on. charge pump current exceeds the C 1 charging current . pause allowing C1 to recharge.
436612 F01
Figure 1. Typical Application Figure 2. Turn-On Waveforms
For more information www.linear .com/L TC4366 APPLICATIONS INFORMATION Starting up with a supply voltage insufficient to charge C1 with large load current may result in overheating the MOSFET and subsequent damage . While the gate and output are ramping the drop across the MOSFET is the input supply minus the output. If the supply is lower than necessary to charge C1, then the output fails to ramp higher than the supply minus the threshold of the MOSFET. This 3V to 5V MOSFET drop with high load current will result in power dissipation without any protection or timeout limit. Overvoltage Fault The LTC4366 prevents an overvoltage on the input supply from reaching the load. Normally, the pass transistor is fully on, powering the load with very little voltage drop. As the input voltage increases the OUT voltage increases until it reaches the regulation point (V REG). From that point any further voltage increase is dropped across the MOSFET . Note the MOSFET is still on so the LTC4366 allows un- interrupted operation during a short overvoltage event. The VREG point is configured with the two FB resistors, RFB1 and RFB2. The regulation amplifier compares the FB pin to a threshold 1.23V below the OUT pin . During regulation the drop across RFB1 is 1.23V, while the remainder of the VREG voltage is dropped across RFB2. When the output is at the regulation point a timer is started to prevent excessive power dissipation in the MOSFET . Normally the TIMER pin is held low with a 1.8µA pull- down current. During regulation the TIMER pin charges with 9µA. If the regulation point is held long enough for the TIMER pin to reach 2.8V then an overvoltage fault is latched. The equation for setting the timer capacitor is: CT = 3.2 • t nF / ms[ ] Depending on which version, the part will cool down and self start (LTC4366-2), or remain latched off until the SD pin activates a shutdown followed by a start-up command (LTC4366-1). The cool-down time is typically nine seconds which provides a very low pulsed power duty cycle. Starting up with an input supply overvoltage and full load current does increase the power dissipation in the MOSFET well beyond the case for an overvoltage surge. During the gate and output ramp up , the partial supply voltage (at full current) is dropped across the MOSFET . After start-up the normal overvoltage surge (with timeout) occurs before the shutting off the MOSFET . The Design Example section only considers the normal overvoltage surge for safe operating area (SOA) calculations for the MOSFET. Start-up into overvoltage will require additional SOA considerations. Shutdown The LTC4366 has a low current (<20µA) shutdown state that turns off the pass FET by tying the GATE and OUT pins together with a switched resistor. In the normal operating condition, the SD pin is pulled up to the V DD pin voltage with a 1.6µA current source. Tie the SD pin to VDD when the shutdown state is not used. Bringing the SD pin more than 1.5V below VDD pin volt- age for greater than the 700µs filter time activates the shutdown state. This filter time prevents unwanted activa- tion of shutdown during transients . The SD pin is diode clamped 0.7V below VSS which requires current limiting (maximum 10mA) on the pull-down device. One way to limit the current is to connect an external 470k resistor in series with the open-collector pull-down device. Activat- ing the external pull-down overcomes the internal 1.6µA pull-up current source and allows the SD pin to cross the shutdown threshold.
series with CG with a bypass diode as shown in Figure 3. during an supply overvoltage.
436612 F03
Figure 3. Output Short Protection
436612 F04
Figure 4. External PNP Option lowers the power and size requirements for this resistor. be used in conjunction with a PNP as shown in Figure 4.
pin, and finally the current from the VSS pin (see Figure 5). the necessary V C1 voltage to turn the charge pump on . in the Maximum Supply Start-Up section. voltage from VDD to VSS is subtracted from the supply.
- V IN(MAX) – VZ(VDD)( ) As VIN increases the VSS(MATCH) voltage increases. If the match voltage exceeds the overvoltage regulation point (VREG), then load is unprotected. This is true because C1 will still need to charge to 2.55V while V SS already M1GATE D17.5µA CG VDD RINIRIN VIN 5.7V 12V I BIASISHUNT29µAISHUNT1 IC1 IRSS VOUTOUT RLOAD
436612 F05
Figure 5. Simplified Block Diagram
For more information www.linear .com/L TC4366 APPLICATIONS INFORMATION has exceeded VREG. Since the OUT pin voltage is at least 2.55V larger than VSS it exceeds the specified maximum. Choosing the match point (with supply at the maximum) sufficiently below VREG (by at least 2.55V), allows C1 to charge up in time to protect the load from overvoltage . In reality having VSS pin voltage 7V below VREG provides required margin for charging C1. VSS(MATCH)(MAX) = VREG – 7V Increasing RSS increases the match point , so determin- ing the maximum R SS value while still protecting from overvoltage is useful. Using IRIN = IRSS: RSS = RIN • VRSS VRIN Using: VRSS = VSS(MATCH)(MAX) = VREG – 7V VRIN = VIN – VZ(VDD) – VRSS Substituting: RSS(MAX) = RIN • V REG – 7V( ) VIN(MAX) – 12V – VREG – 7V( ) RSS(MAX) = RIN • V REG – 7V( ) VIN(MAX) – 5V – VREG If we guarantee that R SS < RSS(MAX) then the following is true: VSS(MATCH) < VSS(MATCH)(MAX) C1 bypasses the charge pump , and requires at least a 0.22µF. The size of C1 needs limits also. The gate capaci- tor (CG) dictates the maximum output capacitor C1(MAX) that will charge to the 2.55V UVLO1 threshold (VUVLO1) before the OUT voltage exceeds the overvoltage threshold. C1(MAX ) = –C G • R SS +RIN( ) VREG – VSS(MATCH )( ) IG •RSS •RIN •In 1– 2 • VUVLO1 VREG – VSS(MATCH ) In most cases: C1(MAX) = 10 • CG to 100 • CG GATE Capacitor, CG The gate capacitor is used for three functions. First, C G absorbs charge from the gate-to-drain capacitance of the MOSFET during overvoltage transients . Second, the capacitor also acts as a compensation element for the overvoltage regulation amplifier. The minimum value for C G to guarantee stability is 2nF. Finally, CG sets the slew rate of the GATE and OUT pins. The voltage at the GATE pin rises at a slope equal to 20µA/CG. This slope determines the charging current into the load capacitor. IINRUSH = CLOAD CG
- IG The voltage rating for CG must be greater than the regula- tion voltage (VREG). MOSFET Selection The LTC4366 drives an N-channel MOSFET to conduct the load current. The important features of the MOSFET are on-resistance, R DS(ON), the maximum drain-source voltage, V(BR)DSS, the threshold voltage, and the SOA. The maximum allowable drain-source voltage must be higher than the supply voltage. If the output is shorted to ground or during an overvoltage event, the full supply voltage will appear across the MOSFET. The threshold voltage of the MOSFET is used in the mini- mum supply start-up calculation. For applications with supplies less than 12V, a logic-level MOSFET is required. Above 12V a standard threshold N-channel MOSFET is sufficient. The SOA of the MOSFET must encompass all fault condi- tions. In normal operation the pass transistor is fully on, dissipating very little power. But during overvoltage faults, the GATE pin is servoed to regulate the output voltage through the MOSFET. Large current and high voltage drop across the MOSFET can coexist in these cases. The SOA curves of the MOSFET must be considered carefully along with the selection of the fault timer capacitor.
pins, these pins are susceptible to leakages to ground . rent will interrupt system operation. in this example are summarized in Table 1.
436612 F06
Figure 6. Overvoltage Protected 28V, 1.5A Supply
lockout 2 threshold (VUVLO2) which starts the charge pump. Table 1. Electrical Parameters Used in Design Example pin when IRIN = IRSS is called the match point (VSS(MATCH)). and the solution is acceptable.
For more information www.linear .com/L TC4366 Step 5: Determine CG, C1(MAX), Check RSS The gate capacitor (CG) determines the gate slew rate and therefore the slew rate of the OUT pin since the output voltage follows the GATE pin. The voltage at the GATE pin rises with a slope equal to 7.5µA/C G at startup and 20µA/CG when the charge pump is on. Limiting this slope will limit the inrush current charging the load capacitance where: IINRUSH = CLOAD CG
- IG In this example we choose CG to be 10nF which limits the inrush current to be 660mA for a 330µF CLOAD. C1 is used as a bypass capacitor for the circuitry between the OUT and V SS pins. C1 also stabilizes the shunt regula- tor that clamps the voltage between these pins where the minimum value for regulator stability is 0.22µF. An even greater 0.47µF value is desired for C1 to protect the OUT to V SS circuitry from transients on the OUT pin. The startup into an overvoltage creates an upper bound- ary on the value of C1. The value of C G, RSS and R VIN determines a maximum C 1 that will reach UVLO 1 and power the regulation amplifier before the OUT pin voltage exceeds the overvoltage threshold . If our desired value for C1 (0.47µF) exceeds the maximum allowed C 1 then a smaller R SS must be used to iterate a new solution for C1(MAX). We start with calculating VSS(MATCH): VSS(MATCH) = RSS RSS +RVIN
- V IN – VZ(VDD)( ) If we use the worst-case 1% maximum value for R SS (51.6k) and minimum value for RVIN (291k): VSS(MATCH) = 35.8V C1(MAX) = –CG • R SS +RIN( ) VREG – VSS(MATCH)( ) IG •RSS •RIN •In 1– 2 • VUVLO1 VREG – VSS(MATCH) Use the worst-case maximum gate current of 11µA instead of the typical 7.5µA and the worst-case minimum UVLO1 APPLICATIONS INFORMATION threshold, 2.75V: 11 µA • 51.6k • 291k •In 1– 2 • 2.75V 43V − 35.8V or C1(MAX) = 0.1µF This limit on C1 does not meet the shunt regulator stability requirements (C1 > 0.22µF). If we desire a larger value of C1 then a lower size of RSS is required. A lower value for R SS is 48.7k, which calls out an RIN value of 309k and a max C 1 value of 0.27µF. The next lower value of 46.4k with RVIN of 324k, results in the worst-case maximum C1 value of 0.49µF. A larger C1 increases circuit immunity to transients in exchange for slightly higher current. Therefore, a selection of com- ponents that allow a 0.47µF C1 is recommended. The lowered R SS value of 46.4k now considers the toler- ances of all the components that set the C1 ramp rate to guarantee it charges to the 2.55V UVLO1 threshold before the OUT voltage exceeds the overvoltage threshold. Step 6: Determine RFB1, RFB2 The feedback resistors, R FB1 and R FB2, are chosen to regulate the overvoltage at 43V. One way to quickly choose these resistors is to assign 100µA or 1.2V across a 12.4k RFB1. RFB2 would need to drop the remainder of the regu- lated voltage. Dividing this remainder by 100µA yields the value for RFB2. In this example R FB2 drops 41.8V. When divided by 100µA it results in a 422k value. Step 7: Determine C T, R1 During an overvoltage the power dissipated in the MOSFET is dependent on the load current and the difference be - tween the supply and regulated voltages. It is necessary to keep the device power in a safe range . In the power MOSFET data sheets there is a maximum safe operating curve displaying current versus drain to source voltage for a fixed pulsed time. Other pulsed time data from DC to 10µs are plotted on the one graph. The different lines of operation generally follow a constant power squared
436612 F07
Figure 7. Rectified 110V AC Supply Protected from 220V AC a 6400W2s P2t for a 10ms single pulse. for R1. Resistor R2 provides ESD protection for Q1’s base. self-oscillation. The recommended value for RG is 10Ω. below the 640W2s specified for this MOSFET.
protection when up to –250V DC is present at the input. base breakdown of Q2 when the input is powering up. from R6 (via D4) develops a forward diode drop on R5.
436612 F08
Figure 8. 28V Vehicle Application with Reverse Voltage Protection
For more information www.linear .com/L TC4366 PACKAGE DESCRIPTION Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. 1.50 – 1.75 (NOTE 4)2.80 BSC 0.22 – 0.36
8 PLCS (NOTE 3)
DATUM ‘A’ 0.09 – 0.20 (NOTE 3) TS8 TSOT-23 0710 REV A
2.90 BSC
(NOTE 4)
0.65 BSC
1.95 BSC
0.80 – 0.90
1.00 MAX
0.01 – 0.100.20 BSC 0.30 – 0.50 REF PIN ONE ID NOTE: 1. DIMENSIONS ARE IN MILLIMETERS 2. DRAWING NOT TO SCALE 3. DIMENSIONS ARE INCLUSIVE OF PLATING 4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR 5. MOLD FLASH SHALL NOT EXCEED 0.254mm 6. JEDEC PACKAGE REFERENCE IS MO-193
3.85 MAX
0.40 MAX 0.65 REF RECOMMENDED SOLDER PAD LAYOUT PER IPC CALCULATOR 1.4 MIN2.62 REF
1.22 REF
(Reference LTC DWG # 05-08-1637 Rev A)
For more information www.linear .com/L TC4366 PACKAGE DESCRIPTION Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. 2.00 ±0.10 (2 SIDES) NOTE: 1. DRAWING CONFORMS TO VERSION (WECD-1) IN JEDEC PACKAGE OUTLINE M0-229 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 0.40 ±0.10 BOTTOM VIEW—EXPOSED PAD 0.56 ±0.05 (2 SIDES) 0.75 ±0.05 R = 0.115 TYPR = 0.05 TYP 2.15 ±0.05 (2 SIDES) 3.00 ±0.10 (2 SIDES) PIN 1 BAR TOP MARK (SEE NOTE 6)
0.200 REF
0 – 0.05 (DDB8) DFN 0905 REV B 0.25 ±0.05
0.50 BSC
R = 0.20 OR 0.25 × 45° CHAMFER 0.25 ±0.05 2.20 ±0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 0.61 ±0.05 (2 SIDES) 1.15 ±0.05 0.70 ±0.05 2.55 ±0.05 PACKAGE OUTLINE 8-Lead Plastic DFN (3mm × 2mm) (Reference LTC DWG # 05-08-1702 Rev B)
For more information www.linear .com/L TC4366 Information furnished by Linear Technology Corporation is believed to be accurate and reliable . However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER A 1/12 Added Patents Pending statement Revised Figure 4 in Applications Information section B 2/12 Removed reference to overcurrent faults under MOSFET Selection Fixed orientation of M2 in Figure 8 C 8/12 Updated Shutdown current from <20µA to <14µA Changed MOSFET part number and Gate Capacitor value used in the Typical Application Added MP-grade order information and specifications Added negative sign to graphs G12 x-axis and G18, G21 y-axis Changed MOSFET part number in Figure 1 and Figure 6 Added section GATE Capacitor, C G Changed ILOAD current from 5A to 3A in Design Example Updated C1(MAX) values in Step 5 calculations to 0.27µF and worst case 0.49µF Updated calculated values in Step 7, added supporting text Changed MOSFET part number and GATE capacitor used in Figure 7 2, 3, 4, 5 6, 7 11, 16 D 8/13 Simplified Diagram: Corrected amplifier’s input polarity in Regulate Diagram Functional Diagram: Added switch in series with TIMER pull-down current E 8/15 Clarified “Ambient” on Operating Temperature Range; raised T JMAX to 150°C TIMER Pin Function: Changed 278ms/µF to 311ms/µF Figures 1, 6, 8: Changed C T to 8.2nF from 10nF In CT equation, changed constant to 3.2 from 3.5; updated CT calculation 11, 16, 20 12, 19
For more information www.linear .com/L TC4366 LINEAR TECHNOLOGY CORPORATION 2011 LT 0815 REV E • PRINTED IN USA Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear .com/L TC4366 TYPICAL APPLICATION Surge Protected Automotive 12V Supply VDD SD 470k 100k OUT CG 2nF GATE HUF76639S3S SD FB CT 3.3nF 0.47µF RFB1 12.4k VOUT (18V CLAMP) VIN 12V (9V TO 100V) RFB2 169k
436612 TA02
1.91k RG 10/uni03A9 RIN 29.4k MMBT3904 L TC4366-2 TIMER BASEV SS RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1696 Overvoltage Protection Controller ThinSOT™ Package, 2.7V to 28V LTC2909 T riple/Dual Inputs UV/OV Negative Monitor Pin Selectable Input Polarity Allows Negative and OV Monitoring LTC2912/LTC2913 Single/Dual UV/OV Voltage Monitor Ads UV and OV T rip Values, ±1.5% Threshold Accuracy LTC2914 Quad UV/OV Monitor For Positive and Negative Supplies LTC3827/LTC3827-1 Low IQ, Dual, Synchronous Controller 4V ≤ VIN ≤ 36V, 0.8V ≤ VOUT ≤ 10V, 80µA Quiescent Current LTC3835/LTC3835-1 Low IQ, Synchronous Step-Down Controller Single Channel LTC3827/LTC3827-1 LT3845 Low IQ, Synchronous Step-Down Controller 4V ≤ VIN ≤ 60V, 1.23V ≤ VOUT ≤ 36V, 120µA Quiescent Current LTC3850 Dual, 550kHz, 2-Phase Synchronous Step-Down Controller Dual 180° Phased Controllers, VIN 4V to 24V, 97% Duty Cycle, 4mm × 4mm QFN-28, SSOP-28 Packages LTC3890 Low IQ, Dual 2-Phase, Synchronous Step-Down Controller 4V ≤ VIN ≤ 60V, 0.8V ≤ VOUT ≤ 24V, 50µA Quiescent Current LT4256 Positive 48V Hot Swap Controller with Open-Circuit Detect Foldback Current Limiting, Open-Circuit and Overcurrent Fault Output, Up to 80V Supply LTC4260 Positive High Voltage Hot Swap Controller with 8-Bit ADC and I Wide Operating Range 8.5V to 80V LTC4352 Ideal MOSFET ORing Diode External N-Channel MOSFETs Replace ORing Diodes, 0V to 18V LTC4354 Negative Voltage Diode-OR Controller Controls T wo N-Channel MOSFETs, 1.2µs Turn-Off, –80V Operation LTC4355 Positive Voltage Diode-OR Controller Controls T wo N-Channel MOSFETs, 0.4µs Turn-Off, 80V Operation LT4363 High Voltage Surge Stopper 100V Overvoltage and Overcurrent Protection, Latch-Off and Auto-Retry Options LTC4365 Window Passer – OV, UV and Reverse Supply Protection Controller 2.5V to 34V Operation, Protects 60V to –40V