LT3840

Linear Technology

Hybrid Step-Down Synchronous Controller

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Rev AFor more information www.analog.com TYPICAL APPLICATION

FEATURES

APPLICATIONS

DESCRIPTION

Efficiency at Various VIN for VOUT = 12V All registered trademarks and trademarks are the property of their respective owners. Protected by U.S. patents, Including 9484799. n Wide VIN Range: 10V to 72V (80V ABS Max) n Soft Switching for Low Noise Operation n Phase-Lockable Fixed Frequency 200kHz to 1.5MHz n ±1% Output Voltage Accuracy n RSENSE or DCR Current Sensing n Programmable CCM, DCM, or Burst Mode® Operation n CLKOUT Pin for Multiphase Operation n Short Circuit Protected n EXTVCC Input for Improved Efficiency n Monotonic Output Voltage Start-Up n Optional External Reference n 32-Pin (5mm × 5mm) QFN n Intermediate Bus Converters n High Current Distributed Power Systems n Telecom, Datacom, and Storage Systems n Automotive Applications The LT C®7821 uses a proprietary architecture that merges a soft switching charge pump topology with a synchro - nous step-down converter to provide superior efficiency and EMI performance compared to traditional switching architectures. In a typical 48V to 12V application, efficiency of greater than 97% is attainable with the LTC7821 switching at 500kHz. The same efficiency can only be achieved with a traditional controller switching at one-third the frequency. Higher switching frequencies allow the use of smaller in- ductances that yield faster transient response and smaller solution size. The LTC7821 can be easily paralleled to provide higher output currents with its accurate current sharing capability and frequency synchronization function. 2µH CF LY 10µF CB1, 0.22µF CB2 0.47µF CB3 1µF 4.7µF CIN 100µF 100/uni03A9 1µF 10k 10k COUT 150µF 0.1µF 10µF 6.81k 0.22µF VIN_SENSE VIN PINS NOT SHOWN IN THIS CIRCUIT : CLKOUT TEMP RUN HYS_PRGM MODE/PLLIN TRACK/SS M1: BSZ070N08LSS M2, M3: BSC032N04LS M4: BSC014N04LSI TIMER FREQ EXT_REF FAUL T PGOOD ITH EXTVCC VFB ISNS+ ISNS– PGND INTVCC BG2 SW3 BOOST3 TG2 MID_SENSE MID BOOST2 BG1 SW1 BOOST1 L TC7821

7821 TA01a

60.4k 4.32k CMID 10µF 2.2µF f SW = 500KHz V OUT = 12V CCM I OUT = 20A I OUT = 10A INPUT VOL TAGE (V) 100 EFFICIENCY (%)

7821 TA01b

Rev A For more information www.analog.com PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS Top Side Driver Voltages 3V to 86V Switch Voltages 80V 3V to 40V V to 40V (BOOST1-SW1), (BOOST2-MID), EX 3V to INTVCC Operating Junction Temperature Range C to 150°C (Note 1) SGND 31 30 29 28 27 26 25 9 10 11 12 TOP VIEW UH PACKAGE 32-LEAD (5mm × 5mm) PLASTIC QFN TJMAX = 125°C, θJA = 44°C/W , θJC = 7.3°C/W EXPOSED PAD (PIN 33) IS GND, MUST BE SOLDERED TO PCB 13 14 15 16 MODE/PLLIN CLKOUT RUN FAUL T PGOOD TIMER TRACK/SS EXT_REF BG1 BOOST2 BOOST3 TG2 SW3 INTV CC BG2 PGND NC BOOST1 TG1 SW1 V IN VIN_SENSE MID_SENSE MID HYS_PRGM I TH FREQ TEMP VFB ISNS– ISNS+ EXTVCC LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC7821EUH#PBF LTC7821EUH#TRPBF 7821 32-Lead (5mm × 5mm) Plastic QFN –40°C to 125°C LTC7821IUH#PBF LTC7821IUH#TRPBF 7821 32-Lead (5mm × 5mm) Plastic QFN –40°C to 125°C Consult L TC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container . For more information on lead free part marking, go to: http://www.linear .com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix. ORDER INFORMATIONhttp://www.linear .com/product/LTC7821#orderinfo

Rev AFor more information www.analog.com PIN CONFIGURATION ELECTRICAL CHARACTERISTICS SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Main Control Loops VIN Input Voltage Range 10 72 V Output Voltage Range (Note 4) 0.9 VIN – 2.5 V VFB Regulated Feedback Voltage ITH Voltage (Note 5) l 0.792 0.8 0.808 V IFB Feedback Current (Note 5) ±10 ±50 nA VREFLNREG Reference Voltage Line Regulation VIN = 36V to 72V (Note 5) 0.003 0.02 %/V VLOADREG Output Voltage Load Regulation (Note 5) ΔITH Voltage = 1.2V to 0.7V ΔITH Voltage = 1.2V to 1.6V l l 0.016 –0.016 0.1 –0.1 gm T ransconductance Amplifier gm ITH = 1.2V; Sink/Source 5µA (Note 5) 2 mmho IVIN Input DC Supply Current Normal Mode Shutdown Precharging Phase (Note 6) V RUN = 0V, EXTVCC = 0V VIN = 20V, VMID = VMID_SENSE = 9V, VSW1 = 15V, VSW3 = 10V VIN = 48V, VMID = VMID_SENSE = 20V, VSW1 ≥ 36V, VSW3 = 12V 0.5 240 mA µA mA mA IVIN_SENSE Input DC Supply Current Normal Mode Shutdown (Note 6) V RUN = 0V mA µA IEXTVCC Input DC Supply Current (Note 6) 2.2 mA IMID MID Pin Current 45 μA IMID_SENSE MID_SENSE Pin Current 4 μA VUVLO VIN Undervoltage Lockout VIN Ramping Up l 8.8 9.4 V VUVLO_HYST UVLO Hysteresis 0.28 V VSENSE Current Sense Threshold VISNS– = 0V l 45 50 55 mV ISNS+/- ISNS + and ISNS– Pin Current VISNS+ = VISNS– = 12V l 1.2 μA ITRACK/SS Soft-Start Charge Current VTRACK/SS = 0V –9 –10 –11 μA VRUN_ON RUN Pin On Threshold VRUN Rising l 1.1 1.3 1.6 V IRUN RUN Pin Current VRUN = 0V 1 μA VRUN_HYST RUN Pin Hysteresis 0.1 V VEXT_REF_UC EXT_REF Upper Clamp Limit (Note 5) l 0.85 0.9 V VEXT_REF_LC EXT_REF Lower Clamp Limit (Note 5) l 0.40 0.45 V VSEL_EXT_REF EXT_REF De-Select Threshold (Ramping Up) 1.3 V IEXT_REF EXT_REF Pin Current VEXT_REF = 0.6V –150 nA VTEMP_TRIP TEMP Pin T rip Point, Rising l 1.22 1.25 V VTEMP_TRIP_HYST TEMP Pin T rip Point Hysteresis 100 mV ITEMP TEMP Pin Current VTEMP = 1V 1 nA VBSTUVLO Undervoltage Lockout of (BOOST1-SW1), (BOOST2- V MID) and (BOOST3-SW3) Difference Voltage, Rising 4.4 V VBSTUVLO_HYST Bootstrap Undervoltage Lockout Hysteresis 1.4 V TOUT TEMP T rip TimeOut 100 ms The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = VIN_SENSE = 48V, VRUN = 5V, EXTVCC = 9V, EXT_REF = 5.6V unless otherwise noted.

Rev AFor more information www.analog.com ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = VIN_SENSE = 48V, VRUN = 5V, EXTVCC = 9V, EXT_REF = 5.6V unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS IFLYSRC1 Current Out of SW1 During Capacitor Balancing (VSW1 – VSW3) < VIN/2, VSW3 = 12V 40 mA IFLYSNK1 Current into SW1 During Capacitor Balancing (V SW1 – VSW3) > VIN/2, VSW3 = 12V 6 mA IFLYSNK3 Current into SW3 During Capacitor Balancing (V SW1 – VSW3) < VIN/2, VSW3 = 12V 40 mA IFLYSRC3 Current Out of SW3 During Capacitor Balancing SW1 – VSW3) < VIN/2, VSW3 = 12V 6 mA IMID_SRC Current Out of MID During Capacitor Balancing V MID < VIN/2, VMID = VMID_SENSE = 20V VSW1 ≥ 36V, VSW3 = 12V 60 mA IMID_SNK Current into MID During Capacitor Balancing V MID > VIN/2, VMID = VMID_SENSE = 28V VSW1 ≥ 36V, VSW3 = 12V 40 mA Gate Driver TG1,2 Pull-Up ON Resistance Pull-Down ON Resistance Ω Ω BG1, 2 Pull-Up ON Resistance Pull-Down ON Resistance Ω Ω TG1,2 t r TG1,2 tf TG1, TG2 Transition Time: Rise Time Fall Time (Note 7) ns ns BG1,2 t r BG1,2 tf BG1, BG2 Transition Time: Rise Time Fall Time (Note 7) ns ns T 1D TG1 Off to BG1 On 45 ns T2D TG2 Off to BG2 On 20 ns T3D TG1 Off to TG2 Off 25 ns T4D BG1 Off to TG1 On 40 ns T5D BG2 Off to TG2 On 20 ns T6D BG1 Off to BG2 Off 20 ns ton(MIN) Minimum On-Time (Note 8) 210 ns Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTC7821E is guaranteed to meet performance specifications from 0°C to 85°C. Specifications over the –40°C to 125°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LTC7821I is guaranteed to meet performance specifications over the full –40°C to 125°C operating junction temperature range. Note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. Note 3: T J is calculated from the ambient temperature TA and power dissipation PD according to the following formulas: LTC7821UH: TJ = TA + (PD • 44°C/W) Note 4: Output voltage range is guaranteed by design. For output voltage setting, read “Output Voltage Setting” and “Minimum VOUT” in the “Applications Information” section. Note 5: The LTC7821 is tested in a feedback loop that servos VITH to a specified voltage and measures the resultant VFB. Note 6: Dynamic supply current is higher due to the gate charge being delivered at the switching frequency. See Applications Information. Note 7: Rise and fall times are measured using 10% and 90% levels. Delay times are measured using 50% levels. Note 8: The minimum on-time condition is specified for an inductor peak-to-peak ripple current ≥ 40% of I MAX (see Minimum On-Time Considerations in the Applications Information section) Note 9: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 125°C when overtemperature protection is active. Continuous operation above the specified maximum junction temperature may impair device reliability or permanently damage the device.

Rev A For more information www.analog.com TYPICAL PERFORMANCE CHARACTERISTICS Efficiency and Power Loss In Different Modes vs Load Current LTC7821 Start-Up Characteristic (Pre-Balancing Period) LTC7821 Start-Up Characteristic T A = 25°C, unless otherwise noted. Shutdown Current vs Temperature Quiescent Current vs Temperature Shutdown (RUN) Threshold vs Temperature Input Voltage UVLO Threshold vs Temperature HYS_PRGM, TRACK/SS and FREQ Pin Current vs Temperature CCM DCM BURST V IN = 48V V OUT = 12V fOSC = 500kHz LOAD CURRENT (A) PAGE 1 SCHEMATIC 0.1 100 100 EFFICIENCY (%) POWER LOSS (W)

7821 G01

7821 G02

7821 G03

TEMPERATURE (°C) –50 –25 100 125 150 200 250 300 350 400 I VIN (µA)

7821 G05

I VIN I VIN_SENSE TEMPERATURE (°C) –50 –25 100 125 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 SUPPL Y CURRENT (mA)

7821 G06

TEMPERATURE (°C) –50 –25 100 125 1.10 1.15 1.20 1.25 1.30 1.35 1.40 V RUN (V)

7821 G07

TEMPERATURE (°C) –50 –25 100 125 8.0 8.2 8.4 8.6 8.8 9.0 V IN (V)

7821 G08

HYS_PRGM Pin TRACK/SS Pin FREQ Pin TEMPERATURE (°C) –50 –25 100 125 9.6 9.7 9.8 9.9 10.0 10.1 10.2 10.3 PIN CURRENT (µA)

7821 G09

f SW = 500KHz V OUT = 12V CCM I OUT = 20A I OUT = 10A INPUT VOL TAGE (V) 100 EFFICIENCY (%) for VOUT = 12V

Rev AFor more information www.analog.com TYPICAL PERFORMANCE CHARACTERISTICS TIMER Pin Current vs Temperature TEMP Pin Current vs Temperature Regulated Feedback Voltage vs Temperature TA = 25°C, unless otherwise noted. Regulated Feedback Voltage vs Temperature Oscillator Frequency vs Input Voltage Oscillator Frequency vs Temperature INTV CC Line Regulation (Supply from EXTVCC) Current Sense Threshold vs I TH Voltage Switching Frequency vs Voltage at FREQ Pin V TIMER = 0V V TIMER = 2.8V TEMPERATURE (°C) –50 –25 100 125 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 I TIMER (µA)

7821 G10

V TEMP = 1V TEMPERATURE (°C) –50 –25 100 125 0.0001 0.001 0.01 0.1 I TEMP (nA)

7821 G11

EXT_REF = INTV CC TEMPERATURE (°C) –50 –25 100 125 798 799 800 801 802 803 804 V FB (mV)

7821 G12

EXT_REF = 0.6V TEMPERATURE (°C) –50 –25 100 125 599.00 599.30 599.60 599.90 600.20 600.50 V FB (mV)

7821 G13

R FREQ = 68kΩ INPUT VOL TAGE (V) 400 425 450 475 500 525 550 575 600 FREQUENCY (kHz)

7821 G14

R FREQ = 68kΩ TEMPERATURE (°C) –50 –25 100 125 100 200 300 400 500 600 700 800 OSCILLATOR FREQUENCY (kHz)

7821 G15

VOL TAGE (V) 5.00 5.25 5.50 5.75 6.00 6.25 6.50 V INTVCC (V)

7821 G17

I TH VOL TAGE (V) 0.4 0.8 1.2 1.6 –30 –20 –10 CURRENT SENSE THRESHOLD (mV)

7821 G18

FREQ PIN VOL TAGE (V) 0.5 1.5 2.5 200.0 400.0 600.0 800.0 1000.0 1200.0 1400.0 1600.0 1800.0 SWITCHING FREQUENCY (kHz)

7821 G16

Rev A For more information www.analog.com TYPICAL PERFORMANCE CHARACTERISTICS HYS_PRGM Voltage Window vs Temperature Voltage at Timer Pin to Start and Stop Capacitor Balancing vs Temperature TEMP Pin T rip Voltage vs Temperature Line T ransient 10V/ms Steady-State Output Voltage Ripple of Typical Application Load T ransient 2A–12A–2A of Typical Application Short-Circuit and Recovery TEMP Fault Characteristic T A = 25°C, unless otherwise noted. V HYS_PRGM = INTV CC V HYS_PRGM = 1.2V TEMPERATURE (°C) –50 –25 100 125 –1.5 –1.2 –0.9 –0.6 –0.3 0.0 0.3 0.6 0.9 1.2 1.5 V MID_SNS - VIN/2 (v)

7821 G20

TEMPERATURE (°C) –50 –25 100 125 0.3 0.5 0.7 0.9 1.1 1.3 1.5 V TIMER (V)

7821 G21

TEMPERATURE (°C) –50 –25 100 125 1.00 1.05 1.10 1.15 1.20 1.25 1.30 V TEMP (V)

7821 G22

V IN 10V/DIV MID 10V/DIV V OUT 100mV/DIV AC-COUPLED

7821 G23

V OUT 10V/DIV I L 20A/DIV PGOOD 5V/DIV

7821 G26

7821 G27

V IN = 48V V OUT = 12V I LOAD = 30mA 10µs/DIV CONTINUOUS MODE 100mV/DIV AC-COUPLED Burst Mode OPERATION 100mV/DIV AC-COUPLED PULSE- SKIPPING MODE 100mV/DIV AC-COUPLED

7821 G24

50µs/DIV V OUT 500mV/DIV AC-COUPLED I L 10A/DIV

7821 G25

V IN = 48V V OUT = 12V f SW = 500kHz Maximum Current Sense Threshold vs Common Mode Voltage V SENSE COMMON MODE VOL TAGE (V) 45.0 47.5 50.0 52.5 55.0 CURRENT SENSE THRESHOLD (mV)

7821 G19

Rev AFor more information www.analog.com PIN FUNCTIONS MODE/PLLIN (Pin 1): Mode Selection or External Synchro- nization Input to Phase Detector . When external synchro- nization is not used, this pin selects the operating modes and can be tied to SGND, to INTVCC or left floating. If the pin is connected to SGND, it enables forced continuous mode while a connection to INTV CC enables pulse-skipping mode. Floating the pin enables Burst Mode operation. For external sync, apply a clock signal to this pin. The integrated PLL along with its internal compensation net- work will synchronize the internal oscillator to this clock. Forced continuous mode will be enabled. CLKOUT (Pin 2) : Clock Output Pin. This pin outputs a clock 180° out of phase with the main operating clock of the LTC7821. RUN (Pin 3): Run Control Input. A voltage above 1.3V turns the controller ON. There is a 1μA pull-up current on this pin when its voltage is below 1.3V. FAUL T (Pin 4): Open Drain Output pin. When the signal goes low, it indicates one of the following conditions: (a) In the capacitor balancing phase, capacitors C F LY or CMID (see Typical Application) are not charged to VIN/2. A low FAUL T indicates an abnormal condition that is preventing CF LY or CMID from being be charged up to VIN/2. (b) During normal operation, the voltage deviates from VIN/2 by a window amount set by the voltage on the HYS_PRGM pin. (c) The die temperature exceeds its internally set limit or the PTC resistor connected as the lower leg of a resistor divider trips the TEMP pin threshold. During any of these condition, the TRACK/SS pin will also be pulled low. PGOOD (Pin 5): Power Good Pin. This is an open drain output. PGOOD is pulled to ground when the voltage of the V FB pin is not within ±7.5% of its set point after an internal 50μs mask timer expires. It will also be pulled low when FAUL T is tripped. TIMER (Pin 6): Charge Balancing Timer Input. A capaci- tor connected from this pin to ground sets the amount of time allocated to charge C F LY and CMID to VIN/2 during the capacitor balancing phase. It also sets the auto-retry timeout, should the capacitors fail to reach this voltage within the set time. Capacitors C F LY and CMID begin and end charging when the TIMER voltage is between 0.5V and 1.2V, respectively. If the capacitor is balanced before the TIMER voltage reaches 1.2V, this voltage is reset to ground and normal operation begins. However , if the bal- ance is not reached when the voltage reaches 1.2V, then the charging of the capacitors stops and the auto-retry timeout period begins. The TIMER capacitor will now slew at half the rate until it reaches 4V and then resets to zero and begins to slew at 1x rate. Once it reaches 0.5V, the CF LY and CMID begin to charge again and the process repeats. TRACK/SS (Pin 7): Output Voltage T racking and Soft-Start Input. The LTC7821 regulates the VFB voltage to the lowest of three voltages: 0.8V, the voltage on the EXT_REF pin or the voltage on the TRACK/SS pin. An internal 10μA pull- up current source is connected to this pin. A capacitor to ground at this pin sets the ramp time to the final regulated output voltage. Alternatively, a resistor divider from another voltage supply connected to this pin allows the LTC7821 output voltage to track the other supply during start-up. EXT_REF (Pin 8): External Reference Input. A voltage ap- plied to this pin forces the V FB to regulate to this voltage. Internal clamps set at 0.4V and 0.93V limit the lower and upper bounds of V FB regulation. Connecting this pin to INTVCC will cause the internal reference to be used for output voltage regulation. HYS_PRGM (Pin 9): There is a 10μA current flowing out of this pin. A voltage created by connecting a resistor from this pin to ground sets an equal amount of window threshold around V IN/2 to a window comparator . When the voltage at MIDSENSE is not within this window threshold, FAUL T will be pulled low and switching will stop. CF LY and CMID will be rebalanced to half of V IN before resuming normal operation. ITH (Pin 10): Current Control Threshold and Error Amplifier Compensation Point. The current comparator threshold increases with its ITH control voltage. FREQ (Pin 11): Frequency Set Pin. There is a 10μA current flowing out of this pin. A resistor to ground sets a voltage which in turn programs the frequency.

Rev A For more information www.analog.com TEMP (Pin 12): Temperature Sensing Input. Using a PTC resistor as the lower leg of a resistor divider , connect the TEMP pin to the common point of the divider . The PTC resistor is used to monitor a hot spot on the PCB. Once it reaches the TEMP threshold of 1.22V, the LTC7821 stops switching for 100ms before retrying. Ground this pin if not used. V FB (Pin 13): Error Amplifier Feedback Input. This pin receives the remotely sensed feedback voltage from an external resistive divider across the output. ISNS– (Pin 14): Current Sense Comparator Input. The (–) input to the current comparator is Kelvin connected to the output voltage of the controller . ISNS+ (Pin 15): Current Sense Comparator Input. The (+) input to the current comparator is normally Kelvin con - nected to the DCR sensing networks or current sensing resistor. EXT VCC (Pin 16): External Power Input to an Internal LDO Connected to INTVCC. This LDO supplies INTV CC power , bypassing the internal LDO powered from V IN whenever EXTVCC is higher than 6.4V. Do not float or exceed 40V on this pin. PGND (Pin 17): Driver Power Ground. Connect this pin closely to the source of bottom (synchronous) N-channel MOSFET M4, the (–) terminal of C IN and the (–) terminal of CVCC. BG2 (Pin 18): Gate Drive for the Bottom (synchronous) N-Channel MOSFET . The voltage swings from slightly below ground to INTV CC. INTVCC (Pin 19): Internal Regulator Output. The bottom synchronous gate driver and control circuits are powered from this regulator . Bypass this pin to PGND with a minimum of 4.7μF low ESR tantalum or ceramic capacitor . Do not use the INTV CC pin for any purpose other than described in this data sheet. SW3 (Pin 20): Switch Node Connection to Inductor and One Terminal of Flying Capacitor . Voltage swing at this pin is from slightly below ground to V IN/2. TG2 (Pin 21): Floating Gate Drive for Second Lowermost N-Channel MOSFET . The voltage swings equal to INTV CC superimposed on the switch node voltage SW3. BOOST1, BOOST2, BOOST3 (Pin 31, 23, 22): Bootstrapped Supplies to Floating Drivers. Capacitors are connected between the BOOSTx and SWx (MID) pin. Voltage swing at the BOOST1 pin is from (V IN/2 + INTVCC) to (VIN + IN- TVCC). Voltage at the BOOST2 pin is at (VIN/2 + INTVCC). Voltage swing at the BOOST3 pin is from INTVCC to (VIN/2 + INTVCC). BG1 (Pin 24): Floating Gate Drive for Second Uppermost N-Channel MOSFET . The voltage swings between (V IN/2 + INTVCC) and VIN/2. MID (Pin 25): Half Supply from V IN. Do not use this to source current. Connect a bypass capacitor from this node to PGND. MID SENSE (Pin 26): Half Supply Monitor . Provides Kelvin sensing input for the comparator that monitors the voltage between MIDSENSE and ground. An RC filter can be added from MID to this pin to filter out noise. VIN_SENSE (Pin 27): VIN Kelvin Sensing Input. Allows an internal VIN/2 to be generated for LTC7821 control circuit usage. For a cleaner supply, an RC filter can be added from VIN to this pin. VIN (Pin 28): Main Input Supply. Bypass this pin to PGND with a capacitor . SW1 (Pin 29): Switch Node Connection to One Terminal of Flying Capacitor . Voltage swing at this pin is from VIN/2 voltage to VIN. TG1 (Pin 30): Floating Gate Drive for Uppermost N-Channel MOSFET . The voltage swings equal to INTVCC superimposed on the switch node voltage SW1. SGND (Exposed Pad, Pin 33): Signal Ground. All Small- signal components and compensation components should connect to this ground, which in turn connects to PGND at one point. Exposed pad must be soldered to the PCB, providing a local ground for the control components of the IC, and be tied to the PGND pin under the IC. PIN FUNCTIONS

Rev AFor more information www.analog.com BLOCK DIAGRAM 1.2V 0.5V 3.5µA 3.5µA 10µA 0.8VREF 1.2V V/I 0.5V SLEEP 1.2V + – – –+ + RUN SS 1µA EA 10µA 51k SWITCH LOGIC AND ANTI-SHOOT THROUGH RUN MODE/SYNC DETECT S Q R OSC 0.6V 500k 500k MODE/PLLIN INTVCC ICMP IREV PLL SYNC SLOPE COMP FCNT BURSTEN BALEN BALEN FREQ CLKOUT ITH SNS– SNS+ TIMER HYS_PRGM TRACK/SS RUN EXT_REF VFB PGND MID_SENSE TEMP FAUL T EXTVCC BOOST3 TG2 SW3 BG2 BOOST1 TG1 SW1 BOOST2 BG1 MID BAL VIN/2 CAPACITOR BALANCING CIRCUIT VIN BST CAP CHARGER VIN BST CAP CHARGER VIN VIN_SENSE BST CAP CHARGER INTVCC VA VB 0.74V VC ×1.075 ×0.925 x0.825 0.86V 0.66V UV OV 6.48V 100ms TIMEOUT 1.2V VIN EXT LINEAR REG SHDN 1.2V SHDN INT LINEAR REG INTVCC PGOOD

7821 BD01

1.5M VIN/2 1.5M

up. The TIMER pin will reset to ground and remain there. Normal operation will begin (see Figure 1A). FL Y and CMID are at VIN/2(See Figure 1B). turned on to bring CF LY and CMID voltages back to VIN/2. Figure 1. Charge Balancing During Power Up with (A) Balancing Completed within One Timer Period and Figure 2. Charge Balancing During Normal Operation with (A) Balancing Completed within One Timer Period and

7821 F01

7821 F02

Rev AFor more information www.analog.com OPERATION current at which ICMP resets the RS latch is controlled by the voltage on the ITH pin, which is the output of the error amplifier EA. The V FB pin receives the voltage feedback signal, which is compared to the internal reference voltage by the EA. When the load current increases, it causes a slight decrease in V FB relative to the 0.8V reference, which in turn causes the I TH voltage to increase until the aver - age inductor current matches the new load current. After MOSFETs M1 and M3 have turned OFF , MOSFETs M2 and M4 are turned ON until either the inductor current starts to reverse, as indicated by the reverse current comparator I REV, or the beginning of the next cycle. During the switching of M1/M3 and M2/M4, capacitor CF LY is alternately connected in series with or parallel to CMID. The voltage at MID will be approximately at VIN/2. INTVCC/EXTVCC Power Power for the bootstrap drivers and bottom MOSFET and most internal circuitry is derived from the INTV CC pin. When the EXTVCC pin is grounded or tied to a voltage less than 7V, an internal 5.8V linear regulator supplies INTVCC power from VIN. If EXTVCC is taken above 7V, this linear regula- tor is turned OFF and another 5.8V linear regulator turns ON to provide the INTV CC power from EXTVCC. Using the EXTVCC pin allows the INTVCC power to be derived from a high efficiency external source, resulting in an overall increase in system efficiency. Bootstrap Capacitor Refresh Each of the three uppermost MOSFET drivers is biased from its respective floating bootstrap capacitor , CB1 to CB3, which are refreshed during switching through a charge pump configuration consisting of diodes D1 to D3 and the external MOSFETs. During the charge balancing phase or light load condition when switching may stop for extended amount of time, the voltage across the bootstrap capacitor may decrease sufficiently that the gate drive voltage is not optimal. Un- dervoltage detectors monitor the voltage across each of the bootstrap capacitors. When any of them goes below 3V, an internal current source of 1mA will be turned ON to charge that bootstrap capacitor through the upper plate of the capacitor . A 1mA sinking source that is connected to the bottom plate of the bootstrap capacitor will also be turned ON to sink away this current. This ensures a net zero residual current at the bottom plate capacitor node, hence avoiding any impact on the bias condition of that node. When CB1 and CB2/CB3 reach 4.3V and 4.47V respectively, the refreshing stops. When CB2 and CB3 need to be refreshed, all switching stops. Shutdown and Start-Up (RUN and TRACK/SS Pins) When the RUN pin is below 1.3V, the INTV CC linear regulator along with all the internal circuitry that is powered from this supply, is disabled. The main control loop will also be disabled. Releasing the RUN pin will allow the internal 1μA current source to pull this pin up, thus enabling the part. The RUN pin can also be driven directly by logic but ensure that this voltage does not exceed the Absolute Maximum Rating of 6V. The slew rate of the output voltage V OUT can be controlled by the voltage on the TRACK/SS pin. When the voltage on the TRACK/SS is less than the internal reference of 0.8V (or EXT_REF if this feature is invoked), the LTC7821 regulates the V FB voltage to the TRACK/SS voltage instead of to the reference. This allows the TRACK/SS pin to be used to program the soft-start period by connecting an external capacitor from the TRACK/SS pin to SGND. An internal 10μA pull-up current charges this capacitor , creat- ing a voltage ramp on the TRACK/SS pin. As the TRACK/ SS voltage rises linearly from 0V to the reference voltage (and beyond), the output voltage V OUT rises smoothly from zero to the final value. Alternatively, the TRACK/SS pin can be used to cause the start-up of V OUT to track that of another supply. Typically this requires connecting to the TRACK/SS pin an external resistor divider from the other supply to ground (see Application Information section). Light Load Current Operation (Burst Mode Operation, Pulse-Skipping Mode, or Continuous Conduction) The LTC7821 can be enabled to enter high efficiency Burst Mode operation, constant-frequency pulse-skipping mode, or forced continuous conduction mode. To select forced continuous operation, tie the MODE/PLLIN pin to a DC voltage below 0.6V (e.g., SGND). To select pulse-skipping mode of operation, tie the MODE/PLLIN pin to INTV CC. To select Burst Mode operation, float the MODE/PLLIN pin.

Rev A For more information www.analog.com When the controller is enabled for Burst Mode operation, the peak current in the inductor is set to approximately one-third of the maximum sense voltage even though the voltage on the I TH pin indicates a lower value. If the average inductor current is higher than the load current, the error amplifier output, EA, will decrease the voltage on the I TH pin. When the I TH voltage drops below 0.5V, the internal sleep signal goes high (enabling sleep mode) and all external MOSFETs are turned off. In sleep mode, the load current is supplied by the output capacitor . As the output voltage decreases, the EA’s output begins to rise. When the output voltage drops enough, the sleep signal goes low, and the controller resumes normal operation by turning on the external MOSFETs on the next cycle of the internal oscillator . When a controller is enabled for Burst Mode operation, the inductor current is not allowed to reverse. The reverse current comparator (IREV) turns off the bottom external MOSFET M4 and M2 just before the inductor current reaches zero, preventing it from revers- ing and going negative. Thus, the controller operates in discontinuous operation. In forced continuous operation, the inductor current is allowed to reverse at light loads or under large transient conditions. The peak inductor current is determined by the voltage on the ITH pin. In this mode, the efficiency at light loads is lower than in Burst Mode operation. However , continuous mode has the advantages of lower output ripple and less interference with audio circuitry. When the MODE/PLLIN pin is connected to INTV CC, the LTC7821 operates in PWM pulse-skipping mode at light loads. At very light loads, the current comparator I CMP may remain tripped for several cycles and force the external MOSFETs M1 and M3 to stay off for the same number of cycles (i.e., skipping pulses). The inductor current is not allowed to reverse (discontinuous operation). This mode, like forced continuous operation, exhibits low output ripple as well as low audio noise and reduced RF interference as compared to Burst Mode operation. It provides higher low current efficiency than forced continuous mode, but not nearly as high as Burst Mode operation. Frequency Selection and Phase-Locked Loop (FREQ and MODE/PLLIN Pins) The selection of switching frequency is a trade-off between efficiency and component size. Low frequency operation increases efficiency by reducing MOSFET switching losses, but requires larger inductance and/or output capacitance to maintain low output ripple voltage. In addition, it will also require larger BOOST capacitance and balancing ca- pacitance (C F LY and CMID) since the refresh rate is lower . The switching frequency of the LTC7821’s controller can be selected using the FREQ pin. If the MODE/PLLIN pin is not being driven by an external clock source, the FREQ pin can be used to program the controller’s operating frequency from 50kHz to 1.7MHz. There is a 10µA current flowing out of the FREQ pin, so the user can program the controller’s switching frequency with a single resistor to SGND. A phase-locked loop (PLL) is integrated on the LTC7821 to synchronize the internal oscillator to an external clock source that is connected to the MODE/PLLIN pin. The controller operates in forced continuous mode when it is synchronized. The PLL loop filter network is integrated inside the LTC7821. The phase-locked loop is capable of locking any frequency within the range of 200kHz to 1.5MHz. The frequency setting resistor should always be present to set the controller’s initial switching frequency before locking to the external clock. Temperature Monitoring When the LTC7821 die temperature reaches 150°C, switching stops and TRACK/SS pin is pulled low. Charge balancing is also disabled. The LTC7821 can provide hotspot monitoring via the TEMP pin. By using a PTC thermistor as the lower leg of a resistor divider and connecting the common point of this divider to the TEMP pin, the voltage increases drastically when the temperature reaches beyond the Curie point of the PTC thermistor as shown in Figure 3. The character- istic of the PTC thermistor is shown in Figure 4. When the TEMP pin reaches 1.22V , all switching stops for 100ms. OPERATION

TEMP pin goes below 1.1V during this 100ms timeout. period will be extended until the voltage drops below 1.1V. often defined as having two times its resistance at 25°C. Figure 5. Temperature T rip Characteristic Figure 3. Temperature Monitoring Setup FB goes out the ±10% window. resistor to sources of up to 80V.

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Figure 4. Characteristic of a Thermistor

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provides the most accurate current limit for the application. are selected, followed by the input and output capacitors. CMID) and the inductance of the inductor . to the current comparators allow accurate DCR sensing. be placed close to the IC pins. IN supply to the step-down control loop. since its contribution is no longer negligible. Figure 6. Sense Lines Placement with Sense Resistor

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of significant parasitic inductance in the sense resistor .

tON • tOFF tON + tOFF ⎝⎜ ⎞ If the RC time constant is chosen to be close to the parasitic inductance divided by the sense resistor (L/R), the result- ing waveform looks resistive again, as shown in Figure 9.

Figure 7. T wo Different Methods of Sensing Current Figure 8. Voltage Waveform Measured Directly Figure 9. Voltage Waveform Measured After the

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Rev A For more information www.analog.com the equation to determine the ESL. However , do not over filter . Keep the RC time constant less than or equal to the inductor time constant to maintain a high enough ripple voltage on V RSENSE. The filter components need to be placed close to the IC. The positive and negative sense traces need to be routed as a differential pair and Kelvin connected to the sense resistor . Inductor DCR Sensing For applications requiring the highest possible efficiency at high load currents, the LTC7821 is capable of sensing the voltage drop across the inductor DCR, as shown in Figure 7b. The DCR of the inductor represents the small amount of DC winding resistance of the copper , which can be less than 1mΩ for today’s low value, high current inductors. In a high current application requiring such an inductor , conduction loss through a sense resistor would cost several points of efficiency compared to DCR sensing. If the external R1|| R2 • C1 time constant is chosen to be exactly equal to the L/DCR time constant, the voltage drop across the external capacitor is equal to the drop across the inductor DCR multiplied by R2/(R1 + R2). R2 scales the voltage across the sense terminals for applications where the DCR is greater than the target sense resistor value. To properly dimension the external filter components, the DCR of the inductor must be known. It can be measured using a good RLC meter , but the DCR tolerance is not always the same and varies with temperature; consult the manufacturers’ data sheets for detailed information. Using the inductor ripple current value from the Inductor Value Calculation section, the target sense resistor value is: RSENSE(EQUIV) = 50mV I(MAX) + ΔIL To ensure that the application will deliver full load current over the full operating temperature range, choose the minimum value for the Maximum Current Sense Threshold SENSE(MAX)) in the Electrical Characteristics table. Next, determine the DCR of the inductor . Where provided, use the manufacturer’s maximum value, usually given at 20°C. Increase this value to account for the temperature coefficient of resistance, which is approximately 0.4%/°C. A conservative value for T L(MAX) is 100°C. To scale the maximum inductor DCR to the desired sense resistor value, use the divider ratio: RD = RSENSE(EQUIV) DCR(MAX) AT T L(MAX) C1 is usually selected to be in the range of 0.047µF to 0.47µF. This forces R1|| R2 to around 2kΩ, reducing error that might have been caused by the SENSE pins’ 1.2µA current. T L(MAX) is the maximum inductor temperature. The equivalent resistance R1||R2 is scaled to the room temperature inductance and maximum DCR: R1||R2 = L (DCR AT 20 °C) • C1 The sense resistor values are: R1= R1||R2 RD ; R2 = R1•R D 1– RD The maximum power loss in R1 is related to duty cycle, and will occur in continuous mode at the maximum input voltage: PLOSS _ R1 = VMID – VOUT( ) • VOUT where VMID is half the voltage of VIN. Ensure that R1 has a power rating higher than this value. If high efficiency is necessary at light loads, consider this power loss when deciding whether to use DCR sensing or sense resistors. Light load power loss can be modestly higher with a DCR network than with a sense resistor , due to the extra switching losses incurred through R1. However , DCR sensing eliminates a sense resistor , reduces conduc- tion losses and provides higher efficiency at heavy loads. Peak efficiency is about the same with either method. To maintain a good signal to noise ratio for the current sense signal, use a minimum ΔVSENSE of 10mV for duty APPLICATIONS INFORMATION

Rev AFor more information www.analog.com cycles less than 40%. For a DCR sensing application, the actual ripple voltage will be determined by the equation: Δ VSENSE = VMID – VOUT R1• C1

VOUT VMID • fOSC Slope Compensation and Inductor Peak Current Slope compensation provides stability in constant fre - quency architectures by preventing subharmonic oscilla- tions at high duty cycles. It is accomplished internally by adding a compensating ramp to the inductor current signal at duty cycles in excess of 40%. Normally , this results in a reduction of maximum inductor peak current for duty cycles >40%. However , the LTC7821 uses a scheme that counteracts this compensating ramp, which allows the maximum inductor peak current to remain unaffected throughout all duty cycles. Inductor Value Calculation Given the desired input and output voltages, the inductor value and operating frequency f OSC directly determine the inductor’s peak-to-peak ripple current: IRIPPLE = VOUT VMID
VMID – VOUT fOSC • L Lower ripple current reduces core losses in the inductor , ESR losses in the output capacitors, and output voltage ripple. Thus, highest efficiency operation is obtained at low frequency with a small ripple current. Achieving this, however , requires a large inductor . A reasonable starting point is to choose a ripple current that is about 40% of I OUT(MAX) for a duty cycle less than 40%. Note that the largest ripple current occurs at the highest input voltage. To guarantee that ripple current does not exceed a specified maximum, the inductor should be chosen according to: L ≥ VMID – VOUT fOSC •IRIPPLE
VOUT VMID For duty cycles greater than 40%, the 10mV current sense ripple voltage requirement is relaxed because the slope compensation signal aids the signal-to-noise ratio and because a lower limit is placed on the inductor value to avoid subharmonic oscillations. To ensure stability for duty cycles up to the maximum of 95%, use the following equation to find the minimum inductance. LMIN > VOUT fSW •ILOAD(MAX)
1.4 where LMIN is in units of µH fSW is in units of MHz Inductor Core Selection Once the inductance value is determined, the type of in - ductor must be selected. Core loss is independent of core size for a fixed inductor value, but it is very dependent on inductance selected. As inductance increases, core losses go down. Unfortunately , increased inductance requires more turns of wire and therefore copper losses will increase. Ferrite designs have very low core loss and are preferred at high switching frequencies, so design goals can con - centrate on copper loss and preventing saturation. Ferrite core material saturates hard, which means that induc - tance collapses abruptly when the peak design current is exceeded. This results in an abrupt increase in inductor ripple current and consequent output voltage ripple. Do not allow the core to saturate! Power MOSFET Selection Four external power MOSFETs must be selected for the LTC7821 . The gate drive voltages to these MOSFETs are derived from the INTVCC voltage, which is typically 5.8V. Hence logic-level threshold MOSFETs must be selected. Only the upper-most MOSFET requires a BV DSS greater than VIN, because this MOSFET sees the full V IN voltage during start-up. The other MOSFETs, M2 to M4, need only have a BV DSS greater than VIN/2. During operation, the type of switching also impacts how each power MOSFET is selected. M1 and M2 operate in soft switching mode, so they should have low Qoss • APPLICATIONS INFORMATION

and (Qg • RdsON) product, respectively. and then plotting the gate voltage versus time. M3 but is not directly specified on MOSFET data sheets. these parameters are not included. switching loss significantly. In the 2nd phase, M2 and M4 are ON (see Figure 13a).

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Figure 11. MOSFET’s Current of T raditional Synchronous Buck Converter Figure 10. Gate Change Characteristic

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Figure 12. First Phase M1 and M3 Current Flow Figure 13. Second Phase M2 and M4 Current Flow

Rev A For more information www.analog.com APPLICATIONS INFORMATION current, but also carries the balancing current that flows between CF LY and C MID due to an imbalance of voltage between the two capacitors at the end of phase 1. There- fore M4 has an increase in conduction losses compared to its counterpart in a traditional buck converter . The current flowing through M2 is dependent on the voltage differential between the capacitors, their ESR, R DSON of M2 and M4, and inductance of the MOSFETs, capacitors, and board traces (see Figure 13b). When the controller is operating in continuous mode the duty cycles for M1, M3, M2 and M4 are given by: M1 , M3 Switch Duty Cycle = 2 • VOUT VIN M2, M4 Switch Duty Cycle = VIN – 2 • VOUT VIN The power dissipation of M1 and M3 is given by: PM1 = IMAX • CFLY CFLY + CMID 2 2 • VOUT VIN ⎠⎟ 1+ d( ) RDS(ON) PM3 = IMAX • CMID CFLY + CMID 2 2 • VOUT VIN ⎠⎟ 1+ d( ) RDS(ON) + VIN

2 IMAX • CMID

2 • C FLY + CMID( ) ⎠⎟ RDR( ) CMILLER( ) • VINTVCC – VTH(MIN) + 1 VTH(MIN) ⎦⎥ • f where d is the temperature dependency of RDS(ON), RDR is the effective top driver resistance (approximately 2Ω at VGS = VMILLER), and VIN is the input supply. V TH(MIN) is the data sheet specified typical gate threshold voltage specified in the power MOSFET data sheet at the specified drain current. C MILLER is the calculated capacitance using the gate charge curve from the MOSFET data sheet and the technique described above. If the switching loss contribution of P M3 is relatively small compared to its conduction loss, then the overall power dissipation (PM1 + PM3) will be the lowest when CF LY = CMID. The power dissipation of M2 and M4 is harder to calcu - late, because the current flowing through these MOSFETs exhibits a 2nd order system response due to the presence of parasitic package inductance of the MOSFETs and ca- pacitors, ESR of the capacitors, RDS(ON) of the MOSFETs and the capacitance of C MID and CF LY. Complicating the matter is that the current could exhibit overdamped, criti- cally damped or underdamped characteristics, depending on the RLC values mentioned above ; this would impact the RMS current significantly. Use ADI/L TC power tool to help select M2 and M4. With the RMS current flowing through M2 and M4 deter- mined, the power dissipation is given by: PM2 = I2rms2 • 1 + d( ) RDS(ON) PM4 = I2rms4 • 1 + d( ) RDS(ON) CF LY and CMID Selection In this hybrid topology, capacitors CF LY and CMID are part of the energy transfer elements. Therefore ceramic capacitors are attractive since they have the lowest ESR. However , care should be taken when choosing this type of capacitor . During operation the DC voltage across the C F LY and CMID is approximately half the VIN supply, therefore the voltage rating of the capacitors should be greater than that. As a general rule, select the voltage rating of the capacitor to be twice the operating voltage of the capacitor . For the same voltage rating and capacitance, a larger case size will have a lower failure rate. In addition, the operating temperature of the capacitors needs to be considered. For operating temperature above 85°C, capacitors with the X7R dielectric need to be used while X5R dielectric is adequate for operation below 85°C. For long term reliability of the capacitor , keep the tem - perature rise of the capacitor to be below 20°C, preferably 10°C . The temperature rise of the capacitor is dependent on the amount of RMS current through the capacitor and the operating frequency. Consult the manufacturer’s data sheet for this data.

in M2 and M4 (see Power MOSFET Selection section). MID to be the same as that of CF LY. to provide the drive voltages for MOSFETs M1 to M3. where VF_DX is the forward voltage of diode X. Figure 14. External Charge Pump

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Rev A For more information www.analog.com APPLICATIONS INFORMATION To obtain the most translation in voltage from VINTVCC to drive M1, Schottky diodes are recommended. The reverse voltage seen by each of the Schottky diodes is approximately: VR _ DIODE ≅ VIN Pay attention to the leakage current when selecting the forward drop of the diodes. In general, the lower the forward drop for the same amount of current flowing through the diode, the higher the leakage current. As these diodes will be operating with large reverse bias for high V IN applications, the leakages are higher , especially at higher operating temperatures. The charge pump diodes operate as conduits for transfer- ring charge from one capacitor to another and as such are subjected to transient current rather than a DC current. Hence peak forward surge rating is more important than the average current rating. A surge rating of 750mA is a good starting point. Since the bootstrap capacitor acts as a supply for the MOSFET’s driver , select large enough capacitance so that the voltage does not droop considerably when the MOSFETs are being turned ON. As with the C MILLER esti- mation described in the Power Selection section, the user can use the same graph to obtain the total gate charge for a given gate drive voltage. This can then easily converted to its equivalent gate capacitance by: CG = QG VGS If the bootstrap capacitor voltage is not allowed to droop by more than 1%, then: CBST ≥ 99CG Besides acting as a supply for their respective MOSFET drivers, C BST2 and CBST3 also serve as charge pump ca - pacitors. As a good starting point, size C BST2 and CBST3 as follows: CBST3 ≥ 2CBST2 ≥ 2CBST1 Soft-Start and T racking The LTC7821 has the ability to either soft-start by itself with a capacitor or track the output of another channel or external supply. When configured to soft-start by itself, a capacitor should be connected to its TRACK/SS pin and ground. When RUN pin voltage is below 1.22V, the TRACK/ SS is actively pulled to ground in this shutdown state. Once the RUN pin voltage is above 1.22V, the controller powers up and a soft-start current of 10µA begins to flow out of the TRACK/SS pin. However , the TRACK/SS will start charging its soft-start capacitor only after charge balance is completed and the associated active pull-down of the TRACK/SS is released. Note that soft-start or tracking is achieved not by limiting the maximum output current of the controller but by controlling the output ramp voltage according to the ramp rate on the TRACK/SS pin. Current fold-back is disabled during this phase to ensure smooth soft-start or tracking. Depending on whether the EXT_REF feature has been invoked or not, the soft-start or tracking range is defined to be either the voltage range from 0V to 0.8V or 0V to V EXT_REF on the TRACK/SS pin. The total soft-start time can be calculated as: tSOFT − START = 0.8 or VEXT _REF( ) • CSS 10µA Regardless of the mode selected by the MODE/PLLIN pin, the regulator will always start in pulse-skipping mode up to TRACK/SS = 82.5% of 0.8V or V EXT_REF. Output Voltage T racking The LTC7821 allows the user to program how its output ramps up and down by means of the TRACK/SS pins. Through this pin, the output can be set up to either coin- cidentally or ratio-metrically track another supply’s output, as shown in Figure 15. In the following discussions, V OUT1 refers to another supply’s output (master channel) while V OUT2 refers to the LTC7821 output (slave channel) that tracks VOUT1. To implement the coincident tracking in Figure 15a, connect an additional resistive divider to VOUT1 and connect its midpoint to the TRACK/SS pin of the LTC7821. The ratio of this divider should be the same as that of the slave channel’s feedback divider shown in Figure 16a. In this tracking mode, V OUT1 must be set higher than VOUT2.

Figure 17. Output Voltage Set By EXT_REF Pin

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Figure 15. T wo Different Methods of Output Voltage T racking Figure 16. Setup for Coincident and Ratio-Metric T racking

The ratio-metric mode uses one less pair of resistors

minimize this error , use smaller resistor values in the divider . 0.9V, as indicated by the characteristic in Figure 17.

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the complete sinking of the sourcing current. Select RLOAD to be about 70% of the calculated value.

e D1• TS 2 •t1 + e –D1• TS 2 •t1 e D1• TS 2 •t1 – e –D1• TS 2 •t1 + e D2 • TS 2 •t2 + e –D2 • TS 2 •t2 e D2 • TS 2 •t2 – e –D2 • TS 2 •t2 = 1 8 • CFLY • fSW
coth D1• TS 2 •t1 ⎠ + coth D2 • TS 2 •t2 where: TS = Switching period fSW = Switching frequency D1 = Duty cycle of MOSFET 1 and 3 D2 = Duty cycle of MOSFET 2 and 4 t1 = (R ON1 + RON3 + RESR_FLY) • CF LY t2 = (RON2 + RON4 + RESR_FLY) • CF LY RONX = Resistance of MOSFET X in Ω

Figure 18. Output Voltage to T rack VIN in 4:1 Ratio Where TS is the switching period.

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Rev AFor more information www.analog.com APPLICATIONS INFORMATION Figure 19a shows a typical LTC7821 output stage setup while 19b shows the equivalent circuit. Note that M3 and M4 form the buck converter switches, taking its power from MID, with its voltage given by: VMID = VIN – I OUT • VOUT VIN

1 h ⎠⎟ • ZMID where h = efficiency of the buck converter . A good conservative number to use for h is 0.9. The above equation gives us the average MID voltage and does not include the AC ripple on it. The C MID ripple voltage is given by (see CF LY and CMID Selection section): VCMID _ RIPPLE = IOUT • tON 2CMID Therefore the maximum deviation of MID voltage from V IN/2 is given by: ΔVMID _ IDEAL = VIN – VMID – IOUT • tON 2CMID Use the above equation as a guideline to set the HYS_PRGM voltage. Design Example A 48V to 5V, 25A operating at 500kHz application is used as an example. Since the output current is high, DCR sensing is used to regulate the current loop. For 500kHz operation, a 68k resistor is connected from FREQ to ground. Since V IN = 48V, Infineon BSC027N06LS5 is chosen for M1. This is an 60V MOSFET . For M2 to M4, 30V MOSFETs are sufficient for this application. For M2 and M3, Infineon BSC032N04LS are selected and an Infineon BSC014N04LSI is selected for M4. M1 , M3 DUTY CYCLE= 5 = 0.208 TOFF = (1– 0.208) • 2µs = 1.58µs With inductor current ripple initially scaled to 40% of output current, ΔI Hence, L = VOUT • TOFF ΔI L = 5 • 1.58 • 10– 6 = 0.79µH An inductance of 0.9µH is selected (Coilcraft SER2011- 901L) instead and this give ΔIL = 8.8A. The RMS current through the inductor is: IRMS _ L = I2OUT + ΔI2L = 252 + 0.42 = 25.2A From the manufacturer data sheet, the rise in temperature of the inductor is 15°C. However , this rise does not account for the conduction of heat from the MOSFETs through the PCB that increases the overall inductor’s temperature. Depending on how the board is being laid out and how much air flow is applied, the net increase in temperature could be higher . For this design example, assume the net temperature rise to be 50°C. The typical DCR of the inductor is typically 1.2mΩ with a maximum of 1.34 mΩ and with a 50°C rise in temperature and assuming the temperature coefficient of the DCR at 0.4%/°C, the maximum DCR is: RDCΔ = 15°C = 1.34 • 1 + 0.4 • 50 100 ⎠⎟ • 10– 3 = 1.61m Ω

Figure 19. LTC7821 Output Setup

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Rev AFor more information www.analog.com APPLICATIONS INFORMATION With a VSENSE = 50mV, the DCR will set the peak inductor current to be 31A. With a ripple ΔIL of 8.8A, the application will provide 25A of output current. For the sensing network, select C1 = 0.22μF, then: R8 = L C1•DCR = 3.4kΩ For the design, a 3.32k resistor is used. The next components to select are the C MID and CF LY. In this example, CMID = CF LY To maintain ripple at C MID and C F LY to be 1% of its DC bias: ΔVCMID and ΔV CFLY = 0.01• 24 = 240mV Hence, CFLY = IOUT • tON 2 • ΔVCMID 2 • 0.24 = 21.88µF = CMID The voltage rating chosen for these capacitors is 50V and even with this rating, the actual capacitance is lower due to its voltage coefficient. 6 × 10µF is chosen for each C MID and CF LY. With this value of CMID, the voltage ripple at MID is now: VCMID _ ripple = IOUT • tON 2 • 60 • 10– 6 = 87.5mV The next components to select are the bootstrap capaci- tors. For M1, the gate charge needed to charge its gate from V GS = 0V to 6V is: QG = 9nC Therefore, it’s equivalent gate capacitance is: CG = QG VGS = 1.5nF Hence, CBST1 = 99 • CG = 0.15μF Use, CBST1 = 0.22μF CBST2 = 0.47μF CBST3 = 1μF For the Schottky diodes, Central’s CMDSH-4 are used. From the manufacturer data sheet, the R DSON of M1 to The equivalent impedance at MID node, Z MID, can be calculated to be: ZMID = 1 8 • CFLY • fSW

coth D1• TS 2 •t1 ⎠⎟ + coth D2 • TS 2 •t2 = 18.15m Ω This will result in an average MID voltage of: VMID = VIN/2 – (31A • 18.15mΩ) = 23.437V Factoring in the ripple voltage on C MID, the minimum VMID is: VMID _ MIN = 23.437 – 0.0875 = 23.35V This is 650mV lower than the ideal voltage of 24V at MID point. Therefore set the voltage at HYST_PRGM pin to be 1V with a resistor of 100k. The completed circuit for this design example is shown in Figure 20.

Rev A For more information www.analog.com APPLICATIONS INFORMATION Minimum On-Time Considerations Minimum on-time tON(MIN) is the smallest time duration that the LTC7821 is capable of turning on the top MOSFET . It is determined by internal timing delays and the gate charge required to turn on the top MOSFET . Low duty cycle applications may approach this minimum on-time limit and care should be taken to ensure that: tON(MIN) < 2 • VOUT VIN(f) If the duty cycle falls below what can be accommodated by the minimum on-time, the controller will begin to skip cycles. The output voltage will continue to be regulated, but the ripple voltage and current will increase. The minimum on-time for the LTC7821 is approximately 210ns, with reasonably good PCB layout, minimum 30% inductor current ripple and at least 10mV – 15mV ripple on the current sense signal. The minimum on-time can be affected by PCB switching noise in the voltage and current loop. As the peak sense voltage decreases the minimum on-time increases. This is of particular concern in forced continuous applications with low ripple current at light loads. If the duty cycle drops below the minimum on-time limit in this situation, a significant amount of cycle skip- ping can occur with correspondingly larger current and voltage ripple. Multiphase Operation For high output power applications, two LTC7821 's can be paralleled to create a dual phase single output configura- tion. Figure 22 shows the key signal connections between the two LTC7821s.

Figure 20. A 48V to 5V, 500kHz, 25A Application

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Figure 21. CF LY Prebias Current Path Figure 22. Connection of Key Signals

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Figure 23. 500kHz 48V to 9V, 20A Step-Down Converter

7821 F23a

Rev A For more information www.analog.com Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However , no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. PACKAGE DESCRIPTION Please refer to http://www.linear .com/product/LTC7821#packaging for the most recent package drawings. 5.00 ±0.10 (4 SIDES) NOTE: 1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE M0-220 VARIATION WHHD-(X) (TO BE APPROVED) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE PIN 1 TOP MARK (NOTE 6) 0.40 ±0.10 BOTTOM VIEW—EXPOSED PAD

3.50 REF

(4-SIDES) 3.45 ±0.10 3.45 ±0.10 0.75 ±0.05 R = 0.115 TYP 0.25 ±0.05 (UH32) QFN 0406 REV D

0.50 BSC

0.200 REF

0.00 – 0.05 0.70 ±0.05 (4 SIDES) 4.10 ±0.05 5.50 ±0.05 0.25 ±0.05 PACKAGE OUTLINE RECOMMENDED SOLDER PAD LAYOUT APPL Y SOLDER MASK TO AREAS THAT ARE NOT SOLDERED PIN 1 NOTCH R = 0.30 TYP OR 0.35 × 45° CHAMFERR = 0.05 TYP 3.45 ±0.05 3.45 ±0.05 32-Lead Plastic QFN (5mm × 5mm) (Reference LTC DWG # 05-08-1693 Rev D)

Rev AFor more information www.analog.com

REVISION HISTORY

REV DATE DESCRIPTION PAGE NUMBER A 04/18 Corrected Note 4 to Note 5 on EC table Corrected conditions for IVIN, VIN_SENSE and gm Remove references to Timing Diagram Update RUN pin description Corrected current source on RUN pin from 10µA to 1µA Fixed text formatting on “RD” symbol Updated Soft-Start time formula for clarity Corrected C11 to C1

Rev A For more information www.analog.com  ANALOG DEVICES, INC. 2017-2018 D16842-0-4/18(A) www.analog.com RELATED PARTS TYPICAL APPLICATION PART NUMBER DESCRIPTION COMMENTS LTC7820 Fixed Ratio High Power Inductorless (Charge Pump) DC/DC Controller 6V < V ≤ VIN 72V, Fixed 50% Duty Cycle, 100kHz to 1MHz Switching Frequency (4mm × 5mm) UFD Package LTC3895 150V Low IQ, Synchronous Step-Down DC/DC Controller 4V ≤ VIN ≤ 140V, 150VPK, 0.8V ≤ VOUT ≤ 24V, IQ = 50µA, PLL Fixed Frequency 50kHz to 900kHz LTC3810 100V Synchronous Step-Down DC/DC Controller Constant On-Time Valley Current Mode 6.2V ≤ V IN ≤ 100V, 0.8V ≤ VOUT ≤ 0.93VIN, SSOP-28 LTC3891 60V, Low IQ, Synchronous Step-Down DC/DC Controller with 99% Duty Cycle 4V ≤ VIN ≤ 60V, 0.8V ≤ VOUT ≤ 24V, IQ = 50µA, PLL Fixed Frequency 50kHz to 900kHz LT3840 60V, Low IQ, Synchronous Step-Down Controller with Integrated Buck-Boost Bias Voltage Regulator 2.5V ≤ VIN ≤ 60V, 1.23V ≤ VOUT ≤ 60V, IQ = 75µA, Synchronizable Fixed Frequency 100kHz to 600kHz LTC3892/ LTC3892-1 60V Low IQ, Dual, 2-Phase Synchronous Step-Down DC/DC Controller with 99% Duty Cycle 4V ≤ VIN ≤ 60V, 0.8V ≤ VOUT ≤ 0.99VIN, PLL Fixed Frequency 50kHz to 900kHz, Adjustable 5V to 10V Gate Drive, IQ = 29µA LTC7813 Low IQ, Synchronous Boost + Buck DC/DC Controller 4.5V (Down to 2.2V After Start-Up) ≤ VIN ≤ 60V, 0.8V ≤ VOUT ≤ 60V, Adjustable 5V to 10V Gate Drive, IQ = 33µA LT8705A 80V VIN and VOUT Synchronous 4-Switch Buck-Boost DC/DC Controller 2.8V ≤ VIN ≤ 80V, 100kHz to 400kHz Programmable Operating Frequency (5mm × 7mm) QFN-38 and TSSOP-38 LTC3886 60V Dual Output Step-Down Controller with PSM 4.5V ≤ VIN ≤ 60V, 0.5V ≤ VOUT (±0.5%) ≤ 13.8V, Input Current Sense, I2C/PMBus Interface with EEPROM and 16-Bit ADC LTC3871 Bidirectional Multiphase Synchronous Buck or Boost Controller Regulation of Input Voltage, Output Voltage or Current V HIGH Up to 100V, VLOW Voltages Up to 30V High Efficiency 500kHz 2-Phase 48V to 12V at 40A Step-Down Converter L1, 2µH CFL Y1 10µF 14.7k CB1 0.22µF CB2 0.47µF CB3 1µF CVCC 4.7µF CIN 100µF R2, 100/uni03A9 C6, 0.1µF R11 55.57k 1µF 10k 10k C10 0.1µF 0.015µF COUT 150µF VOUT 12V , 40A R3, 1k RFB1 60.4k RFB2 4.32k 0.1µF C7, 0.1µF 10µF R6, 68k R7, 100k 6.81k C11 0.22µF VIN_SENSE VIN TEMP CLKOUT TIMER RUN FREQ HYS_PRGM EXT_REF FAUL T PGOOD MODE/PLLIN ITH TRACK/SS EXTVCC VFB ISNS+ ISNS– PGND INTVCC BG2 SW3 BOOST3 TG2 MID_SENSE MID BOOST2 BG1 SW1 BOOST1

7821 TA02

10µF 2.2µF VIN 36V TO 72V VIN_SENSE VIN TEMP TIMER RUN FREQ HYS_PRGM EXT_REF FAUL T PGOOD MODE/PLLIN ITH TRACK/SS EXTVCC VFB ISNS+ ISNS– PGND INTVCC BG2 SW3 BOOST3 TG2 MID_SENSE MID BOOST2 BG1 SW1 BOOST1 TG1 INTVCC2 L2, 2µH CFL Y2 10µF CB4 0.22µF C13 0.1µF C12 1µF CB5 0.47µF CB6 1µF CVCC1 4.7µF R16 6.81k R15, 100k R14, 100k R10, 100/uni03A9 R13, 1k C22 0.22µF C17 0.1µF C18 10µF R9 : MURATA PRF15BC102RB6RC M1, M5: INFINEON BSC057N08NS3 M2, M3, M6, M7: INFINEON BSC032N04LS M4, M6: INFINEON BSC014N04LSI L1, L2 : COILCRAFT SER2011-202ML CFL Y1, CFL Y2, C2, C18: MURATA GRM32ER71H106KA12 D1 TO D6 : CENTRAL SEMICONDUCTOR CMDSH-4 VOUTVOUT 12V 8V TO EXTVCC PIN OF L TC7821VIN L TC3621

Selected Specification

Linear Technology LT3840 overview.

Summary

Hybrid Step-Down Synchronous Controller

Description

Hybrid Step-Down Synchronous Controller

Source title LT3840 Datasheet(PDF) - Linear Technology

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