LT3825

LT3825 LINER

Document overview

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Technical content

FEATURES

APPLICATIONS

DESCRIPTION

Synchronous Flyback Controller with Wide Input Supply Range n Isolated Medium Power (10W to 60W) Supplies n Isolated Telecom, Medical Converters n Instrumentation Power Supplies n Isolated Power over Ethernet Supplies L, L TC and L T are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 6948466, 5841643. 48V to 3.3V at 12V Isolated Supply Effi ciency n Senses Output Voltage Directly from Primary Side Winding—No Optoisolator Required n Synchronous Driver for High Effi ciency n Input Voltage Limited Only by External Power Components n Accurate Output Regulation Without User T rims n Switching Frequency from 50kHz to 250kHz n Synchronizable n Load Compensation n Programmable Undervoltage Lockout n Available in a Thermally Enhanced 16-Lead The L T®3825 is an isolated switching regulator controller designed for medium power fl yback topologies. A typical application is 10W to 60W with input voltage limited only by external power path components. A third transformer winding provides output voltage feedback. The L T3825 is a current mode controller that regulates output voltage based on sensing secondary voltage via a transformer winding during fl yback. This allows for tight output regulation without the use of an optoisolator , improving dynamic response and reliability. Synchronous rectifi cation increases converter effi ciency and improves output cross regulation in multiple output converters. The L T3825 operates in forced continuous conduction mode which improves cross regulation in multiple winding ap- plications. Switching frequency is user programmable and can be externally synchronized. The part also has load com- pensation, undervoltage lockout and soft-start circuity. LOAD CURRENT (A) EFFICIENCY (%) 3 7 9

3825 TA01b

LOAD CURRENT (A)

3.13 OUTPUT (V)

3.18 3.28 3.33 3.38 3.43 3 7 9

3825 TA01c

3.23 6 11 124 5 81 0 36VIN 48VIN 72VIN 100k12k 3.01k 28.7k 402k 20Ω 47Ω 47k 20Ω 100pF 470μF VOUT+ 3.3V 12A VIN+ 36V TO 72V 0.02Ω 47μF 15k 2.1k 150k 0.22μF 100k 10k 15Ω330Ω 47pF 2.2μF 0.1μF 10nF 2.2nF0.1μF

3825 TA01a

1μF tON SYNC PGDL Y UVLO SENSE– VC SENSE+ RCMP ENDL Y OSC L T3825 GND SFST SGFB VCC SG SG PG CCMP

PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS VCC to GND Current Fed V Operating Junction Temperature Range (Note 1)

ELECTRICAL CHARACTERISTICS

The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. VCC = 14V; PG, SG Open; VC = 1.5V , VSENSE– = 0V; RCMP = 1k, RtON = 90k, RPGDL Y = 27.4k, RENDL Y = 90k, unless otherwise specifi ed. FE PACKAGE 16-LEAD PLASTIC TSSOP TOP VIEW SG V CC tON ENDL Y SYNC SFST OSC FB PG PGDL Y R CMP CCMP SENSE+ SENSE– UVLO V C TJMAX = 125°C, θJA = 40°C/W , θJC = 10°C/W EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB PARAMETER CONDITIONS MIN TYP MAX UNITS Power Supply VCC Turn-On Voltage l 14.0 15.3 16.0 V VCC Turn-Off Voltage ● 8 9.7 11 V VCC Hysteresis VCC(ON) – VCC(OFF) ● 4.0 5.6 6.5 V VCC Shunt Clamp VUVLO = 0V , IVCC = 15mA ● 19.5 20.5 V VCC Supply Current (Note 5) (ICC)V C = Open ● 4 6.4 10 mA VCC Start-Up Current VCC = 10V ● 180 400 μA Feedback Amplifi er Feedback Regulation Voltage (V FB) ● 1.220 1.237 1.251 V Feedback Pin Input Bias Current R CMP Open 200 nA Feedback Amplifi er T ransconductance ΔIC = ±10μA ● 700 1000 1400 μmho Feedback Amplifi er Source or Sink Current ● 25 55 90 μA Feedback Amplifi er Clamp Voltage VFB = 0.9V VFB = 1.4V 2.56 V ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE L T3825EFE#PBF L T3825EFE#TRPBF 3825EFE 16-Lead Plastic 4.4mm TSSOP –40°C to 125°C LEAD BASED FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE L T3825EFE L T3825EFE#TR 3825EFE 16-Lead Plastic 4.4mm TSSOP –40°C to 125°C Consult L TC Marketing for parts specifi ed with wider operating temperature ranges. For more information on lead free part marking, go to: http://www.linear .com/leadfree/ For more information on tape and reel specifi cations, go to: http://www.linear .com/tapeandreel/

PARAMETER CONDITIONS MIN TYP MAX UNITS Reference Voltage Line Regulation 12V ≤ V CC ≤ 18V ● 0.005 0.02 %/V Feedback Amplifi er Voltage Gain V C = 1.2V to 1.7V 1400 V/V Soft-Start Charging Current V SFST = 1.5V 16 20 25 μA Soft-Start Discharge Current V SFST = 1.5V , VUVLO = 0V 0.8 1.3 mA Control Pin Threshold (VC) Duty Cycle = Min 1.0 V Gate Outputs PG, SG Output High Level

• 6.6 7.4 8.0 V PG, SG Output Low Level ● 0.01 0.05 V PG, SG Output Shutdown Strength V UVLO = 0V; IPG, ISG = 20mA ● 1.6 2.3 V PG Rise Time C PG = 1nF 11 ns SG Rise Time C SG = 1nF 15 ns PG, SG Fall Time C PG, CSG = 1nF 10 ns Current Amplifi er Switch Current Limit at Maximum V C VSENSE+ ● 88 98 110 mV ΔVSENSE/ΔVC 0.07 V/V Sense Voltage Overcurrent Fault Voltage V SENSE+, VSFST < 1V ● 206 230 mV Timing Switching Frequency (f OSC)C OSC = 100pF ● 84 100 110 kHz Oscillator Capacitor Value (COSC) (Note 6) 33 200 pF Minimum Switch On Time (tON(MIN)) 200 ns Flyback Enable Delay Time (tED) 265 ns PG Turn-On Delay Time (tPGDL Y) 200 ns Maximum Switch Duty Cycle ● 85 88 % SYNC Pin Threshold ● 1.53 2.1 V SYNC Pin Input Resistance 40 kΩ Load Compensation Load Comp to V SENSE Offset Voltage V RCMP with VSENSE+ = 0V 1 mV Feedback Pin Load Compensation Current V SENSE+ = 20mV , VFB = 1.230V 20 μA UVLO Function UVLO Pin Threshold (V UVLO) ● 1.215 1.240 1.265 V UVLO Pin Bias Current V UVLO = 1.2V VUVLO = 1.3V –0.25 –4.50 –3.4 ±0.25 –2.50 μA μA

The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. VCC = 14V; PG, SG Open; VC = 1.5V , VSENSE– = 0V; RCMP = 1k, RtON = 90k, RPGDL Y = 27.4k, RENDL Y = 90k, unless otherwise specifi ed. Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 125°C when overtemperature protection is active. Continuous operation above the specifi ed maximum operating junction temperature may impair device reliability. Note 3: The L T3825E is guaranteed to meet performance specifi cations from 0°C to 125°C. Specifi cations over the –40°C to 125°C operating temperature range are assured by design, characterization and correlation with statistical process controls. Note 4: T J is calculated from the ambient temperature TA and power dissipation PD according to the following formula: T J = TA + (PD • 40°C/W) Note 5: Supply current does not include gate charge current to the MOSFETs. See Applications Information. Note 6: Component value range guaranteed by design.

TYPICAL PERFORMANCE CHARACTERISTICS VCC(0N) and VCC(OFF) vs Temperature VCC Start-Up Current vs Temperature VCC Current vs Temperature SENSE Voltage vs Temperature SENSE Fault Voltage vs Temperature Oscillator Frequency vs Temperature VFB vs Temperature Feedback Pin Input Bias vs Temperature VFB Reset vs Temperature TEMPERATURE (°C) –50 VCC (V)

3825 G01

–25 0 50 75 100 125 VCC(ON) VCC(OFF) TEMPERATURE (°C) –50 IVCC (μA) 200 250 300 25 75

3825 G02

–25 0 50 100 125 TEMPERATURE (°C) –50 25 75

3825 G03

–25 0 50 100 125 IVCC (mA) DYNAMIC CURRENT CPG = 1nF, CSG = 1nF, fOSC = 100kHz STATIC PART CURRENT VCC = 14V TEMPERATURE (°C) –50 SENSE VOLTAGE (mV) 100 110 104 0 50 75

3825 G04

–25 25 100 125 FB = 1.1V SENSE = VSENSE+ WITH VSENSE– = 0V TEMPERATURE (°C) –50 SENSE VOLTAGE (mV) 215

3825 G05

–25 0 50 185 180 220 210 205 195 75 100 125 SENSE = VSENSE+ WITH VSENSE– = 0V TEMPERATURE (°C) –50 fOSC (kHz) 100 110 104 0 50 75

3825 G06

–25 25 100 125 COSC = 100pF TEMPERATURE (°C) –50

1.230 VFB (V)

1.231 1.233 1.234 1.235 1.240 1.237 0 50 75

3825 G07

1.232 1.238 1.239 1.236 –25 25 100 125 TEMPERATURE (°C) –50 FEEDBACK PIN INPUT BIAS (nA) 200 250 300 25 75

3825 G08

–25 0 50 100 125 RCMP OPEN TEMPERATURE (°C) –50 VFB RESET (V) 1.03

3825 G09

1.00 0.98 –25 0 50 0.97 0.96 1.04 1.02 1.01 0.99 75 100 125

TYPICAL PERFORMANCE CHARACTERISTICS Feedback Amplifi er Output Current vs VFB Feedback Amplifi er Source and Sink Current vs Temperature Feedback Amplifi er g m vs Temperature Feedback Amplifi er Voltage Gain vs Temperature UVLO vs Temperature I UVLO Hysteresis vs Temperature Soft-Start Charge Current vs Temperature PG, SG Rise and Fall Times vs Load Capacitance VCC Clamp Voltage vs Temperature VFB (V) 0.9 –70 IVC (μA) –50 –30 –10 1 1.1 1.4 1.2 1.3 1.5

3825 G10

125°C 25°C –40°C TEMPERATURE (°C) –50 IVC (μA) 25 75

3825 G11

–25 0 50 100 125 SOURCE CURRENT VFB = 1.1V SINK CURRENT VFB = 1.4V TEMPERATURE (°C) –50 900 gm (μmho) 950 1000 1050 1100 –25 0 25 50

3825 G12

TEMPERATURE (°C) –50 AV (V/V) 1550

3825 G13

–25 0 50 1250 1200 1150 1100 1600 1650 1700 1500 1450 1350 75 100 125 TEMPERATURE (°C) –50 UVLO (V) 1.240 1.245 1.250 25 75

3825 G14

1.235 1.230 –25 0 50 100 125 1.225 1.220 TEMPERATURE (°C) –50 3.4 3.5 3.7 25 75

3825 G15

3.3 3.2 –25 0 50 100 125 3.1 3.0 3.6 IUVLO (μA) TEMPERATURE (°C) –50 SFST CHARGE CURRENT (μA)

3825 G16

–25 0 50 75 100 125 CAPACITANCE (nF) TIME (ns)

3825 G17

TA = 25°C FALL TIME RISE TIME TEMPERATURE (°C) –50 –25

19.0 VCC (V)

20.0 21.5 0 50 75

3825 G18

19.5 21.0 20.5 25 100 125 ICC = 10mA

TYPICAL PERFORMANCE CHARACTERISTICS Minimum PG On Time vs Temperature PG Delay Time vs Temperature Enable Delay Time vs Temperature TEMPERATURE (°C) –50 tON(MIN) (ns) 330

3825 G19

–25 0 50 270 260 340 320 310 290 75 100 125 RtON(MIN) = 158k TEMPERATURE (°C) –50 tPGDLY (ns) 150 200 250 0 50 75

3825 G20

–25 25 100 125 300 RPGDLY = 16.9k RPGDLY = 27.4k TEMPERATURE (°C) –50 tED (ns) 220 240 260 25 75

3825 G21

–25 0 50 100 125 160 140 RENDLY = 90k SG (Pin 1): Synchronous Gate Drive Output. This pin provides an output signal for a secondary-side synchro- nous switch. Large dynamic currents may fl ow during voltage transitions. See the Applications Information for details. V CC (Pin 2): Supply Voltage Pin. Bypass this pin to ground with a 4.7μF capacitor or more. This pin has a 19.5V clamp to ground. V CC has an undervoltage lockout function that turns the part on when VCC is approximately 15.3V and off at 9.7V . In a conventional “trickle-charge” bootstrapped confi guration, the V CC supply current increases signifi cantly during turn-on causing a benign relaxation oscillation action on the V CC pin if the part does not start normally. tON (Pin 3): Pin for external programming resistor to set the minimum time that the primary switch is on for each cycle. Minimum turn-on facilitates the isolated feedback method. See Applications Information for details. ENDL Y (Pin 4): Pin for external programming resistor to set enable delay time. The enable delay time disables the feedback amplifi er for a fi xed time after the turn-off of the primary-side MOSFET . This allows the leakage inductance voltage spike to be ignored for fl yback voltage sensing. See Applications Information for details. SYNC (Pin 5): Pin for synchronizing the internal oscilla- tor with an external clock. The positive edge on a pulse causes the oscillator to discharge causing PG to go low (off) and SG high (on). The sync threshold is typically 1.6V . See Applications Information for details. Tie to ground if unused. SFST (Pin 6): This pin, in conjunction with a capacitor to ground, controls the ramp-up of peak primary current as sensed through the sense resistor . This is used to control converter inrush current at start-up. The V C pin voltage cannot exceed the SFST pin voltage, so as SFST increases, the maximum voltage on V C increases commensurately, allowing higher peak currents. Total VC ramp time is ap- proximately 70ms per μF of capacitance. Leave pin open if not using the soft-start function. OSC (Pin 7): This pin in conjunction with an external capacitor defi nes the controller oscillator frequency. The frequency is approximately 100kHz • 100/C OSC(pF). FB (Pin 8): Pin for the feedback node for the power sup- ply feedback amplifi er . Feedback is usually sensed via a third winding and enabled during the fl yback period. This pin also sinks additional current to compensate for load current variation as set by the R CMP pin. Keep the Thevenin equivalent resistance of the feedback divider at roughly 3k.

VC (Pin 9): Pin used for frequency compensation for the switcher control loop. It is the output of the feedback amplifi er and the input to the current comparator . Switcher frequency compensation components are normally placed on this pin to ground. The voltage on this pin is propor- tional to the peak primary switch current. The feedback amplifi er output is enabled during the synchronous switch on time. UVLO (Pin 10): A resistive divider from V IN to this pin sets an undervoltage lockout based upon VIN level (not VCC). When the UVLO pin is below its threshold, the gate drives are disabled, but the part draws its normal quiescent current from V CC. The VCC undervoltage lockout supersedes this function so VCC must be great enough to start the part. The bias current on this pin has hysteresis such that the bias current is sourced when the UVLO threshold is ex- ceeded. This introduces a hysteresis at the pin equivalent to the bias current change times the impedance of the upper divider resistor . The user can control the amount of hysteresis by adjusting the impedance of the divider . See the Applications Information for details. Tie the UVLO pin to V CC if you are not using this function. SENSE– (Pin 11), SENSE+ (Pin 12): These pins are used to measure primary side switch current through an ex- ternal sense resistor . Peak primary side current is used in the converter control loop. Make Kelvin connections to the sense resistor to reduce noise problems. SENSE connects to the ground side. At maximum current (VC at its maximum voltage) it has a 98mV threshold. The signal is blanked (ignored) during the minimum turn-on time. CCMP (Pin 13): Pin for external fi lter capacitor for the optional load compensation function. Load compensation reduces the effects of parasitic resistances in the feedback sensing path. A 0.1μF ceramic capacitor suffi ces for most applications. Short this pin to GND in less demanding ap- plications that don’t require load compensation. R CMP (Pin 14): Pin for optional external load compensation resistor . Use of this pin allows for nominal compensation of parasitic resistances in the feedback sensing path. In less demanding applications, this resistor is not needed and this pin can be left open. See Applications Informa- tion for details. PGDL Y (Pin 15): Pin for external programming resistor to set delay from synchronous gate turn-off to primary gate turn-on. See Applications Information for details. PG (Pin 16): Gate Drive Pin for the Primary Side MOSFET Switch. Large dynamic currents fl ow during voltage transi- tions. See the Applications Information for details. GND (Exposed Pad, Pin 17): This is the ground connection for both signal ground and gate driver grounds. This GND should be connected to the PCB ground plane. Careful at- tention must be paid to ground layout. See Applications Information for details. PIN FUNCTIONS

SENSE– SENSE+ CCMP VCC TO FB PGATE SGATE CURRENT SENSE AMP RCMPF 50k LOAD COMPENSATION + – – + VCC 15.3V VCC UVLO UVLO IUVLO OSC7 tON PGDLY15 ENDLY4 SYNC5 1.235V REFERENCE (VFB) INTERNAL REGULATOR UVLO COLLAPSE DETECT ERROR AMP CLAMPS 0.7 1.3 19.5V S R Q Q 8FB VC SFST TSD CURRENT TRIP SLOPE COMPENSATION CURRENT COMPARATOR OVERCURRENT FAULT LOGIC BLOCK RCMP GATE DRIVE PG SG GND OSCILLATOR SET ENABLE VCC GATE DRIVE

FLYBACK FEEDBACK AMPLIFIER S R Q VFB 1.25V ENABLE COLLAPSE DETECT LT3825 FEEDBACK AMP FB – + VC VIN PRIMARY FLYBACK SECONDARY MP T1VFLBK MS CVC

3825 FFA

tON(MIN) ENABLE DELAY MIN ENABLE FEEDBACK AMPLIFIER ENABLED PG DELAY 3825 TD VFLBK 0.8 • VFLBK

The L T3825 is a current mode switcher controller IC de- signed specifi cally for use in an isolated fl yback topology employing synchronous rectifi cation. The L T3825 operation is similar to traditional current mode switchers. The major difference is that output voltage feedback is derived via sensing the output voltage through the transformer . This precludes the need of an optoisolator in isolated designs greatly improving dynamic response and reliability. The L T3825 has a unique feedback amplifi er that samples a transformer winding voltage during the fl yback period and uses that voltage to control output voltage. The internal blocks are similar to many current mode controllers. The differences lie in the fl yback feedback amplifi er and load compensation circuitry. The logic block also contains circuitry to control the special dynamic requirements of fl yback control. For more information on the basics of current mode switcher/controllers and isolated fl yback converters see Application Note 19. Feedback Amplifi er—Pseudo DC Theory For the following discussion refer to the simplifi ed Fly- back Feedback Amplifi er diagram. When the primary side MOSFET switch MP turns off, its drain voltage rises above the V IN rail. Flyback occurs when the primary MOSFET is off and the synchronous secondary MOSFET is on. Dur- ing fl yback the voltage on nondriven transformer pins is determined by the secondary voltage. The amplitude of this fl yback pulse as seen on the third winding is given as: V VI E S R R NFLBK OUT SEC DS ON SF ++ ()• () RDS(ON) = on resistance of the synchronous MOSFET MS ISEC = transformer secondary current ESR = impedance of secondary circuit capacitor , winding and traces NSF = transformer effective secondary-to-feedback winding turns ratio (i.e., NS/NFLBK) The fl yback voltage is scaled by an external resistive divider R1/R2 and presented at the FB pin. The feedback amplifi er compares the voltage to the internal bandgap reference. The feedback amp is actually a transconductance ampli- fi er whose output is connected to V C only during a period in the fl yback time. An external capacitor on the V C pin integrates the net feedback amp current to provide the control voltage to set the current mode trip point. The regulation voltage at the FB pin is nearly equal to the bandgap reference V FB because of the high gain in the overall loop. The relationship between V FLBK and V FB is expressed as: V RR R VFLBK FB= +12 2 • Combining this with the previous VFLBK expression yields an expression for VOUT in terms of the internal reference, programming resistors and secondary resistances: VOUT = R1+ R2

• VFB •NSF –ISEC •E S R + RDS(ON)() The effect of nonzero secondary output impedance is dis- cussed in further detail; see Load Compensation Theory. The practical aspects of applying this equation for V OUT are found in the Applications Information. Feedback Amplifi er Dynamic Theory So far , this has been a pseudo-DC treatment of fl yback feedback amplifi er operation. But the fl yback signal is a pulse, not a DC level. Provision must be made to enable the fl yback amplifi er only when the fl yback pulse is present. This is accomplished by the “Enable” line in the diagram. Timing signals are then required to enable and disable the fl yback amplifi er . There are several timing signals which are required for proper L T3825 operation. Please refer to the Timing Diagram. Minimum Output Switch On Time (t ON(MIN)) The L T3825 affects output voltage regulation via fl yback pulse action. If the output switch is not turned on, there is no fl yback pulse and output voltage information is not available. This causes irregular loop response and start-up/latch-up problems. The solution is to require the primary switch to be on for an absolute minimum time per each oscillator cycle. If the output load is less than

that developed under these conditions, forced continuous operation normally occurs. See Applications Information for further details. Enable Delay (ENDL Y) The fl yback pulse appears when the primary side switch shuts off. However , it takes a fi nite time until the trans- former primary side voltage waveform represents the output voltage. This is partly due to rise time on the pri- mary side MOSFET drain node but, more importantly, is due to transformer leakage inductance. The latter causes a voltage spike on the primary side, not directly related to output voltage. Some time is also required for internal settling of the feedback amplifi er circuitry. In order to maintain immunity to these phenomena, a fi xed delay is introduced between the switch turn-off command and the enabling of the feedback amplifi er . This is termed “enable delay.” In certain cases where the leakage spike is not suffi ciently settled by the end of the enable delay period, regulation error may result. See Applications Information for further details. Collapse Detect Once the feedback amplifi er is enabled, some mechanism is then required to disable it. This is accomplished by a collapse detect comparator , which compares the fl yback voltage (FB referred) to a fi xed reference, nominally 80% of V FB. When the fl yback waveform drops below this level, the feedback amplifi er is disabled. Minimum Enable Time The feedback amplifi er , once enabled, stays enabled for a fi xed minimum time period termed “minimum enable time.” This prevents lockup, especially when the output voltage is abnormally low; e.g., during start-up. The mini- mum enable time period ensures that the V C node is able to “pump up” and increase the current mode trip point to the level where the collapse detect system exhibits proper operation. This time is set internally. Effects of Variable Enable Period The feedback amplifi er is enabled during only a portion of the cycle time. This can vary from the fi xed minimum enable time described to a maximum of roughly the “off” switch time minus the enable delay time. Certain parameters of feedback amp behavior are directly affected by the variable enable period. These include effective transconductance and V C node slew rate. Load Compensation Theory The L T3825 uses the fl yback pulse to obtain information about the isolated output voltage. An error source is caused by transformer secondary current fl ow through the synchronous MOSFET R DS(ON) and real life nonzero impedances of the transformer secondary and output capacitor . This was represented previously by the ex- pression “I SEC • (ESR + RDS(ON)).” However , it is gener- ally more useful to convert this expression to effective output impedance. Because the secondary current only fl ows during the off portion of the duty cycle (DC), the effective output impedance equals the lumped secondary impedance divided by OFF time DC. Since the OFF time duty cycle is equal to 1 – DC then: R ESR R DCS OUT DS ON where: R S(OUT) = effective supply output impedance DC = duty cycle R DS(ON) and ESR are as defi ned previously This impedance error may be judged acceptable in less critical applications, or if the output load current remains relatively constant. In these cases the external FB resistive divider is adjusted to compensate for nominal expected error . In more demanding applications, output impedance error is minimized by the use of the load compensation function. Figure 1 shows the Block Diagram of the load compensation function. Switch current is converted to a voltage by the external sense resistor , averaged and lowpass fi ltered by the internal 50k resistor R CMPF and the external capacitor on CCMP . This voltage is impressed across the external RCMP resistor by op amp A1 and transistor Q3 producing a current at the collector of Q3 that is subtracted from the

tain output voltage regulation as output loading increases. output voltage, compensating for the IR drops.

3825 F01

Figure 1. Load Compensation Diagram

• R 1•NSF thus : ΔVOUT ΔIOUT = K1• RSENSE RCMP
• R 1•NSF where: K1 = dimensionless variable related to V IN, VOUT and effi ciency as explained above RSENSE = external sense resistor Nominal output impedance cancellation is obtained by equating this expression with RS(OUT): K R R RN ESR R DC SENSE CMP SF DS ON11 1•• • – ()= Solving for RCMP gives: RK RD C ESR R RNCMP SENSE DS ON SF= () The practical aspects of applying this equation to determine an appropriate value for the RCMP resistor are found in the Applications Information.

T ransformer design/specifi cation is the most critical part of a successful application of the L T3825. The following sections provide basic information about designing the transformer and potential tradeoffs. If you need help, the L TC Applications group is available to assist in the choice and/or design of the transformer . Turns Ratios The design of the transformer starts with determining duty cycle (DC). DC impacts the current and voltage stress on the power switches, input and output capacitor RMS cur- rents and transformer utilization (size vs power). The ideal turns ratio is: N V V DC DCIDEAL OUT IN = • –1 Avoid extreme duty cycles as they, in general, increase current stresses. A reasonable target for duty cycle is 50% at nominal input voltage. For instance, if we wanted a 48V to 5V converter at 50% DC then: NIDEAL ==5 10 5 96• –. In general, better performance is obtained with a lower turns ratio. A DC of 45.5% yields a 1:8 ratio. Note the use of the external feedback resistive divider ratio to set output voltage provides the user additional freedom in selecting a suitable transformer turns ratio. Turns ratios that are the simple ratios of small integers; e.g., 1:1, 2:1, 3:2 help facilitate transformer construction and improve performance. When building a supply with multiple outputs derived through a multiple winding transformer , lower duty cycle can improve cross regulation by keeping the synchronous rectifi er on longer , and thus, keep secondary windings coupled longer . For a multiple output transformer , the turns ratio between output windings is critical and affects the accuracy of the voltages. The ratio between two output voltages is set with the formula V OUT2 = VOUT1 • N21 where N21 is the turns ratio between the two windings. Also keep the secondary MOSFET R DS(ON) small to improve cross regulation. The feedback winding usually provides both the feedback voltage and power for the L T3825. So set the turns ratio between the output and feedback winding to provide a rectifi ed voltage that under worst-case conditions is greater than the 11V maximum V CC turn-off voltage. NSF > VOUT 11+ VF For our example: NSF > 5 11+ 0.7 = 1 2.34 We will choose 1 Leakage Inductance T ransformer leakage inductance (on either the primary or secondary) causes a spike after the primary side switch turn-off. This is increasingly prominent at higher load currents, where more stored energy is dissipated. Higher fl yback voltage may break down the MOSFET switch if it has too low a BV DSS rating. One solution to reducing this spike is to use a snubber circuit to suppress the voltage excursion. However , sup- pressing the voltage extends the fl yback pulse width. If the fl yback pulse extends beyond the enable delay time, output voltage regulation is affected. The feedback system has a deliberately limited input range, roughly ±50mV re- ferred to the FB node. This rejects higher voltage leakage spikes because once a leakage spike is several volts in amplitude, a further increase in amplitude has little effect on the feedback system. Therefore, it is advisable to arrange the snubber circuit to clamp at as high a voltage as possible, observing MOSFET breakdown, such that leakage spike duration is as short as possible. Application Note 19 provides a good reference on snubber design.

As a rough guide, leakage inductance of several percent (of mutual inductance) or less may require a snubber , but exhibit little to no regulation error due to leakage spike behavior . Inductances from several percent up to perhaps ten percent cause increasing regulation error . Avoid double digit percentage leakage inductances as there is a potential for abrupt loss of control at high load current. This curious condition potentially occurs when the leakage spike becomes such a large portion of the fl yback waveform that the processing circuitry is fooled into thinking that the leakage spike itself is the real fl yback signal! It then reverts to a potentially stable state whereby the top of the leakage spike is the control point, and the trailing edge of the leakage spike triggers the collapse detect circuitry. This typically reduces the output voltage abruptly to a fraction, roughly one-third to two-thirds of its correct value. Once load current is reduced suffi ciently, the system snaps back to normal operation. When using transformers with considerable leakage inductance, exercise this worst-case check for potential bistability: 1. Operate the prototype supply at maximum expected load current. 2. Temporarily short circuit the output. 3. Observe that normal operation is restored. If the output voltage is found to hang up at an abnormally low value, the system has a problem. This is usually evident by simultaneously viewing the primary side MOSFET drain voltage to observe fi rsthand the leakage spike behavior . A fi nal note—the susceptibility of the system to bistable behavior is somewhat a function of the load current/volt- age characteristics. A load with resistive—i.e., I = V/R behavior—is the most apt to be bistable. Capacitive loads that exhibit I = V 2/R behavior are less susceptible. Secondary Leakage Inductance Leakage inductance on the secondary forms an inductive divider on the transformer secondary, reducing the size of the feedback fl yback pulse. This increases the output voltage target by a similar percentage. Note that unlike leakage spike behavior , this phenomenon is independent of load. Since the secondary leakage in- ductance is a constant percentage of mutual inductance (within manufacturing variations), the solution is to adjust the feedback resistive divider ratio to compensate. Winding Resistance Effects Primary or secondary winding resistance acts to reduce overall effi ciency (P OUT/PIN). Secondary winding resistance increases effective output impedance degrading load regu- lation. Load compensation can mitigate this to some extent but a good design keeps parasitic resistances low. Bifi lar Winding A bifi lar or similar winding is a good way to minimize troublesome leakage inductances. Bifi lar windings also improve coupling coeffi cients and thus improve cross regulation in multiple winding transformers. However , tight coupling usually increases primary-to-secondary capacitance and limits the primary-to-secondary break- down voltage, so it isn’t always practical. Primary Inductance The transformer primary inductance, L P , is selected based on the peak-to-peak ripple current ratio (X) in the trans- former relative to its maximum value. As a general rule, keep X in the range of 20% to 40% ripple current (i.e., X = 0.2 to 0.4). Higher values of ripple will increase conduction losses, while lower values will require larger cores. APPLICATIONS INFORMATION

Ripple current and percentage ripple is largest at minimum duty cycle; in other words, at the highest input voltage. L P is calculated from: L VD C fX P V P IN MAX MIN OSC MAX IN IN MAX= () =() () • DDC Eff fX P MIN OSC MAX OUT where: f OSC is the oscillator frequency DC MIN is the DC at maximum input voltage X MAX is ripple current ratio at maximum input voltage For a 48V (VIN = 36V to 72V) to 5V/8A converter with 90% effi ciency, POUT = 40W and PIN = 44.44W . Using X = 0.4 and fOSC = 200kHz: DCMIN = 1 1+ N•V IN(MAX) VOUT = 1 1+ 1 8 • 72 = 35.7% LP = 72V • 0.357() 200kHz • 0.4 • 44.44W = 186μH Optimization might show that a more effi cient solution is obtained at higher peak current but lower inductance and the associated winding series resistance. A simple spreadsheet program is useful for looking at tradeoffs. T ransformer Core Selection Once L P is known, the type of transformer is selected. High effi ciency converters use ferrite cores to minimize core loss. Actual core loss is independent of core size for a fi xed inductance, but decreases as inductance increases. Since increased inductance is accomplished through more turns of wire, copper losses increase. Thus transformer design balances core and copper losses. Remember that increased winding resistance will degrade cross regulation and in- crease the amount of load compensation required. The main design goals for core selection are reducing copper losses and preventing saturation. Ferrite core material saturates hard, rapidly reducing inductance when the peak design current is exceeded. This results in an abrupt increase in inductor ripple current and, con- sequently, output voltage ripple. Do not allow the core to saturate! The maximum peak primary current occurs at minimum V IN: IPK = PIN VIN(MIN) •D CMAX

• 1 + XMIN now : DCMAX = 1 1+ N•V IN(MIN) VOUT = 1 1+ 1 8 • 36 = 52.6% XMIN = VIN(MIN) •D CMAX() fOSC •L P •PIN = 36 • 52.6%() 200kHz •186 μH • 44.44 = 0.202 Using the example numbers leads to: IPK = 44.44W 36 • 0.52 6
• 1 + 0.202 = 2.58A Multiple Outputs One advantage that the fl yback topology offers is that ad- ditional output voltages can be obtained simply by adding windings. Designing a transformer for such a situation is beyond the scope of this document. For multiple windings, realize that the fl yback winding signal is a combination of activity on all the secondary windings. Thus load regulation is affected by each windings load. Take care to minimize cross regulation effects. APPLICATIONS INFORMATION

Setting Feedback Resistive Divider The expression for VOUT developed in the Operation sec- tion is rearranged to yield the following expression for the feedback resistors: R1= R2 VOUT +ISEC •E S R + RDS(ON)() VFB •N SF Continuing the example, if ESR + R DS(ON) = 8mΩ, R2 = 3.32k, then: R1= 3.4k 5 + 8 • 0.008 1.232 •1/ 3 = 37.6k choose 37.4k. It is recommended that the Thevenin impedance of the resistive divider (R1||R2) is roughly 3k for bias current cancellation and other reasons. Current Sense Resistor Considerations The external current sense resistor is used to control peak primary switch current, which controls a number of key converter characteristics including maximum power and external component ratings. Use a noninductive current sense resistor (no wire-wound resistors). Mounting the resistor directly above an unbroken ground plane con- nected with wide and short traces keeps stray resistance and inductance low. The dual sense pins allow for a fully Kelvined connection. Make sure that SENSE + and SENSE– are isolated and con- nect close to the sense resistor to preserve this. Peak current occurs at 98mV of sense voltage VSENSE. So the nominal sense resistor is VSENSE/IPK. For example, a peak switch current of 10A requires a nominal sense resistor of 0.010Ω. Note that the instantaneous peak power in the sense resistor is 1W , and that it is rated accordingly. The use of parallel resistors can help achieve low resistance, low parasitic inductance and increased power capability. Size R SENSE using worst-case conditions, minimum L P , VSENSE and maximum VIN. Continuing the example, let us assume that our worst-case conditions yield an IPK 40% above nominal so IPK = 3.64A . If there is a 10% tolerance on RSENSE and minimum VSENSE = 80mV , then RSENSE • 110% = 80mV/3.64A and nominal RSENSE = 20mΩ. Round to the nearest available lower value. Selecting the Load Compensation Resistor The expression for R CMP was derived in the Operation section as: RK RD C ESR R RN RCMP SENSE DS ON SF= () SS OUT() Continuing the example: K1= VOUT VIN •Ef f = 5 48 • 90% = 0.116 If ESR + RDS(ON) = 8m

• 37.4k = 1.96k This value for RCMP is a good starting point, but empiri- cal methods are required for producing the best results. This is because several of the required input variables are diffi cult to estimate precisely. For instance, the ESR term above includes that of the transformer secondary, but its effective ESR value depends on high frequency behavior , not simply DC winding resistance. Similarly, K1 appears as a simple ratio of V IN to V OUT times (differential) ef- fi ciency, but theoretically estimating effi ciency is not a simple calculation. The suggested empirical method is as follows: 1. Build a prototype of the desired supply including the actual secondary components. 2. Temporarily ground the C CMP pin to disable the load compensation function. Measure output voltage while sweeping output current over the expected range. Approximate the voltage variation as a straight line, ΔV OUT/ΔIOUT = RS(OUT). 3. Calculate a value for the K1 constant based on VIN, VOUT and the measured effi ciency. APPLICATIONS INFORMATION

1. Verify this result by connecting a resistor of this value

from the RCMP pin to ground.

1. Disconnect the ground short to CCMP and connect a 0.1μF

in place. RS(OUT) should have decreased signifi cantly. load compensation (from step 2). the sync pulse width greater than 500ns. time, enable delay time and primary MOSFET turn-on delay. optimizing these timing values. that there is always a signal to close the loop. The L T3825 does not employ cycle skipping at light loads.

3825 F02

Figure 2. fOSC vs OSC Capacitor Values

The tON(MIN) resistor is set with the following equation: RtON(MIN) (kΩ) = tON(MIN)(ns) – 104 1.063 Keep RtON(MIN) greater than 70k. A good starting value is 160k. Enable Delay Time (ENDL Y) Enable delay time provides a programmable delay between turn-off of the primary gate drive node and the subsequent enabling of the feedback amplifi er . As discussed earlier , this delay allows the feedback amplifi er to ignore the leakage inductance voltage spike on the primary side. The worst-case leakage spike pulse width is at maximum load conditions. So set the enable delay time at these conditions. While the typical applications for this part use forced continuous operation, it is conceivable that a secondary- side controller might cause discontinuous operation at light loads. Under such conditions the amount of energy stored in the transformer is small. The fl yback waveform becomes “lazy” and some time elapses before it indicates the actual secondary output voltage. The enable delay time should be made long enough to ignore the “irrelevant” portion of the fl yback waveform at light load. Even though the L T3825 has a robust gate drive, the gate transition time slows with very large MOSFETs. Increase delay time as required when using such MOSFETs. The enable delay resistor is set with the following equation: RENDLY (kΩ) = tENDLY (ns) – 30 2.616 Keep RENDL Y greater than 40k. A good starting point is 56k. Primary Gate Delay Time (PGDL Y) Primary gate delay is the programmable time from the turn-off of the synchronous MOSFET to the turn-on of the primary side MOSFET . Correct setting eliminates overlap between the primary side switch and secondary side synchronous switch(es) and the subsequent current spike in the transformer . This spike will cause additional component stress and a loss in regulator effi ciency. The primary gate delay resistor is set with the following equation: RPGDLY (kΩ) = tPGDLY (ns)+ 47 9.01 A good starting point is 27k. Soft-Start Functions The L T3825 contains an optional soft-start function that is enabled by connecting an external capacitor between the SFST pin and ground. Internal circuitry prevents the control voltage at the V C pin from exceeding that on the SFST pin. There is an initial pull-up circuit to quickly bring the SFST voltage to approximately 0.8V . From there it charges to approximately 2.8V with a 20μA current source. The SFST node is discharged to 0.8V when a fault occurs. A fault is V CC too low (undervoltage lockout), current sense voltage greater than 200mV or the IC’s thermal (over tem- perature) shutdown is tripped. When SFST discharges, the V C node voltage is also pulled low to below the minimum current voltage. Once discharged and the fault removed, the SFST recharges up again. In this manner , switch currents are reduced and the stresses in the converter are reduced during fault conditions. The time it takes to fully charge soft-start is: tSS = CSFST • 1.4V 20μA =70ms • CSFST (μF) UVLO Pin Function The UVLO pin provides a user programming undervoltage lockout. This is typically used to provide undervoltage lockout based on V IN. The gate drivers are disabled when UVLO is below the 1.24V UVLO threshold. An external resistive divider between the input supply and ground is used to set the turn-on voltage. APPLICATIONS INFORMATION

the hysteresis produced from the change in bias current. put more of the resistance on the UVLO side. converter effi ciency but is not inherently self-starting.

3825 F03

3825 F04

Figure 4. Typical Power Bootstrapping

than the minimum rated L T3825 supply current. never attain this clamp voltage. frequency pole and is usually sized at 0.1 times CVC.

3825 F05

Figure 5. VC Compensation Network VC pin ripple is generally not an issue with the L T3825.

next cycle. This action naturally holds the VC voltage stable during the current comparator sense action (current mode switching). AN19 provides a method for empirically tweaking frequency compensation. Basically it involves introducing a load current step and monitoring the response. Slope Compensation This part incorporates current slope compensation. Slope compensation is required to ensure current loop stability when the DC is greater than 50%. In some switcher con- trollers, slope compensation reduces the maximum peak current at higher duty cycles. The L T3825 eliminates this problem by having circuitry that compensates for the slope compensation so that maximum current sense voltage is constant across all duty cycles. Minimum Load Considerations At light loads, the L T3825 derived regulator goes into forced continuous conduction mode. The primary side switch always turns on for a short time as set by the t ON(MIN) resistor . If this produces more power than the load requires, power will fl ow back into the primary during the “off” period when the synchronization switch is on. This does not produce any inherently adverse problems, though light load effi ciency is reduced. Maximum Load Considerations The current mode control uses the V C node voltage and amplifi ed sense resistor voltage as inputs to the current comparator . When the amplifi ed sense voltage exceeds the V C node voltage, the primary side switch is turned off. In normal use, the peak switch current increases while FB is below the internal reference. This continues until V C reaches its 2.56V clamp. At clamp, the primary side MOSFET will turn off at the rated 98mV VSENSE level. This repeats on the next cycle. It is possible for the peak primary switch currents as referred across R SENSE to exceed the max 98mV rating because of the minimum switch on time blanking. If the voltage on V SENSE exceeds 206mV after the minimum turn-on time, the SFST capacitor is discharged, causing the discharge of the V C capacitor . This then reduces the peak current on the next cycle and will reduce overall stress in the primary switch. Short-Circuit Conditions Loss of current limit is possible under certain conditions such as an output short circuit. If the duty cycle exhib- ited by the minimum on time is greater than the ratio of secondary winding voltage (referred-to-primary) divided by input voltage, then peak current is not controlled at the nominal value. It ratchets up cycle-by-cycle to some higher level. Expressed mathematically, the requirement to maintain short-circuit control is: DC t f IR R VNMIN ON MIN OSC SC SEC DS ON IN +() ()•

• SSP where: t ON(MIN) = primary side switch minimum on time I SC = short-circuit output current NSP = secondary-to-primary turns ratio (N SEC/NPRI) Other variables as previously defi ned T rouble is typically encountered only in applications with a relatively high product of input voltage times secondary- to-primary turns ratio and/or a relatively long minimum switch on time. Additionally, several real world effects such as transformer leakage inductance, AC winding losses, and output switch voltage drop combine to make this simple theoretical calculation a conservative estimate. Prudent design evaluates the switcher for short-circuit protection and adds any additional circuitry to prevent destruction. APPLICATIONS INFORMATION

Output Voltage Error Sources The L T3825’s feedback sensing introduces additional sources of errors. The following is a summary list. The internal bandgap voltage reference sets the reference voltage for the feedback amplifi er . The specifi cations detail its variation. The external feedback resistive divider ratio proportional directly affects regulated voltage. Use 1% components. Leakage inductance on the transformer secondary reduces the effective secondary-to-feedback winding turns ratio S/NF) from its ideal value. This increases the output volt- age target by a similar percentage. Since secondary leakage inductance is constant from part to part (with a tolerance) adjust the feedback resistor ratio to compensate. The transformer secondary current fl ows through the im- pedances of the winding resistance, synchronous MOSFET R DS(ON) and output capacitor ESR. The DC equivalent current for these errors is higher than the load current because conduction occurs only during the converter’s “off” time. So divide the load current by (1 – DC). If the output load current is relatively constant, the feedback resistive divider is used to compensate for these losses. Otherwise, use the L T3825 load compensation circuitry (see Load Compensation). If multiple output windings are used, the fl yback winding will have a signal that represents an amalgamation of all these windings impedances. Take care that you examine worst- case loading conditions when tweaking the voltages. Power MOSFET Selection The power MOSFETs are selected primarily on the criteria of “on” resistance R DS(ON), input capacitance, drain-to- source breakdown voltage (BVDSS), maximum gate voltage (VGS) and maximum drain current (ID(MAX)). For the primary-side power MOSFET , the peak current is: IPK(PRI) = PIN VIN(MIN)•D CMAX

• 1 + XMIN where X MIN is peak-to-peak current ratio as defi ned earlier . For each secondary-side power MOSFET , the peak current is: IPK(SEC) = IOUT 1–DC MAX
• 1 + XMIN Select a primary-side power MOSFET with a BVDSS greater than: BVDSS ≥IPK LLKG CP + VIN(MAX) + VOUT(MAX) NSP where NSP refl ects the turns ratio of that secondary-to-pri- mary winding. LLKG is the primary-side leakage inductance and CP is the primary-side capacitance (mostly from the COSS of the primary-side power MOSFET). A snubber may be added to reduce the leakage inductance as discussed earlier . For each secondary-side power MOSFET , the BV DSS should be greater than: BV DSS ≥ VOUT + VIN(MAX) • NSP Choose the primary side MOSFET RDS(ON) at the nominal gate drive voltage (7.5V). The secondary side MOSFET gate drive voltage depends on the gate drive method. Primary side power MOSFET RMS current is given by: I P VD CRMS PRI IN IN MIN MAX APPLICATIONS INFORMATION

loss, but is not directly specifi ed on the data sheets. on most MOSFET data sheets (Figure 6).

3825 F06QB

Figure 6. Gate Charge Curve (gate-to-drain) capacitance as the drain voltage drops.

• RDR • CMILLER VGATE(MAX) –V TH
• f OSC where: R DR is the gate driver resistance (≈10Ω) V TH is the MOSFET gate threshold voltage f OSC is the operating frequency V GATE(MAX) = 7.5V for this part (1 + δ) is generally given for a MOSFET in the form of a normalized RDS(ON) vs temperature curve. If you don’t have a curve, use δ = 0.005/°C • ΔT for low voltage MOSFETs. The secondary-side power MOSFETs typically operate at substantially lower VDS, so you can neglect transition losses. The dissipation is calculated using: P D(SEC) = IRMS(SEC)2 • RDS(ON)(1 + δ) With power dissipation known, the MOSFETs’ junction temperatures are obtained from the equation: T J = TA + PD • θJA where TA is the ambient temperature and θJA is the MOSFET junction to ambient thermal resistance. Once you have TJ, iterate your calculations recomputing δ and power dissipations until convergence. Gate Drive Node Consideration The PG and SG gate drivers are strong drives to minimize gate drive rise and fall times. This improves effi ciency but the high frequency components of these signals can cause problems. Keep the traces short and wide to reduce parasitic inductance. The parasitic inductance creates an LC tank with the MOSFET gate capacitance. In less than ideal layouts, a series resistance of 5Ω or more may help to dampen the ringing at the expense of slightly slower rise and fall times and effi ciency. The L T3825 gate drives will clamp the max gate voltage to roughly 7.5V , so you can safely use MOSFETs with max V GS of 10V or larger .

application on the front page of this data sheet. to Application Note 19 for more information. fl yback converter are illustrated in Figure 7.

3825 F07

Figure 7. Typical Flyback Converter Waveforms

charging/discharging ΔV . This percentage ripple changes, depending on the requirements of the application. You can modify the equations below. For a 1% contribution to the total ripple voltage, the ESR of the output capacitor is determined by: ESRCOUT ≤1% • VOUT •1 – D CMAX() IOUT The other 1% is due to the bulk C component, so use: COUT ≥ IOUT 1% • VOUT •f OSC In many applications the output capacitor is created from multiple capacitors to achieve desired voltage ripple, reli- ability and cost goals. For example, a low ESR ceramic capacitor can minimize the ESR step, while an electrolytic capacitor satisfi es the required bulk C. Continuing our example, the output capacitor needs: ESRCOUT ≤1% • 5V • 1– 49%() = 3mΩ COUT ≥ 8A 1 %•5•2 0 0 k H z = 800μF These electrical characteristics require paralleling several low ESR capacitors possibly of mixed type. Most capacitor ripple current ratings are based on 2000 hour life. This makes it advisable to derate the capacitor or to choose a capacitor rated at a higher temperature than required. One way to reduce cost and improve output ripple is to use a simple LC fi lter . Figure 8 shows an example of the fi lter . The design of the fi lter is beyond the scope of this data sheet. However , as a starting point, use these general guide lines. Start with a C OUT 1/4 the size of the nonfi lter solution. Make C1 1/4 of C OUT to make the second fi lter pole independent of COUT . C1 may be best implemented with multiple ceramic capacitors. Make L1 smaller than the output inductance of the transformer . In general, a 0.1μH fi lter inductor is suffi cient. Add a small ceramic capacitor (C OUT2) for high frequency noise on V OUT. For those interested in more details refer to “Second-Stage LC Filter Design,” Ridley, Switching Power Magazine, July 2000, p8-10. Circuit simulation is a way to optimize output capacitance and fi lters, just make sure to include the component parasit- ics. L TC SwitcherCAD™ is a terrifi c free circuit simulation tool that is available at www.linear .com. Final optimization of output ripple must be done on a dedicated PC board. Parasitic inductance due to poor layout can signifi cantly impact ripple. Refer to the PC Board Layout section for more details. IC Thermal Considerations Take care to ensure that the L T3825 junction temperature does not exceed 125°C. Power is computed from the aver- age supply current, the sum of quiescent supply current CC in the specifi cations) plus gate drive currents. The primary gate drive current is computed as: f OSC • QG where QG is the total gate charge at max VGS (obtained from the gate charge curve) and f is the switching frequency. Since the synchronous driver is usually driving a capacitive load, the synchronous gate drive power dissipation is: f OSC • CS • VSGMAX where CS is the SG capacitive load and VSGMAX is the SG pin max voltage. RLOADCOUT2 1μF VOUT COUT 470μF 47μF FROM SECONDARY WINDING 0.1μH

3825 F08

SwitcherCAD is a trademark of Linear Technology Corporation.

VCC is the worst-case L T3825 supply voltage. capacitor carries high di/dt MOSFET gate drive currents. Use a low ESR ceramic capacitor . circuitry to prevent coupling between PCB planes. add a snubber or specify an avalanche-rated MOSFET .

3825 F09

Figure 9. High Current Paths

Place the small-signal components away from high frequency switching nodes. This allows the use of a pseudo-Kelvin connection for the signal ground, where high di/dt gate driver currents fl ow out of the IC ground pin in one direction (to the bottom plate of the V CC de- coupling capacitor) and small-signal currents fl ow in the other direction. Keep the trace from the feedback divider tap to the FB pin short to preclude inadvertent pickup. For applications with multiple switching power converters connected to the same input supply, make sure that the input fi lter capacitor for the L T3825 is not shared with other converters. AC input current from another converter could cause substantial input voltage ripple and this could interfere with the L T3825 operation. A few inches of PC trace or wire (L ≅ 100nH) between the C IN of the L T3825 and the actual source VIN is suffi cient to prevent current sharing problems. APPLICATIONS INFORMATION

48V to 5V at 8A Isolated Supply 100k12k VOUT+ 8AVIN+ 36V TO 72V 0.03Ω Si4490DY P6SMB100A MBRS1100 15k ALL CAPACITORS 25V UNLESS OTHERWISE NOTED T1: EDFD25-3F3 GAP FOR LP = 200μH (i.e., AL = 200nH/T2) 3.01k 20Ω 47μF 20V 47k 1/4W 0.1μF 29.4k 402k BAS21 2.1k 1% 100k 100k 680pF 10k 15Ω B0540W 47Ω 470μF 6TPE470MI FMMT718 FMMT618 10Ω 1/4W PA0184 BAT54 330Ω 47pF 2.2μF 100V 0.1μF 0.22μF 10nF 2.2nF0.1μF 1μF 0.1μF 2.2nF 250V Si7336ADP 1nF

3825 TA02a

UVLO SENSE– VC SENSE+ RCMP ENDL Y OSC L T3825 GND SFST SG FB VCC SG SG PG CCMP 123 PINS 1 TO 3, 32T OF 2 × 32AWG PINS 4 TO 5, 11T OF 1 × 32AWG PINS 1 TO 3, 32T OF 2 × 32AWG PINS 10, 11, 12 TO PINS 7, 8, 9, 4T OF 5 MIL COPPER FOIL PINS 1 TO 3, 32T OF 2 × 32AWG

2 MIL

Effi ciency vs Load Current LOAD CURRENT (A) EFFICIENCY (%)

3825 TA02b

Output Regulation vs Load Current LOAD CURRENT (A)

4.75 OUTPUT (V)

4.80 4.90 4.95 5.00 5.25 5.10 3 5 6

3825 TA02c

4.85 5.15 5.20 5.05 2 4 7 8 36VIN 72VIN 48VIN

48V to 3.3V at 6A Isolated Supply Effi ciency vs Load Current Output Regulation vs Load Current 100k15k VOUT+ 3.3V 6AVIN+ 36V TO 72V 0.04Ω Si4490DY Si7892DP 15k 3.01k 20Ω 47μF 20V 47k 1/4W 0.1μF 26.1k 402k BAS21 866Ω 1% 62k 10k 680pF 10k 15Ω B0540W 47Ω 150μF 6TPB150ML PA0184 BAT54 330Ω 47pF 0.82μF 100V 0.1μF 0.22μF 3.3nF 2.2nF0.1μF 1μF 0.1μF PULSE PB2134 2.2nF 250V

3825 TA03a

UVLO SENSE– VC SENSE+ RCMP ENDL Y OSC L T3825 GND SFST SG FB VCC SG SG PG CCMP 123 FMMT718 FMMT618 LOAD CURRENT (A) EFFICIENCY (%)

3825 TA03b

LOAD CURRENT (A) 3.38 3.43

3825 TA03c

3.33 3.28 234 6 3.23 3.18

48V to 5V at 12A Isolated Supply Effi ciency vs Load Current Output Regulation vs Load Current 100k12k 3.01k 28.7k 402k 20Ω 47Ω47k 1/4W BAS21 20Ω 100pF 250V 2.2μF 250V C1 TO C4 47μF ×3 470μF 0.1μH VOUT+ 3.3V 12A VIN+ 36V TO 72V T1 0.02Ω 1/2W 47μF Si4490DY 15k 750Ω 150k 10k C1 TO C4: TDK C3225X5R0J476M C5: SANYO 6TPD470M L1: VISHAY IHLP2525CZERR10M Q1: ZETEX FMMT618 Q2: ZETEX FMMT718 T1: PULSE PA1477NL 10k BAT54 B0540W 15Ω PA0184 330Ω 47pF 2.2μF 100V 0.1μF 0.01μF 1nF 10nF 2.2nF0.1μF

3825 TA04a

1μF tON SYNC PGDL Y UVLO SENSE– VC SENSE+ RCMP ENDL Y OSC L T3825 GND SFST SGFB VCC SG SG PG CCMP Si7336ADP LOAD CURRENT (A) EFFICIENCY (%) 3 7 9

3825 TA04b

LOAD CURRENT (A) 3.23 3.33 3.43 3.18 3.28 3.38 468 1 0

3825 TA04c

Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However , no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. PACKAGE DESCRIPTION 16-Lead Plastic TSSOP (4.4mm) (Reference L TC DWG # 05-08-1663) Exposed Pad Variation BC FE16 (BC) TSSOP 0204 0.09 – 0.20 (.0035 – .0079) 0° – 8° 0.25 REF 0.50 – 0.75 (.020 – .030) 4.30 – 4.50* (.169 – .177) 13 4 5 6 7 8 10 9 4.90 – 5.10* (.193 – .201) 16 1514 13 12 11 1.10 (.0433) MAX 0.05 – 0.15 (.002 – .006) 0.65 (.0256) BSC 2.94 (.116) 0.195 – 0.30 (.0077 – .0118) TYP 2RECOMMENDED SOLDER PAD LAYOUT 0.45 ±0.05

0.65 BSC

4.50 ±0.10 6.60 ±0.10 1.05 ±0.10 2.94 (.116) 3.58 (.141) 3.58 (.141) MILLIMETERS (INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.150mm (.006") PER SIDE NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS 2. DIMENSIONS ARE IN 3. DRAWING NOT TO SCALE SEE NOTE 4 4. RECOMMENDED MINIMUM PCB METAL SIZE FOR EXPOSED PAD ATTACHMENT 6.40 (.252) BSC

Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear .com © LINEAR TECHNOLOGY CORPORATION 2007 LT 0108 REV A • PRINTED IN USA RELATED PARTS PART NUMBER DESCRIPTION COMMENTS L T1424-5 Isolated Flyback Switching Regulator 5V Output Voltage, No Optoisolator Required L T1424-9 Isolated Flyback Switching Regulator 9V Output Voltage, Regulation Maintained Under Light Loads L T1425 Isolated Flyback Switching Regulator No Third Winding or Optoisolator Required L TC1698 Isolated Secondary Synchronous Rectifi er Controller Isolated Power Supplies, Contains Voltage Merging, Optocoupler Driver , Primary Synchronization Circuit L T1725 General Purpose High Power Isolated Flyback Controller Suitable for Telecom or Offl ine Input Voltage L T1737 High Power Isolated Flyback Controller Powered from a DC Supply Voltage L TC1871 Wide Input Range Current Mode No R SENSE™ Controller 50kHz to 1MHz, Boost, Flyback and SEPIC Topology L TC3710 Secondary Side Synchronous Post Regulator Generates a Regulated Auxiliary Output in Isolated DC/DC Converters. Dual N-Channel MOSFET Synchronous Drivers L T3781/L T1698 36V to 72V Input Isolated DC/DC Converter Chipset Synchronous Operation: Overvoltage/Undervoltage Protection, 10W to 100W Power Supply, 1/2 to 1/4 Brick Footprint L TC3803 SOT-23 Flyback Controller Adjustable Slope Compensation, Internal Soft-Start, 200kHz L TC3806 Synchronous Flyback DC/DC Controller Medium Power Multiple Outputs, 250kHz Soft-Start No R SENSE is a trademark of Linear Technology Corporation.