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3V TO 5.5V VIN CAP 0.47µF GATE GND FB ISP ISN 4.7µF 80.6k 10k 2 × 47µF 22µH 33m/uni03A9 PWMCK TTL/CMOS 2.048MHz CLOCK TTL/CMOS
3746 TA01
10µF 46.4k 10nF 60.4k 32.4k Typical applicaTion
DescripTion
Driver with Buck Controller The LT®3746 integrates a 32-channel LED driver with a 55V buck controller. The LED driver lights up to 30mA/13V of LEDs in series per channel, and the buck controller gener- ates an adaptive bus voltage supplying the parallel LED strings. Each channel has individual 6-bit dot correction current adjustment and 12-bit grayscale PWM dimming. Both dot correction and grayscale are accessible via a serial data interface in TTL/CMOS logic. The LT3746 performs full diagnostic and protection against open/short LED and overtemperature fault. The fault status is sent back through the serial data interface. The 30MHz fully-buffered, skew-balanced, cascadable serial data interface makes the chip extremely suitable for large screen LCD dynamic backlighting and mono-, multi-, full-color LED displays. 32-Channel LED Driver, 1MHz Buck, 3 LEDs 10mA to 30mA per Channel, 500Hz 12-Bit Dimming
FeaTures
applicaTions
n 6V to 55V Power Input Voltage Range n 32 Independent LED Outputs up to 30mA/13V n 6-Bit Dot Correction Current Adjustment n 12-Bit Grayscale PWM Dimming n 0.5µs Minimum LED On Time n Adaptive LED Bus Voltage for High Efficiency n Cascadable 30MHz Serial Data Interface n Full Diagnostic and Protection: Individual Open/Short LED an d Overtemperature Fault n Large Screen Display LED Backlighting n Mono-, Multi-, Full-Color LED Displays n LED Billboards and Signboards L, L T , L TC, L TM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.
pin conFiguraTionabsoluTe MaxiMuM raTings V to ISN + 1V SCKI, SCKO, SDI, SDO, LDI, LDO, PWMCK, SYNC, 3V to VCC Operating Junction Temperature Range (Notes 2, 3) °C to 125°C °C to 125°C (Note 1) 19 20 21 22 TOP VIEW GND UHH PACKAGE 56-LEAD (5mm × 9mm) PLASTIC QFN 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47
1 EN/UVLO
V CC PWMCK LDO SDO GND SCKO TJMAX = 125°C, θJA = 32°C/W, θ JC = 2.0°C/W EXPOSED PAD (PIN 57) IS GND, MUST BE SOLDERED TO PCB orDer inForMaTion LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LT3746EUHH#PBF LT3746EUHH#TRPBF 3746 56-Lead (5mm × 9mm) Plastic QFN –40°C to 125°C LT3746IUHH#PBF LT3746IUHH#TRPBF 3746 56-Lead (5mm × 9mm) Plastic QFN –40°C to 125°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
elecTrical characTerisTics
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Supply VIN VIN Operating Voltage l 6 55 V IVIN VIN Supply Current VEN/UVLO = 0V No Switching 0.2 0.4 0.55 µA mA VCC VCC Operating Voltage l 3 5.5 V IVCC VCC Supply Current (Note 4) VEN/UVLO = 0V LED Channel Off, 30MHz Data Off LED Channel On, 30MHz Data Off LED Channel On, 30MHz Data On 0.1 3.3 3.8 µA mA mA mA Undervoltage Lockout (UVLO) V CC UVLO Threshold VCC Rising VCC Falling 2.82 2.61 2.89 2.68 2.96 2.75 V V EN/UVLO Shutdown Threshold UVLO Threshold I VCC <20µA VEN/UVLO Rising VEN/UVLO Falling 0.35 1.28 1.19 1.31 1.22 1.34 1.25 V V V I EN/UVLO EN/UVLO Bias Current VEN/UVLO = VCC 0.1 1 µA (VIN – VCAP) UVLO Threshold (VIN – VCAP) Rising (VIN – VCAP) Falling 4.6 4.1 4.9 4.4 5.2 4.7 V V Soft Start (SS) I SS Soft Start Charge Current VSS = 1V –16 –12 –8 µA Soft Start Discharge Current VSS = VCC, VEN/UVLO = 1V 330 µA VSS(TH) Soft Start Reset Threshold 0.35 V Oscillator V RT RT Pin Voltage 1.186 1.205 1.224 V IRT RT Pin Current Limit VRT = 0V –80 µA fOSC Oscillator Frequency RT = 280k, VIN = 12V RT = 105k, VIN = 12V RT = 46.4k, VIN = 12V 196 490 1000 208 515 1050 220 540 1100 kHz kHz kHz fSYNC Sync Frequency Range (Note 5) RT = 348k, VIN = 12V 200 1000 kHz SYNC LOGIC High Level Voltage Low Level Voltage VIN = 12V, VCC = 3V to 5.5V 2.4 VCC 0.6 V V Error Amplifiers and Loop Dynamics VFB FB Regulation Voltage VISP = VISN = 5V l 1.186 1.210 1.234 V IFB FB Input Bias Current VISP = VISN = 5V, VFB Regulated –120 nA LED Regulation Voltage VISP = VISN = 5V, VFB = 1V 0.44 0.54 0.64 V TOFF(MIN) Minimum GATE Off Time VIN = 12V, VISP = VISN = 5V, VFB = 1V 120 ns TON(MIN) Minimum GATE On Time VIN = 12V, (VISP – VISN) = 60mV, VISN = 5V, VFB = 1V 200 ns Current Sense Amplifier ISP/ISN Pin Common Mode VISP = VISN l 0 13 V VIN to ISN Dropout Voltage (V IN – VISN) V IN = 12V, VISP = VISN, VFB = 1V l 1.7 2 V Current Limit Sense Threshold (VISP – VISN) V FB = 1V 34 46.5 59 mV IISP ISP Input Bias Current –23 µA IISN ISN Input Bias Current –48 µA The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T A = 25°C. VIN = 24V, VCC = 3.3V, VEN/UVLO = 1.5V, VFB = 1.5V, VISP = VISN = 0V, RT = 105k, RISET = 60.4k, CCAP = 0.47µF to VIN, unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Gate Driver VBIAS CAP Bias Voltage (V IN – VCAP) 7V < VIN < 55V 6.54 6.77 7.00 V ICAP CAP Bias Current Limit (VIN – VCAP) = VBIAS – 0.5V 22 mA GATE High Level (V IN – VGATE) IGATE = –100mA 0.4 V GATE Low Level (V GATE – VCAP) IGATE = 100mA 0.3 V GATE Rise Time CGATE = 3.3nF to VIN, VIN = 12V 30 ns GATE Fall Time CGATE = 3.3nF to VIN, VIN = 12V 30 ns LED Driver V ISET Trimmed ISET Pin Voltage l 1.181 1.205 1.229 V LEDxx Operating Voltage VISP = VISN = VLEDxx l 0 13 V LEDxx Leakage Current LED Channel Off, V ISP = VISN = 5V, VLEDxx = 3V 0.2 µA ILED LED Constant Sink Current VISP = VISN = 5V, VLEDxx = 0.5V REGDC = 0x00 REGDC = 0x20 REGDC = 0x3F 10.5 20.5 mA mA mA ∆ILEDC Current Mismatch Between Channels V ISP = VISN = 5V, VLEDxx = 0.5V, REGDC = 0x20 (Note 6) 8 15 % ∆ILEDD Current Mismatch Between Devices V ISP = VISN = 5V, VLEDxx = 0.5V, REGDC = 0x20 (Note 7) –15 5 20 % ∆ILINE LED Current Line Regulation VISP = VISN = 5V, VLEDxx = 0.5V, REGDC = 0x20, VCC = 3V to 5.5V (Note 8) –0.2 0.2 0.7 %/V ∆ILOAD LED Current Load Regulation VISP = VISN = 5V, REGDC = 0x20, VLEDxx = 0.5V to 2.5V (Note 9) –1 0.7 2 %/V VOPEN Open LED Threshold VISP = VISN = 5V, VLEDxx Falling 0.1 V VSHT Short LED Threshold VISP = VISN = 5V, VLEDxx Rising 3.65 3.9 4.15 V TLEDON Minimum LED On Time VISP = VISN = 5V, REGGS = 0x001 0.5 µs PWMCK LOGIC High Level Voltage Low Level Voltage VCC = 3V to 5.5V 2.4 VCC 0.6 V V Thermal Protection ITSET TSET Output Current VTSET = 1V l 19.0 19.8 20.6 µA TSET Over Temperature Threshold TA = 25°C 510 mV Serial Data Interface V SIH VSIL Single-Ended Input (Note 10) High Level Voltage Low Level Voltage VCC = 3V to 5.5V 2.4 VCC 0.6 V V I SI Single-Ended Input Current VCC = 3V to 5.5V, SI = VCC or GND –0.2 0.2 µA V SOH VSOL Single-Ended Output (Note 10) High Level Voltage Low Level Voltage VCC = 3V to 5.5V ISO = –1mA ISO = 1mA VCC – 0.1 0.1 V V V elecTrical characTerisTics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T A = 25°C. VIN = 24V, VCC = 3.3V, VEN/UVLO = 1.5V, VFB = 1.5V, VISP = VISN = 0V, RT = 105k, RISET = 60.4k, CCAP = 0.47µF to VIN, unless otherwise noted.
Table 1. Test Parameter Equations
- 100 (1) ∆ILEDD(%)=IOUTavg – IOUTcal IOUTcal
- 100 (2) IOUTcal =1000 • 1.205V RISET Ê ËÁ ˆ ¯˜ (3) ∆ILINE(% / V)= IOUTn VCC =5.5V –IOUTn VCC =3.0V IOUTn VCC =3.0V
- 100 2.5V (4) ∆ILOAD(% / V)= IOUTn VOUTn =2.5V –IOUTn VOUTn =0.5V IOUTn VOUTn =0.5V
- 100 2.0V (5)
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LT3746E is guaranteed to meet performance specifications from 0°C to 125°C junction temperature. Specifications over the –40°C to 125°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LT3746I is guaranteed over the full –40°C to 125°C operating junction temperature range. Note 3: This IC includes thermal shutdown protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 125°C when thermal shutdown protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability. Note 4: The V CC supply current with LED channel on highly depends on the LED current setting and LEDxx pin voltage; its test condition is RISET = 60.4k, REGDC = 0x3F, REGGS = 0xFFF, VISP = VISN = 5V, VLEDxx = 0.5V. The VCC supply current with serial data interface on highly depends on VCC supply voltage, serial data interface clock frequency, SCKO/SDO/LDO loading capacitance, and PWMCK clock frequency; its test condition is V CC = 3.3V, fSCKI = 30MHz, CSCKO = CSDO = CLDO = 27pF, fPWMCK = 409.6KHz. Note 5: The SYNC frequency must be higher than the RT programmed oscillator frequency, and is suggested to be around 20% higher. Any SYNC frequency higher than the suggested value may introduce sub-harmonic oscillation in the converter due to insufficient slope compensation. See Application Information section. Note 6: The Current Mismatch between Channels is calculated as Equation 1 in Table 1. Note 7: The Current Mismatch between Devices is calculated as Equations 2 and 3 in Table 1. Note 8: The LED Current Line Regulation is calculated as Equation 4 in Table 1. Note 9: The LED Current Load Regulation is calculated as Equation 5 in Table 1. Note 10: The specifications of single-ended input SI apply to SCKI, SDI, and LDI pins; the specifications of single-ended output SO apply to SCKO, SDO, and LDO pins.
Typical perForMance characTerisTics 200Hz Two-Level DC Dimming 200Hz Four-Level DC Dimming Adaptive LED Bus Voltage I Adaptive LED Bus Voltage II Adaptive LED Bus Voltage III Adaptive LED Bus Voltage IV 100Hz 8:1 GS Dimming 100Hz 4096:1 GS Dimming 500Hz 4096:1 GS Dimming TA = 25°C, unless otherwise noted. CIRCUIT OF FIGURE 7: DC31 = 0×20, GS31 = 0×200 VPWMCK 5V/DIV VLED31 2VDIV VOUT 2V/DIV ILED31 20mA/DIV 5ms/DIV 3746 G01 CIRCUIT OF FIGURE 7: DC 31 = 0×20, GS31 = 0×001 VPWMCK 5V/DIV VLED31 2VDIV VOUT 2V/DIV ILED31 20mA/DIV 500ns/DIV 3746 G02 CIRCUIT OF FIGURE 7: DC 31 = 0×20, GS31 = 0×001 VPWMCK 5V/DIV VLED31 2VDIV VOUT 2V/DIV ILED31 20mA/DIV 500ns/DIV 3746 G03 CIRCUIT OF FIGURE 7: (A) EN = 1, GS 31 = 0×FF; (B) EN = 1, DC31 = 0×3F; VSCKI 5V/DIV VLED31 2VDIV VOUT 2V/DIV ILED31 20mA/DIV 1ms/DIV (A) (B) (C) (A) (B) (C)
3746 G04
CIRCUIT OF FIGURE 7: (A) EN = 0, GS 31 = 0×FFF, (B) EN = 1, DC31 = 0×3F, VSCKI 5V/DIV VLED31 2VDIV VOUT 2V/DIV ILED31 20mA/DIV 0.5ms/DIV (A) (B) (C) (D)
3746 G05
CIRCUIT OF FIGURE 7: DC 00-31 = 0×3F, GS00-31 = 0×FFF ILOAD 0.5A/DIV IL 0.5A/DIV VOUT 0.2V/DIV 2ms/DIV 3746 G06 CIRCUIT OF FIGURE 7: DC 00-31 = 0×20, GS00-31 = 0×800 ILOAD 0.5A/DIV IL 0.5A/DIV VOUT 0.2V/DIV 2ms/DIV 3746 G07 CIRCUIT OF FIGURE 7: DC GS08-11 = 0×5FF, GS12-15 = 0×7FF, GS16-19 = 0×9FF, GS20-23 = 0×BFF, GS24-27 = 0×DFF, GS28-31 = 0×FFF ILOAD 0.5A/DIV IL 0.5A/DIV VOUT 0.2V/DIV 2ms/DIV 3746 G08 CIRCUIT OF FIGURE 7: DC GS08-15 = 0×7FF, DC16-23 = 0×1F, DC16-23 = 0×BFF, DC24-31 = 0×0F, GS24-31 = 0×FFF ILOAD 0.5A/DIV IL 0.5A/DIV VOUT 0.2V/DIV 2ms/DIV 3746 G09
Typical perForMance characTerisTics IVCC vs VCC – Shutdown Mode IVCC vs VCC – Channel Off, Data Off IVCC vs VCC – Channel On, Data Off IVCC vs VCC – Channel On, Data On VCC UVLO Threshold vs Temperature EN/UVLO UVLO Threshold vs Temperature Buck Efficiency Shutdown IVIN vs VIN Quiescent IVIN vs VIN EFFICIENCY (%) 100 0.1 0.2 0.3 LOAD CURRENT (A) 0.4
3746 G10
48VIN, 4VOUT at 200kHz 24VIN, 12VOUT at 1MHz 12VIN, 4VOUT at 500kHz IVIN (µA) 10 20 VIN (V)
3746 G11
T = 25°C T = 125°C T = –40°C
0.38 IVIN (mA)
0.39 0.41 0.40 0.42 0.43 10 20 V IN (V)
3746 G12
T = 25°C T = 125°C T = –40°C 3.0 IVCC (µA) 3.5 4.0 V CC (V)
3746 G13
4.5 5.0 5.5 T = 25°C T = 125°C T = –40°C –50 2.60 VCC (V)2.75 2.70 2.65 2.80 2.85 2.90 –25 25 50 75 100 1250 JUNCTION TEMPERATURE (°C)
3746 G17
UVLO– UVLO+ –50 1.20 VEN/UVLO (V) 1.26 1.24 1.22 1.28 1.30 1.32 –25 25 50 75 100 1250 JUNCTION TEMPERATURE (°C)
3746 G18
UVLO– UVLO+ TA = 25°C, unless otherwise noted. 3.0 3.05 IVCC (mA)3.25 3.20 3.15 3.10 3.35 3.30 3.40 3.45 3.5 4.0 V CC (V)
3746 G14
4.5 5.0 5.5 T = 25°C T = 125°C T = –40°C 3.0 9.95 IVCC (mA)10.15 10.10 10.05 10.00 10.25 10.20 10.30 10.35 3.5 4.0 V CC (V)
3746 G15
4.5 5.0 5.5 T = 25°C T = 125°C T = –40°C 3.0 IVCC (mA)21 3.5 4.0 V CC (V)
3746 G16
4.5 5.0 5.5 T = 25°C T = 125°C T = –40°C
Typical perForMance characTerisTics FB Regulation Voltage vs Load Current LED Regulation Voltage vs Load Current Soft-Start Charge Current I SS vs Temperature Current Sense Threshold ISP - VISN) vs VISN CAP Bias Voltage (V IN - VCAP) vs VIN CAP Bias Voltage (V IN - VCAP) vs ICAP (VIN - VCAP) UVLO Threshold vs Temperature Oscillator Frequency f OSC vs RT Oscillator Frequency f OSC vs Temperature –50
4.40 VIN - VCAP (V)
4.60 4.50 4.70 4.80 4.90 –25 25 50 75 100 1250 JUNCTION TEMPERATURE (°C)
3746 G19
UVLO– UVLO+ –50 480 fOSC (kHz)500 490 510 520 –25 25 50 75 100 1250 JUNCTION TEMPERATURE (°C)
3746 G21
1.198 VFB (V)
1.202 1.200 1.204 1.206 1.208 200 400 600 800 1000 LOAD CURRENT (mA)
3746 G22
0.48 VLEDxx (V)
0.49 0.50 0.51 0.52 200 400 600 800 1000 LOAD CURRENT (mA)
3746 G23
–50 –11.0 ISS (µA) –10.8 –10.6 –10.4 –10.0 –10.2 –25 0 25 50 75 100 125 JUNCTION TEMPERATURE (°C)
3746 G24
VISP -VISN (mV) 3 6 9 12 15 VISN (V)
3746 G25
T = 25°C T = 125°C T = –40°C TA = 25°C, unless otherwise noted. 20 60 100 180 220 260 fOSC (kHz) 400 200 600 800 1000 140 300 RT (k/uni03A9)
3746 G20
6.70 VIN -VCAP (V)
6.74 6.78 6.90 6.86 6.82 10 20 30 40 50 60 VIN (V)
3746 G26
T = 25°C T = 125°C T = –40°C
6.20 VIN -VCAP (V)
6.30 6.40 6.90 6.80 6.70 6.60 6.50 4 8 12 16 24 20 ICAP (mA)
3746 G27
T = 25°C T = 125°C T = –40°C
Typical perForMance characTerisTics LED Current I LED vs LED Voltage VLED LED Current Variation I LED vs Temperature Short LED Threshold vs V ISN TSET Current vs I SET Current TSET Threshold vs Temperature LED Current Derating vs Temperature VISET Pin Voltage vs Temperature Nominal LED Current vs R ISET LED Current I LED vs Dot Correction –50
1.200 VISET (V)
1.202 1.210 1.208 1.206 1.204 –25 0 25 50 75 100 125 JUNCTION TEMPERATURE (°C)
3746 G28
ILED (mA) 10 16 22 28 34 40 46 52 58 64 DOT CORRECTION +1
3746 G30
–50 ILED (mA) –25 0 25 50 75 100 125 JUNCTION TEMPERATURE (°C)
3746 G32
ITSET (µA) 4 8 12 16 20 IISET (µA)
3746 G34
–50 350 450
400 VTSET (mV)
–25 0 25 50 12575 100 JUNCTION TEMPERATURE (°C)
3746 G35
VLED (V) 4 8 12 16 VISN (V)
3746 G33
ILED (mA) V LED (V)
3746 G31
DC = 0×3F DC = 0×20 DC = 0×00 ILED (mA) 85 90 95 100 120105 110 115 JUNCTION TEMPERATURE (°C)
3746 G36
OT = 0 OT = 1 40 80 ILED (mA) 120 160 200 240 280 320 RISET (k/uni03A9)
3746 G29
TA = 25°C, unless otherwise noted.
EN/UVLO (Pin 1): Enable and Undervoltage Lockout (UVLO) Pin. The pin can accept a digital input signal to enable or disable the chip. Tie to 0.35V or lower to shut down the chip or tie to 1.34V or higher for normal operation. This pin can also be connected to V IN through a resistor divider to program a power input UVLO threshold. If both the enable and UVLO functions are not used, tie this pin to V CC pin. LED00 to LED31 (Pins 2-17, 30-45): LED Driver Output Pins. Connect the cathodes of LED strings to these pins. GND (Pin 18, 20, 27, 29): Ground Pin. SCKI (Pin 19): Serial Interface TTL/CMOS Logic Clock Input Pin. SDI (Pin 21): Serial Interface TTL/CMOS Logic Data Input Pin. LDI (Pin 22): Serial Interface TTL/CMOS Logic Latch Input Pin. An asynchronous input signal at this pin latches the serial data in the shift registers into the proper registers and the status information is ready to shift out with the coming clock pulses. See more details in the Operation section. V CC (Pin 23): Logic and Control Supply Pin. The pin powers serial data interface and internal control circuitry. Must be locally bypassed with a capacitor to ground. PWMCK (Pin 24): Grayscale PWM Dimming TTL/CMOS Logic Clock Pin. Individual PWM dimming signal is gener- ated by counting this clock pulse from zero to the bits in its 12-bit grayscale PWM register. LDO (Pin 25): Serial Interface TTL/CMOS Logic Latch Output Pin. SDO (Pin 26): Serial Interface TTL/CMOS Logic Data Output Pin. SCKO (Pin 28): Serial Interface TTL/CMOS Logic Clock Output Pin. SYNC (Pin 46): Switching Frequency Synchronization Pin. Synchronizes the internal oscillator frequency to an external clock applied to the SYNC pin. The SYNC pin is TTL/CMOS logic compatible. Tie to ground or V CC if not used. RT (Pin 47): Timing Resistor Pin. Programs the switching frequency from 200kHz to 1MHz. See Table 2 for the rec- ommended RT values for common switching frequencies. SS (Pin 48): Soft Start Pin. Placing a capacitor here pro- grams soft start timing to limit inductor inrush current during startup. The soft start cycle will not begin until all the V CC, EN/UVLO, and (V IN - VCAP) voltages are higher than their respective UVLO thresholds. FB (Pin 49): Feedback Pin. The pin is regulated to the internal bang-gap reference 1.205V during startup and precharging phases. Connect to a resistor divider from the buck converter output to program the maximum LED bus voltage. See more details in the Applications Informa- tion section. ISN (Pin 50): Negative Inductor Current Sense Pin. The pin is connected to one terminal of the external inductor current sensing resistor and the buck converter output supplying parallel LED channels. ISP (Pin 51): Positive Inductor Current Sense Pin. The pin is connected to the inductor and the other terminal of the external inductor current sensing resistor. CAP (Pin 52): V IN Referenced Regulator Supply Capacitor Pin. The pin holds the negative terminal of an internal VIN referenced 6.8V linear regulator used to bias the gate driver circuitry. Must be locally bypassed with a capacitor to VIN. GATE (Pin 53): Gate Driver Pin. The pin drives an external P-channel power MOSFET with a typical peak current of 1A. Connect this pin to the gate of the power MOSFET with a short and wide PCB trace to minimize trace inductance. V IN (Pin 54): Power Input Supply Pin. Must be locally bypassed with a capacitor to ground. T SET (Pin 55): Temperature Threshold Setting Pin. A resistor to ground programs overtemperature threshold. See more details in the Applications Information section. ISET (Pin 56): Nominal LED Current Setting Pin. A resistor to ground programs the nominal LED current for all the channels. See more details in the Applications Informa - tion section. Exposed Pad (Pin 57): Ground Pin. Must be soldered to a continuous copper ground plane to reduce die temperature and to increase the power capability of the device.
12µA EN/UVLO FB PWMCK LDI SDI OT STATUS INFO (FAULT LEDXX) x SCKI SCKI PRECHG VSS < 1V (VIN - VCAP) VIN VIN CIN RS L GATE CAP 6.8V 1.205V ISET TSET VPTATIREF OT UV 1.205V + REFERENCE BIAS AND UVLO RAMP OSC S R Q RT DRIVER GM1 CCAP COUT VOUT PG POR GM2 0.5V LED 00 LED01 LED31 EN + – – . . . –
25 LDO
(18, 20, 27, 29, EXPOSED PAD 57) RISET RTSET S R Q
The LT3746 integrates a single constant-frequency current- mode nonsynchronous buck controller with thirty-two linear current sinks. The buck controller generates an adaptive output LED bus voltage to supply parallel LED strings and the thirty-two linear current sinks regulate and modulate individual LED strings. Its operation is best understood by referring to the Block Diagram. Start-Up The LT3746 enters shutdown mode and drains almost zero current when the EN/UVLO pin is lower than 0.35V. Once the EN/UVLO pin is above 0.35V, the part starts to wake up internal bias currents, generate various references, and charge the capacitor C CAP towards 6.8V regulation voltage. This VIN referenced voltage regulator (VIN - VCAP) will supply the internal gate driver circuitry driving an external P-channel MOSFET in normal operation. The LT3746 remains in undervoltage lockout (UVLO) mode as long as any one of the EN/UVLO, V CC, and (VIN - VCAP) UVLO flags is high. Their UVLO thresholds are typically 1.31V, 2.89V, and 4.9V, respectively. After all the UVLO flags are cleared, the buck controller starts to switch, and the soft start SS pin is released and charged by a 12µA current source, thereby smoothly ramping up the inductor current and the output LED bus voltage. Power-on-Reset (POR) During start-up, an internal power-on-reset (POR) high signal blocks the input signals to the serial data interface and resets all the internal registers except the 386-bit shift register. The 1-bit frame select (FS) register, 1-bit enable LED channel (EN) register, individual 12-bit grayscale (GS) registers, and individual 6-bit dot correction (DC) registers are all reset to zero. Thus all the LED channels are turned off initially with the default grayscale (0x000) and dot correction (0x00) setting. Once the part completes its soft start (i.e., the SS pin voltage is higher than 1V) and the output LED bus voltage is power good (i.e., within 5% of its FB programmed regulation level), the POR signal goes low to allow the input signals to the serial data interface. Any fault triggering the soft start will generate another POR high signal and reset internal registers again. Serial Data Interface The LT3746 has a 30MHz, fully-buffered, skew-balanced, cascadable serial data interface. The interface uses a novel 6-wire (LDI, SCKI, SDI, LDO, SCKO, and SDO) topology and can be connected to microcontrollers, digital signal processors (DSPs), or field programmable gate arrays (FPGAs). In a conventional 4-wire topology shown in Figure 1, the LDI and SCKI signals need global routing while the SDI signal only needs local routing between chips. Depending on the number of chips in cascade and the size of system PCB board, external clock-tree type buffers with corresponding driving capability are needed for both the LDI and SCKI signals to minimize signal skews. The propagation delay caused by the buffer insertion on the SCKI signal yields the clock skew between the SCKI and SDI signals, which usually requires the customer end to balance it. Since both the SDI and SDO signals require the same SCKI signal to send and receive, the propagation delay between the SDI and SDO signals limits the number of chips in cascade and the series data interface clock frequency. The novel 6-wire topology eliminates the need for global routing and buffer insertion for the LDI and SCKI signals. Instead, it provides the LDO and SCKO signals along with the SDO signal to drive the next chip. The skew inside the chip among the LDI, SCKI, and SDI signals is balanced internally. The skew outside the chip among the LDO, SCKO, and SDO signals can be easily balanced by parallel routing these three signals between chips. The SDI signal is sent with the SCKI signal, and the SDO signal is received with the SCKO signal. A slight duty cycle change between the SCKI and SCKO signals may occur due to the process variation, supply voltage and operating temperature. This duty cycle change results from the difference in propagation delays of the positive and negative edges of the SCKI/SCKO signals and will affect the maximum number of cascadable chips, depending on the SCKI speed. In summary, the 6-wire topology extends the maximum number of cascadable chips, boosts the series data interface clock frequency, eliminates the need for buffer insertion for global signals, and offers an easy PCB layout. In a low-speed application with a small number of cascaded chips, the 6-wire topol- ogy can be simplified to the 4-wire topology by ignoring the LDO and SCKO outputs.
3746 F01
Figure 1. LT3746 6-Wire Topology vs Conventional 4-Wire Topology
386 BITS
3746 F02
Figure 2. Serial Data Frame Format
Figure 4. Grayscale PWM Dimming and Precharging Signal Timing Chart Figure 3. Serial Data Input and Output Timing Chart
3746 F04
3746 F03
3746 F05
as well as the individual 6-bit DC setting. registers to the 386-bit shift register at the same time. data at the SDI pin into the 386-bit shift register SR[0:385]. out with the coming clock cycles. Figure 5. Adaptive-Tracking-plus-Precharging LED Bus Voltage Technique
LED bus voltage VOUT will force a higher LED pin voltage across the current sink, thereby dissipating more power inside the part. See more details about the choice of the LED bus voltage and the power dissipation calculation in the Application Information section. Dot Correction and Grayscale Digital-to-Analog Conversion The resistor on the I SET pin programs the nominal LED current (4mA to 20mA) for all the channels. Individual LED channel can be adjusted to a different current setting by its own 6-bit dot correction register. The adjustable LED current ranges from 0.5X to 1.5X of the nominal LED current in 63 linear steps. See more details about setting nominal LED current and dot correction in the Applications Information section. In addition to the dot correction current adjustment, individual LED channels can also be modulated by their own grayscale PWM dimming signal. To achieve a better performance, all the grayscale PWM dimming signals are synchronized to the same frequency with no phase shift between rising edges. Each constant current sink is enabled or disabled when its grayscale PWM dimming signal goes high or low. This periodic grayscale PWM dimming signal is generated by its own 12-bit grayscale register with a duty cycle from 0/4096 to 4095/4096 and a period equal to 4096 PWMCK clock cycles. The generation of the grayscale PWM dimming signal is best understood by referring to Figure 4. After EN = 1 is set, the first rising edge of the PWMCK signal will in - crease the internal 12-bit grayscale counter from zero to one and turn on all the LED channels with grayscale value not zero. Each following rising edge of the PWMCK signal increases the grayscale counter by one. Any LED channel will be turned off when its 12-bit grayscale register value is equal to the value in the grayscale counter. To generate a 100% duty cycle for all the grayscale PWM dimming signals, the PWMCK signal can be paused before counting to the value in any individual 12-bit grayscale registers. Setting EN = 0 will reset the grayscale counter to zero and turn off all the LED channels immediately. Dual-Loop Analog OR Control The switching frequency can be programmed from 200kHz to 1MHz with the resistor connected to the RT pin and it can be synchronized to an external clock using the SYNC pin. Each switching cycle starts with the gate driver turning on the external P-channel MOSFET M1 and the inductor current is sampled through the sense resistor R S between the ISP and ISN pins. This current is amplified and added to a slope compensation ramp signal, and the resulting sum is fed into the positive terminal of the PWM comparator. When this voltage exceeds the level at the negative terminal of the PWM comparator, the gate driver turns off M1. The level at the negative terminal of the PWM comparator is set by either of two error amplifiers G and GM2. In this dual-loop analog OR control, the FB loop GM1 regulates the FB pin voltage to 1.205V and the LED loop GM2 regulates the minimum active LED pin voltage (LED00 to LED31) to 0.5V. In the startup phase, the GM2 is disabled and the output LED bus voltage is regulated towards the feedback resistor programmed LED bus volt- age. This FB programmed voltage defines the maximum LED bus voltage and should be programmed high enough to supply the worst case LED string across temperature, current, and manufacturing variation. Adaptive-T racking-Plus-Precharging Higher system efficiency and faster transient response are two highly anticipated specifications in an indi - vidually-modulated multi-channel LED driver chip. The LT3746 uses a patent pending adaptive-tracking- plus-precharging technique to achieve both of them simultaneously. Besides 32 internal grayscale PWM dimming signals, the part also generates another internal precharging signal PRECHG. As shown in Figure 4, the PRECHG signal divides any grayscale PWM dimming cycle into two phases: tracking phase when PRECHG = 0 and precharging phase when PRECHG = 1. During each grayscale PWM dimming cycle – 4096 PWMCK clock cycles, the PRECHG signal stays low for the first 3584 clock cycles (7/8 of the grayscale PWM dimming operaTion
signal will go high immediately. Figure 5. Each channel consists of a single LED with regulating the minimum active LED pin voltage to 0.5V. to a constant 4.4V output voltage.
Globally, the LT3746 converts a higher input voltage to a single lower LED bus voltage (VOUT) supplying 32 parallel LED strings with the adaptive-tracking-plus-precharging technique. Locally, the part regulates and modulates the current of each string to an independent dot correction and grayscale PWM dimming setting sent by TTL/CMOS logic serial data interface. This Application Information section serves as a guideline of selecting external components (refer to the Block Diagram) and avoiding common pitfalls for the typical application. Programming Maximum V OUT The adaptive-tracking-plus-precharging technique regu- lates VOUT to its maximum value during the startup and precharging phases, and adaptively lowers the voltage to keep the minimum active LED pin voltage around 0.5V during the tracking phase. Therefore, the maximum V OUT should be programmed high enough to keep all the LED pin voltages higher than 0.5V to maintain LED current regulation across temperature, current, and manufactur- ing variation. As a starting point, the maximum LED bus voltage, V OUT(MAX), can be calculated as: VOUT(MAX) =0.5V +n •VF(MAX) where n is the number of LED per string and V F(MAX) is the maximum LED forward voltage rated at the highest operating current and the lowest operating temperature. The V OUT(MAX) is programmed with a resistor divider between the output and the FB pin. The resistor values are calculated as: RFB2 =RFB1 VOUT(MAX) 1.205V - 1Ê ËÁ ˆ Tolerance of the feedback resistors will add additional errors to the output voltage, so 1% resistor values should be used. The FB pin output bias current is typically 120nA, so use of extremely high value feedback resistors could also cause bias current errors. A typical value for R FB1 is 10k. VIN Power Input Supply Range The power input supply for the LT3746 can range from 6V to 55V, covering a wide variety of industrial power supplies. Another restriction on the minimum input voltage V IN(MIN) is the 2V minimum dropout voltage between the VIN and ISN pins, and thus the VIN(MIN) is calculated as: VIN(MIN) =VOUT(MAX) +2V Choosing Switching Frequency Selection of the switching frequency is a tradeoff between efficiency and component size. Low frequency operation improves efficiency by reducing MOSFET switching losses and gate charge losses. However, lower frequency opera- tion requires larger inductor and capacitor values. Another restriction on the switching frequency comes from the input and output voltage range caused by the minimum switch on and switch off time. The highest switching frequency f SW(MAX) for a given application can be calculated as: fSW(MAX) =MIN DMIN tON(MIN) , 1– DMAX tOFF(MIN) where the minimum duty cycle D MIN and the maximum duty cycle DMAX are determined by: DMIN = VOUT(MIN) +VD VIN(MAX) +VD and DMAX = VOUT(MAX) +VD VIN(MIN) +VD tON(MIN) is the minimum switch on time (~200ns), tOFF(MIN) is the minimum switch off time (~120ns), VOUT(MIN) is the minimum adaptive output voltage, VIN(MAX) is the maxi- mum input voltage, and VD is the catch diode forward volt- age (~0.5V). The calculation of fSW(MAX) simplifies to: fSW(MAX) = MIN 5 • VOUT(MIN)+ VD VIN(MAX)+ VD , 8.33• VIN(MIN)– VOUT(MAX) VIN(MIN)+ VD MHz Obviously, lower frequency operation accommodates both extremely high and low VOUT to VIN ratios. Besides these common considerations, the specific application also plays an important role in switching fre- quency choice. In a noise-sensitive system, the switching
out of a sensitive frequency band. common switching frequencies. Table 2. Switching Frequency f SW vs RT Value oscillation at duty cycles greater than 50%. between inductor performance and inductor size and cost. due to insufficient slope compensation.
The largest inductor ripple current occurs at the highest VIN. To guarantee that the ripple current stays below the specified maximum, the inductor value should be chosen according to the following equation: L ≥ VOUT +VD VIN(MAX) +VD VIN(MAX) – VOUT fSW •∆I L The inductor DC or RMS current rating must be greater than the maximum output load current I OUT(MAX) and its saturation current should be higher than the maximum inductor current I L(MAX). To achieve high efficiency, the DCR resistance should be less than 0.1Ω, and the core material should be intended for high frequency applications. Power MOSFET Selection Important parameters for the external P-channel MOSFET M1 include drain-to-source breakdown voltage (V (BR)DSS), maximum continuous drain current (ID(MAX)), maximum gate-to-source voltage (VGS(MAX)), total gate charge (QG), drain-to-source on resistance (RDS(ON)), reverse transfer capacitance (CRSS). The MOSFET V(BR)DSS specification should exceed the maximum voltage across the source to the drain of the MOSFET, which is V IN(MAX) plus VD. The ID(MAX) should exceed the peak inductor current, IL(MAX). Since the gate driver circuit is supplied by the internal 6.8V V IN referenced regulator, the V GS(MAX) rating should be at least 10V. Each switching cycle the MOSFET is switched off and on, a packet of gate charge QG is transferred from the VIN pin to the GATE pin, and then from the GATE pin to the CAP pin. The resulting dQ G/dt is a current that must be sup - plied to the CCAP capacitor by the internal regulator. The maximum 20mA current capability of the internal regulator limits the maximum Q G(MAX) it can deliver to: Q G(MAX)= 20mA fSW Therefore, the QG at VGS = 6.8V from the MOSFET data sheet should be less than QG(MAX). For maximum efficiency, both R DS(ON) and CRSS should be minimized. Lower RDS(ON) means less conduction loss while lower CRSS reduces transition loss. Unfortunately, RDS(ON) is inversely related to C RSS. Thus balancing the conduction loss with the transition loss is a good criterion in selecting a MOSFET. For applications with higher V IN voltages (≥24V) a lower C RSS is more important than a low RDS(ON). Catch Diode Selection The catch diode D1 carries load current during the switch off time. Important parameters for the catch diode includes peak repetitive reverse voltage (V RRM), forward voltage (VF), and maximum average forward current (IF(AV)). The diode VRRM specification should exceed the maximum reverse voltage across it, i.e., VIN(MAX). A fast switching schottky diode with lower VF should be used to yield lower power loss and higher efficiency. In continuous conduction mode, the average current conducted by the catch diode is calculated as: ID(AVG) =IOUT •(1– D) The worst-case condition for the diode is when V OUT is shorted to ground with maximum VIN and maximum IOUT at present. In this case, the diode must safely conduct the maximum load current almost 100% of the time. To improve efficiency and to provide adequate margin for short circuit operation, a schottky diode rated to at least the maximum output current is recommended. C IN, CVCC, and CCAP Capacitor Selection A local input bypass capacitor C IN is required for buck converters because the input current is pulsed with fast rise and fall times. The input capacitor selection criteria are based on the voltage rating, bulk capacitance, and RMS current capability. The capacitor voltage rating must be greater than V IN(MAX). The bulk capacitance determines the input supply ripple voltage and the RMS current capability is used to keep from overheating the capacitor.
The bulk capacitance is calculated based on maximum input ripple, ∆VIN: CIN =DMAX •IOUT(MAX) ∆VIN •fSW ∆VIN is typically chosen at a level acceptable to the user. 100mV is a good starting point. For ceramic capacitors, only X5R or X7R type should be used because they retain their capacitance over wider voltage and temperature ranges than other types such as Y5V or Z5U. Aluminum electrolytic capacitors are a good choice for high voltage, bulk capacitance due to their high capacitance per unit area. The capacitor RMS current is: ICIN(RMS) = IOUT • VOUT •( VIN – VOUT ) VIN If applicable, calculate at the worst case condition, VIN=2 • V OUT. The capacitor RMS current rating speci - fied by the manufacturer should exceed the calculated ICIN(RMS). Due to their low ESR, ceramic capacitors are a good choice for high voltage, high RMS current han - dling. Note that the ripple current ratings from aluminum electrolytic capacitor manufacturers are based on 2000 hours of life. This makes it advisable to further derate the capacitor or to choose a capacitor rated at a higher temperature than required. For a larger high voltage capacitor value, the combination of aluminum electrolytic capacitors and ceramic capacitors is an economical approach. Multiple capacitors may also be paralleled to meet size or height requirements in the design. Locate the capacitor very close to the MOSFET switch and the catch diode, and use short, wide PCB traces to minimize parasitic inductance. The general discussion above also applies to the capacitor C VCC at the VCC pin and the capacitor CCAP between the VIN and CAP pins. Typically, a 10µF 10V-rated ceramic capaci- tor for CVCC and a 0.47µF 16V-rated ceramic capacitor for CCAP should be sufficient. COUT Capacitor Selection The output capacitor has two essential functions. Along with the inductor, it filters the square wave generated by the LT3746 to produce the DC output containing a con - trolled voltage ripple. It also stores energy to satisfy load transients and to stabilize the dual-loop operation. Thus the selection criteria for C OUT are based on the voltage rating, the equivalent series resistance ESR, and the bulk capacitance. As always, choose the C OUT with a voltage rating greater than VOUT(MAX). The LT3746 utilizes the output as the dominant pole to sta- bilize the dual loop operation, so the COUT value determines the unity gain frequency fUGF, which is set around 1/10 of the switching frequency. To stabilize the FB loop during the startup and precharging phases and the LED loop during the tracking phase, a low-ESR capacitor (tens of mΩ) should be used and its minimum C OUT is calculated as: COUT = MAX 0.25 RS •fUGF , 1.5 VOUT(MAX)• RS • fUGF The ad aptive-tracking-plus-precharging technique moves the VOUT with the grayscale PWM dimming frequency to improve system efficiency, choosing a ceramic capacitor as the COUT inevitably generates acoustic noise due to the piezo effect of the ceramic material. In an acoustic noise sensitive application, low ESR tantalum or aluminum capacitors are preferred. When choosing a capacitor, look carefully through the data sheet to find out what the actual capacitance is under operating conditions (applied voltage and temperature). A physically larger capacitor, or one with a higher voltage rating, may be required.
and ground to program a power input VIN UVLO threshold. 0.35V. The part then initiates a new soft-start cycle.
- 1000 ILED(NOM) must be set between 4mA and 20mA. Typical RISET resistor values for various nominal LED currents are listed in Table 3.
Table 3. Nominal LED Current I LED(NOM) vs. RISET Value Figure 6. Methods of Controlling the EN/UVLO Pin
3746 F06
correction setting adjusts each LED current from 0.5X to 1.5X of the nominal LED current according to: ILEDn= ILED(NOM)• DCn+32 where ILEDn is the nth LED current and DC n is the nth programmed dot correction setting (DCn = 0 to 63). The fine current step over the nominal LED current gives an excellent resolution: ∆ILED ILED(NON) = 1 64 ≈1.56% which enhances the relative LED current match accuracy if used as calibration. Setting Grayscale Although adjusting the LED current changes its luminous intensity, or brightness, it will also affect the color match- ing between LED channels by shifting the chromaticity coordinate. The best way to adjust the brightness is to control the amount of LED on/off time by pulse width modulation (PWM). The LT3746 can adjust the brightness for each channel independently. The 12-bit grayscale PWM dimming results in 4096 linear brightness steps from 0% to 99.98%. The brightness level GS n% for channel n can be calculated as: GSn%= GSn 4096 •100% where GS n is the nth programmed grayscale setting (GSn = 0 to 4095). Open/Short LED Fault The LT3746 has individual LED fault diagnostic circuitry that detects both open and short LED faults for each channel. The open LED fault is defined as any LED string is open or disconnected from the circuit; and the short LED fault is defined as any LED string is shorted across itself. The open LED flag is set if the LED pin voltage is lower than 0.1V (typical) during on status with initial 500ns blanking. The short LED flag is set if the LED pin voltage is higher than 75% of the LED bus voltage V OUT any time. If one LED channel is shorted across itself, the channel will be turned off to eliminate unnecessary power dissipation. The function can also be used to disable LED channels by connecting their LED pins to the output directly. Both the open and short LED flags are combined to set the LED fault bits (S0 to S31) in the status frame to 1. Thermal Protection The LT3746 has two over temperature thresholds: one is the fixed internal thermal shutdown and the other one is programmed by a resistor, R TSET, between the T SET pin and ground. When the junction temperature exceeds 165°C, the part will enter thermal shutdown mode, shut down serial data interface, turn off LED channels, and stop switching. After the junction temperature drops below 155°C, the part will initiate a new soft start. When the R TSET is placed at the TSET pin, a current equal to the current flowing through the R ISET passes the RTSET, generating a voltage VTSET at the TSET pin, which is calculated as: VTSET =1.205V •RTSET RISET applicaTions inForMaTion
Then the VTSET is compared to an internal proportional- to-absolute-temperature voltage VPTAT, VPTAT = 1.72mV•(TJ +273.15) where TJ is the LT3746 junction temperature in °C. When VPTAT is higher than V TSET, an overtemperature flag OT = 1 is set. Once the RTSET programmed temperature is exceeded, the part will also gradually derate the nominal LED current ILED(NOM) to limit the total power dissipation without interrupting its normal operation. Cascading Devices and Determining Serial Data Interface Clock In a large LCD backlighting or LED display system, mul- tiple LT3746 chips can be easily cascaded to drive all the LED strings. The LT3746 adopts a 6-wire topology, which balances the internal clock skew and matches the external trace capacitance with an easy PCB layout. The minimum serial data interface clock frequency f SCKI for a large display system can be calculated as: fSCKI = NLT3746 •386 •fREFRESH applicaTions inForMaTion where NLT3746 is the number of LT3746 chips and fREFRESH is the refresh rate of the whole system. Calculating Power Dissipation The total power dissipation inside the chip can be calcu- lated as: PTOTAL = VIN•(IVIN+ fSW •QG)+ VCC •IVCC + GSn% •ILEDn •VLEDn n=0 where IVIN is the power input VIN quiescent current, IVCC is the VCC supply current, and VLEDn is the LED pin volt- age for channel n. From the total power dissipation P TOTAL, the junction temperature TJ can be calculated as: TJ =TA +PTOTAL •θJA Keep TJ below the maximum operating junction tempera- ture 125°C.
Figure 7. 32-Channel LED Driver, 500kHz Buck, 1 LED 10mA to 30mA per Channel, 100Hz 12-Bit Dimming
3746 TA02
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package DescripTion 56-Lead Plastic QFN (5mm × 9mm) (Reference L TC DWG # 05-08-1727 Rev A) 5.00 ± 0.10 (2 SIDES) NOTE: 1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS PIN 1 TOP MARK (SEE NOTE 6) BOTTOM VIEW—EXPOSED PAD 3.45 ±0.10 7.13 ±0.10 6.80 REF9.00 ± 0.10 (2 SIDES) 0.75 ± 0.05 R = 0.115 TYP 0.20 ± 0.05 (UH) QFN 0406 REV A 0.40 BSC0.200 REF
0.200 REF
0.00 – 0.05 RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
3.60 REF
0.40 ±0.10 0.70 ± 0.05
0.40 BSC
6.80 REF (2 SIDES)
(2 SIDES) 4.10 ± 0.05 (2 SIDES) 5.50 ± 0.05 (2 SIDES) 7.13 ±0.05 3.45 ±0.05 8.10 ± 0.05 (2 SIDES) 9.50 ± 0.05 (2 SIDES) 0.20 ± 0.05 PACKAGE OUTLINE 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE PIN 1 NOTCH R = 0.30 TYP OR 0.35 × 45° CHAMFER 56-Lead Plastic QFN (5mm × 9mm) (Reference LTC DWG # 05-08-1727 Rev A)
Figure 8. 32-Channel LED Driver, 1MHz Buck, 3 LEDs 10mA to 30mA per Channel, 500Hz 12-Bit Dimming