LT3743

LT3743_15 LINER

Document overview

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Technical content

DESCRIPTION

The LT®3743 is a fixed frequency synchronous step-down DC/DC controller designed to drive high current LEDs. The average current mode controller will maintain inductor current regulation over a wide output voltage range of 0V to (VIN – 2V). LED dimming is achieved through analog dimming on the CTRL_L, CTRL_H and CTRL_T pins and with PWM dimming on the PWM and CTRL_SEL pins. Through the use of externally switched load capacitors, the LT3743 is capable of changing regulated LED current levels within several µs, providing accurate, high speed PWM dimming between two current levels. The switching frequency is programmable from 200kHz to 1MHz through an external resistor on the RT pin. Additional features include voltage regulation and overvoltage protection set with a voltage divider from the output to the FB pin. Overcurrent protection is provided and set by the CTRL_H pin. 92% Efficient 20A LED Driver

FEATURES

APPLICATIONS

n PWM Dimming Provides Up to 3000:1 Dimming Ratio n CTRL_SEL Dimming Provides Up to 3000:1 Dimming Ratio Between Any Current n Three-State Current Control for Color Mixing n ±6% Current Regulation Accuracy n 6V to 36V Input Voltage Range n Average Current Mode Control n 2µs Maximum Recovery Time Between Any Current Regulation State n <1µA Shutdown Current n Output Voltage Regulation and Open-LED Protection n Thermally Enhanced 4mm × 5mm QFN and 28-Pin FE Package n DLP Projectors n High Power Architectural Lighting n Laser Diodes CTRL_SEL 5V/DIV PWM 5V/DIV SW 20V/DIV ILED 10A/DIV 20µs/DIV

3743 TA01b

VIN = 24V 0A TO 2A TO 20A LED CURRENT STEP L, LT, LT C, LT M, Linear Technology and the Linear logo are registered trademarks and T rue Color PWM is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents including 7199560, 7321203, 8120335 and others pending. EN/UVLO PWM CTRL_SEL EN/UVLO PWM CTRL_SEL HG V IN CBOOT VREF CTRL_L CTRL_H CTRL_T L T3743 RT SYNC SW LG GND VCHVCL SENSE+ SENSE– PWMGH PWMGL VCC_INT 220nF 1.1µH 22µF 330µF 2.5m/uni03A9 FB 10nF 34k 8.2nF 34k 8.2nF 82.5k 100k 100k 330µF 51.1k 3743 TA01a 10.0k 4.7µF 330µF 2.2nF RNTC 10k 4.7µF V IN 10V TO 30V OUTPUT 20A MAXIMUM 1µF SS RHOT 499Ω M1, M2: SiR462DP M3, M4: Si7234DP

(Note 1) ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LT3743EUFD#PBF LT3743EUFD#TRPBF 3743 28-Lead (4mm × 5mm) Plastic QFN –40°C to 125°C LT3743IUFD#PBF LT3743IUFD#TRPBF 3743 28-Lead (4mm × 5mm) Plastic QFN –40°C to 125°C LT3743EFE#PBF LT3743EFE#TRPBF LT3743FE 28-Lead Plastic TSSOP –40°C to 125°C LT3743IFE#PBF LT3743IFE#TRPBF LT3743FE 28-Lead Plastic TSSOP –40°C to 125°C Consult LT C Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LT C Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ ABSOLUTE MAXIMUM RATINGS 9 10 TOP VIEW UFD PACKAGE 28-LEAD (4mm × 5mm) PLASTIC QFN 11 12 13 28 27 26 25 24 1GND EN/UVLO VREF CTRL_T GND CTRL_H CTRL_L SS PWMGL GND GND PWMGH PWM CTRL_SEL SYNC RT VIN VCC_INT LG CBOOT SW HG GND FB SENSE SENSE– VCL VCH 8 15 GND TJMAX = 125°C, θJA = 37°C/W EXPOSED PAD (PIN 29) IS GND, MUST BE SOLDERED TO PCB TOP VIEW FE PACKAGE 28-LEAD PLASTIC TSSOP V CC_INT GND VIN EN/UVLO VREF CTRL_T GND CTRL_H CTRL_L SS GND FB SENSE+ SENSE– LG GND CBOOT SW HG PWMGL GND PWMGH PWM CTRL_SEL SYNC RT V CH VCL GND TJMAX = 125°C, θJA = 30°C/W EXPOSED PAD (PIN 29) IS GND, MUST BE SOLDERED TO PCB PIN CONFIGURATION Lead Temperature (Soldering, 10 sec) (Note 2)

ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, VEN/UVLO = 5V, VSYNC = 0V, VCTRL_SEL = 0V, VPWM = 2V, unless otherwise noted. PARAMETER CONDITIONS MIN TYP MAX UNITS Input Voltage Range 6 36 V VIN Pin Quiescent Current (Note 3) Non-Switching Operation Shutdown Mode V PWM = VCTRL_SEL = 0V, Not Switching, RT = 40k VEN/UVLO = 0V l 1.8 0.1 2.5 mA µA EN/UVLO Pin Falling Threshold 1.49 1.55 1.61 V EN/UVLO Hysteresis 130 mV EN/UVLO Pin Current VIN = 6V, EN/UVLO = 1.45V 5.5 µA PWM Pin Threshold 1.0 V CTRL_SEL Threshold 1.0 V SYNC Pin Threshold 1.0 V CTRL_H and CTRL_L Pin Control Range 0 1.5 V CTRL_H and CTRL_L Pin Current 100 nA Reference Reference Voltage (VREF Pin) l 1.96 2 2.04 V Inductor Current Sensing Full Range SENSE + to SENSE– VCTRL_H = 1.5V, VSENSE– = 6V l 48 51 54 mV SENSE+ Pin Current VSENSE+ = VSENSE– = 6V 50 nA SENSE– Pin Current VSENSE+ = VSENSE– = 6V 10 µA Internal VCC Regulator (VCC_INT Pin) Regulation Voltage l 4.7 5 5.2 V NMOS FET Driver (Note 2) Non-Overlap time HG to LG 100 ns Non-Overlap time LG to HG 60 ns Minimum On-Time LG (Note 3) 50 ns Minimum On-Time HG (Note 3) 80 ns Minimum Off-Time LG (Note 3) 60 ns High Side Driver Switch On-Resistance Gate Pull Up Gate Pull Down V CBOOT – VSW = 5V 2.3 1.3 Ω Ω Low Side Driver Switch On-Resistance Gate Pull Up Gate Pull Down VCC_INT = 5V 2.5 1.3 Ω Ω Switching Frequency f SW RT = 40kΩ RT = 200kΩ l 900 190 1000 200 1070 233 kHz kHz Soft-Start Charging Current 5.5 µA Voltage Regulation Amplifier Input Bias Current 1 nA g m 200 µA/V Feedback Regulation Voltage VCTRL_H = 0V, VCTRL_L = 2V, VSENSE+ = 2V l 0.945 1 1.025 V

ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, VEN/UVLO = 5V, unless otherwise noted. PARAMETER CONDITIONS MIN TYP MAX UNITS PWMG Control Signals CTRL_SEL High to PWMGL Low Delay 10 40 ns CTRL_SEL High to PWMGH High Delay 150 200 ns CTRL_SEL Low to PWMGH Low Delay 30 60 ns CTRL_SEL Low to PWMGL High Delay 170 220 ns PWMGH and PWMGL Pull-up Impedance 3.2 Ω PWMGH and PWMGL Pull-Down Impedance 1.75 Ω Current Control Loop gm Amp Offset Voltage VSENSE+ = 4V, VSENSE– = 4V l –3 0 3 mV Input Common Mode Range VCM(LOW) VCM(HIGH) V CM(HIGH) Measured from VIN to VCM V V Output Impedance 3.5 MΩ g m 375 475 625 µA/V Differential Gain 1.7 V/mV Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LT3743E is guaranteed to meet performance specifications from 0°C to 125°C junction temperature. Specifications over the –40°C to 125°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LT3743I is guaranteed to meet performance specifications over the –40°C to 125°C operating junction temperature range. Note 3: The minimum on and off times are guaranteed by design and are not tested.

TYPICAL PERFORMANCE CHARACTERISTICS EN/UVLO Threshold (Falling) EN/UVLO Pin Current IQ in Shutdown VIN (V) EN/UVLO THRESHOLD (V) 1.58 1.64 1.70 –50°C 130°C

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1.52 1.46 1.40 12 18 24 36 VIN (V) EN/UVLO PIN CURRENT (µA)

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25°C 130°C –50°C VIN (V) IQ (µA) 0.3 0.4 0.5

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0.2 0.1 8 16 24 40 130°C 25°C Quiescent Current (Non-Switching) VREF Pin Voltage VREF Current Limit VIN (V) QUIESCENT CURRENT (mA) 1.2 1.6 2.0

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0.8 0.4 12 18 24 36 TA = 25°C TA = 130°C TA = –50°C TEMPERATURE (°C) –50 VREF VOL TAGE (V) 2.00 2.01 2.02

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1.99 1.98 1.97 –15 20 55 125 VIN = 36V VIN = 6V VIN (V) ILIMIT (mA)1.2 1.4 1.6

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1.0 0.8 12 18 24 36 TA = 25°C TA = 130°C TA = –50°C Oscillator Frequency RT Pin Current Limit Soft-Start Pin Current TEMPERATURE (°C) –50 FREQUENCY (MHz) 0.9 1.2 1.5

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0.6 0.3 –15 20 55 125 1.2MHz 900kHz 220kHz TEMPERATURE (°C) –50 ILIMIT (µA)

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–15 20 55 125 TEMPERATURE (°C) –50 ISS (µA)5

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–15 20 55 125 VIN = 36V VIN = 6V

TYPICAL PERFORMANCE CHARACTERISTICS VCC_INT Load Reg at 12V Regulated Current vs VFB Open-LED Threshold Open-LED Timeout Regulated Sense Voltage Common Mode Lockout Internal UVLO CBOOT-SW UVLO Voltage VCC_INT UVLO TEMPERATURE (°C) –50 VIN (V)4.0 4.5 5.0

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3.5 3.0 –15 20 55 125 TEMPERATURE (°C) –50

1.50 VOLTAGE (V)

1.75 2.00 2.25 2.50 2.75 3.00 –15 20 55 90

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TEMPERATURE (°C) –50

2.50 UVLO (V)

2.75 3.00 3.25 3.50 3.75 4.00 –15 20 55 90

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ILOAD (mA) VCC_INT (V)5.2 5.6 6.0

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4.8 4.4 4.0 10 20 30 60 50 VFB (mV) 800 –150 REGULATED CURRENT (%) –100 –50 100 150 900 1000 1100 1200

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TEMPERATURE (°C) –50 OPEN-LED THRESHOLD (V) 1.3 1.4 1.5

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1.2 1.1 1.0 –15 20 55 125 TEMPERATURE (°C) –50 OPEN-LED TIMEOUT (µs)

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–15 20 55 125 VCTRL (V) VSENSE+ – VSENSE– (mV) 0.5 1.0 1.5

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2.0 TEMPERATURE (°C) –50 CM LOCKOUT (V) 1.5 2.0 2.5

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1.0 0.5 –15 20 55 125 VIN = 6V VIN = 36V MEASURED VIN – VOUT

TYPICAL PERFORMANCE CHARACTERISTICS Non-Overlap PWM Signal Delay Non-Overlap Time Minimum On-Time Minimum Off-Time Regulation Accuracy CTRL_H = 1.5V, VIN = 12V Regulation Accuracy CTRL_H = 0.75V, V IN = 12V PWM Driver RDS(0N) HG Driver RDS(ON) LG Driver RDS(ON) TEMPERATURE (°C) –50 RDS(ON) (/uni03A9)3

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–15 20 55 125 PMOS NMOS TEMPERATURE (°C) –50 RDS(ON) (/uni03A9)3

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–15 20 55 125 PMOS NMOS TEMPERATURE (°C) –50 RDS(ON) (/uni03A9)3

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–15 20 55 125 PMOS NMOS TEMPERATURE (°C) –50 DELAY (ns) 130 140 150

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–15 20 55 125 PWMGL TO PWMGH PWMGH TO PWMGL TEMPERATURE (°C) –50 NON-OVERLAP TIME (ns) 120 150

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–15 20 55 125 HG TO LG LG TO HG TEMPERATURE (°C) –50 MINIMUM ON-TIME (ns) 120 150

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–15 20 55 125 HG LG TEMPERATURE (°C) –50 MINIMUM OFF-TIME (ns) 180 240 300

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–15 20 55 125 LG HG OUTPUT VOL TAGE (V) ACCURACY (%) 2.5 5.0 7.5 10

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OUTPUT VOL TAGE (V) ACCURACY (%) 2.5 5.0 7.5 10

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TYPICAL PERFORMANCE CHARACTERISTICS LED Current Waveforms (3000:1) 2A to 20A LED Current Waveforms (3000:1) 0A to 2A to 20A LED Current Waveforms (3000:1) Analog Dimming on CTRL_L C OUT(LOW) = 22µF, COUT(HIGH) = 1mF Overcurrent Threshold LED Current Waveforms (90% PWM) 0.5A to 5A LED Current Waveforms (2000:1) 3A to 10A Voltage Regulation with 10A Regulated Inductor Current Common Mode Lockout (V IN = 7V) Overvoltage Lockout Operation With Open-Load Condition CTRL_H (V) VSENSE+ – VSENSE– (mV) 100 120 0.75 1.5 2.25 3.0

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CTRL_SEL 5V/DIV SW 20V/DIV ILED 5A/DIV IL 10A/DIV 40µs/DIV

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CTRL_SEL 5V/DIV ILED 5A/DIV IL 10A/DIV 5µs/DIV

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CTRL_SEL 5V/DIV SW 10V/DIV PWM 5V/DIV ILED 10A/DIV 20µs/DIV

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CTRL_L 0.2V/DIV CTRL_SEL 5V/DIV PWM 5V/DIV ILED 8A/DIV 40µs/DIV

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100µs/DIV

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CTRL_SEL 5V/DIV SW 10V/DIV ILED 11.1A/DIV 20µs/DIV

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PIN FUNCTIONS (QFN/TSSOP) GND (Pins 1, 5, 9, 20, 21, Exposed Pad Pin 29/Pins 2, 7, 11, 22, 27, Exposed Pad Pin 29): Ground. The exposed pad must be soldered to the PCB. EN/UVLO (Pin 2/Pin 4): Enable Pin. The EN/UVLO pin acts as an enable pin and turns on the internal current bias core and subregulators at 1.55 V. The pin does not have any pull-up or pull-down, requiring a voltage bias for normal part operation. Full shutdown occurs at approximately 0.5V. V REF (Pin 3/Pin 5): Buffered 2V Reference Capable of 0.5mA Drive. CTRL_T (Pin 4/Pin 6): The thermal control input to reduce the regulated current level for both current levels (CTRL_L and CTRL_H). CTRL_H (Pin 6/Pin 8): The CTRL_H pin sets the high level regulated output current and overcurrent. The maximum input voltage is internally clamped to 1.5V. The overcurrent set point is equal to the high level regulated current level set by the CTRL_H pin with an additional 23mV offset between the SENSE+ and SENSE– pins. CTRL_L (Pin 7/Pin 9): The CTRL_L pin sets the low level regulated output current. It is not recommended that the CTRL_L voltage be higher than the CTRL_H voltage. SS (Pin 8/Pin 10): Soft-Start Pin. Place an external capacitor to ground to limit the regulated current during start-up conditions. The SS pin has a 5.5µA charging current. This pin controls both of the regulated inputs determined by CTRL_L and CTRL_H. FB (Pin 10/Pin 12): Feedback Pin for Overvoltage Protec- tion. The feedback voltage is 1V. Overvoltage/Open LED is sensed through the FB pin. When the feedback voltage exceeds 1.3V, the overvoltage lockout prevents switch- ing and connects both output capacitors to discharge the inductor current. SENSE + (Pin 11/Pin 13): SENSE+ is the inverting input of the average current mode loop error amplifier. This pin is connected to the external current sense resistor, RS. The voltage drop between SENSE+ and SENSE– referenced to the voltage drop across an internal resistor produces the input voltages to the current regulation loop. SENSE– (Pin 12/Pin 14): SENSE– is the noninverting input of the average current mode loop error amplifier. The reference current, based on CTRL_L or CTRL_H flows out of the pin to the output (LED) side of the sense resistor, RS. VCL (Pin 13/Pin 15): VCL provides the necessary compensa- tion for the average current loop stability during low level current regulation. Typical compensation values are 15k to 80k for the resistor and 2nF to 10nF for the capacitor. V CH (Pin 14/Pin 16): VCH provides the necessary compen- sation for the average current loop stability during high level current regulation. Typical compensation values are 15k to 80k for the resistor and 2nF to 10nF for the capacitor. RT (Pin 15/Pin 17): A resistor to ground sets the switching frequency between 200kHz and 1MHz. When using the SYNC function, set the frequency to be 20% lower than the SYNC pulse frequency. This pin is current limited to 60µA. Do not leave this pin open. SYNC (Pin 16/Pin 18): Frequency Synchronization Pin. This pin allows the switching frequency to be synchronized to an external clock. The R T resistor should be chosen to operate the internal clock at 20% slower than the SYNC pulse frequency. The synchronization range is 240kHz to 1.2MHz. This pin should be grounded when not in use. CTRL_SEL (Pin 17/Pin 19): The CTRL_SEL pin selects between the high current control, CTRL_H and the low current control, CTRL_L. When high, the V CH pin is con- nected to the error amp output and the PWMGH gate signal is high. When low, the VCL pin is connected to the error amp output and the PWMGL gate signal is high. This pin is used for current level dimming of the LED. This pin should be grounded when not in use. PWM (Pin 18/Pin 20): The input pin for PWM dimming of the LED. When low, all switching is terminated and the output caps are disconnected. This pin should be pulled to VCC_INT when not in use. PWMGH (Pin 19/Pin 21): The PWMGH output pin drives the gate of an external FET to connect one of the switching regulator output capacitors to the load. The driver pull-up impedance is 3.2Ω and pull-down impedance is 1.75Ω.

PWMGL (Pin 22/Pin 23): The PWMGL output pin drives the gate of an external FET to connect one of the switching regulator output capacitors to the load. The driver pull-up impedance is 3.2Ω and pull-down impedance is 1.75Ω. HG (Pin 23/Pin 24): HG is the top FET gate drive signal that controls the state of the high side external power FET. The driver pull-up impedance is 2.3Ω and pull-down impedance is 1.3Ω. SW (Pin 24/Pin 25): The SW pin is used internally as the lower rail for the floating high side driver. Externally, this node connects the two power FETs and the inductor. CBOOT ( Pin 25/Pin 26): The CBOOT pin provides a floating 5V regulated supply for the high side FET driver. An external Schottky diode is required from the V CC_INT pin to the CBOOT pin to charge the CBOOT capacitor when the switch pin is near ground. PIN FUNCTIONS (QFN/TSSOP) LG (Pin 26/Pin 28): LG is the bottom FET gate drive sig- nal that controls the state of the low side external power FET. The driver pull-up impedance is 2.5Ω and pull-down impedance is 1.3Ω. V CC_INT (Pin 27/Pin 1): A regulated 5V output for charging the CBOOT capacitor. VCC_INT also provides the power for the digital and switching subcircuits. Below 6V VIN, tie this pin to the rail. VCC_INT is current limited to ≈50mA. Shutdown operation disables the output voltage drive. V IN (Pin 28/Pin 3): Input Supply Pin. Must be locally bypassed with a 1µF low ESR capacitor to ground.

15 SYNCRONOUS

3743 F01

Figure 1. Block Diagram

The LT3743 utilizes fixed frequency, average current mode control to accurately regulate the inductor current, independently from the output voltage. This is an ideal solution for applications requiring a regulated current source including driving high current LEDs where the forward junction voltage can range from 2V to 6V with a dynamic resistance of 20mΩ to 40mΩ. The control loop will regulate the current in the inductor at an accuracy of 6%. For additional operation information, refer to the Block Diagram in Figure 1. The control loop has two independent reference inputs, determined by the analog control pins, CTRL_H and CTRL_L. When the CTRL_SEL pin is low, the control loop uses the reference determined by the CTRL_L pin and when high, the loop uses the reference determined by the CTRL_H pin. The analog voltage at the CTRL_L and CTRL_H pins is buffered and produces a reference voltage across an internal resistor. The internal buffers have a 1.5V clamp on the output, limiting the analog control range of the CTRL_L and CTRL_H pins from 0V to 1.5V. The aver- age current mode control loop uses the internal reference voltage to regulate the inductor current, as a voltage drop across the external sense resistor, RS. In many applications, a rapid transition between the two regulated current states is desirable to provide background LED color mixing for pure colors in an RGB projector or display. For this purpose, pulse width modulation dimming can be achieved with both the PWM and CTRL_SEL pins. When the PWM pin is low, the regulated current in the inductor is zero and both output capacitors are disconnected. When the PWM pin is high, and the CTRL_SEL pin is low, the regulated current in the inductor is determined by the analog voltage at the CTRL_L pin. When the PWM and CTRL_SEL pins are both high, the regulated current in the inductor is determined by the analog voltage at the CTRL_H pin. The LT3743 uses a unique switched output capacitor topology and two independent compensation networks to transition between the two regulated current states in less than 2µs. When the CTRL_SEL pin is low and the PWM pin is high, the PWMGL output pin is high, switching in the output capacitor for the CTRL_L current level. The CTRL_L output capacitor stores the LED forward voltage drop when the control loop regulates the low current level. When the CTRL_SEL pin changes to the high state, a 150ns delay ensures that the output capacitors are not connected at the same time. After this delay, the output capacitor for the CTRL_H level is switched in when PWMGH goes high and immediately delivers current to the LED. The CTRL_H output capacitor has the voltage drop of the LED with the regulated current determined by the analog voltage at the CTRL_H pin. To achieve minimum transition delay, the inductor is precharged to 70% of the regulation current level just after the PWMGH pin goes high. Conversely, when the PWM pin goes low, the inductor is discharged to 70% of the low current level before normal switching at the low current level commences. The error amplifier for the average current mode control loop also has a common mode lockout that regulates the inductor current so that the error amplifier is never operated out of the common mode range. The common mode range is with an output voltage from 0V to 2V below the VIN supply rail. The overcurrent set point is equal to the high level regulated current level set by the CTRL_H pin with an additional 23mV offset between the SENSE+ and SENSE– pins. The overcurrent is limited on a cycle-by-cycle basis; shutting switching down once the overcurrent level is reached. Overcurrent is not soft started. The output voltage may be limited with a resistor divider from the output back to the FB pin. The reference at the FB pin is 1.0V. If the output voltage level is high enough to engage the voltage loop, the regulated inductor current will be reduced so that the output voltage is limited. If the voltage at the FB pin reaches 1.3V (30% higher than the regulation level), an internal open-LED flag is set, shutting down switching for 13µs and switching in both output capacitors to fully drain the inductor’s current. During start-up, the SS pin is held low until the first time the PWM pin goes high. Once the PWM signal goes high, the capacitor at the SS pin is charged with a 5.5µA current source. The internal buffers for the CTRL_L and CTRL_H signals are limited by the voltage at the SS pin, slowly ramping the regulated inductor current to the current determined by the voltage at the CTRL_H or CTRL_L pins.

age inductor current, which is equal to the LED current. resistor. Figure 3 shows the power dissipation in RS. Table 1. Sense Resistor Values approximately 10% ripple at maximum regulated current. Table 2. Recommended Inductor Manufacturers

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Figure 2. RS Value Selection for LED Current Figure 3. Power Dissipation in RS

Switching MOSFET Selection When selecting switching MOSFETs, the following pa- rameters are critical in determining the best devices for a given application: total gate charge (QG), on-resistance (RDS(ON)), gate to drain charge (Q GD), gate-to-source charge (QGS), gate resistance (RG), breakdown voltages (maximum VGS and VDS) and drain current (maximum ID). The following guidelines provide information to make the selection process easier. Both of the switching MOSFETs need to have their maximum rated drain currents greater than the maximum inductor current. The following equation calculates the peak induc- tor current: IMAX =IO + VIN • VF +RDIO( ) – V F +RDIO( ) 2 •fS •L •VIN where VIN is the input voltage, L is the inductance value, VF is the LED forward voltage drop, RD is the dynamic series resistance of the LED, IO is the regulated output current and fS is the switching frequency. During MOSFET selec- tion, notice that the maximum drain current is temperature dependant. Most data sheets include a table or graph of the maximum rated drain current vs temperature. The maximum VDS should be selected to be higher than the maximum input supply voltage (including transient) for both MOSFETs. The signals driving the gates of the switching MOSFETs have a maximum voltage of 5V with respect to the source. During start-up and recovery con- ditions, the gate drive signals may be as low as 3V. To ensure that the LT3743 recovers properly, the maximum threshold should be less than 2V. For a robust design, select the maximum VGS greater than 7V. Power losses in the switching MOSFETs are related to the on-resistance, RDS(ON); the transitional loss related to the gate resistance, RG; gate-to-drain capacitance, QGD and gate-to-source capacitance, QGS. Power loss to the on-resistance is an Ohmic loss, I2 RDS(ON), and usually dominates for input voltages less than ~15V. Power losses to the gate capacitance dominate for voltages greater than ~12V. When operating at higher input voltages, efficiency can be optimized by selecting a high side MOSFET with higher RDS(ON) and lower CGD. The power loss in the high side MOSFET can be approximated by: PLOSS = (ohmic loss) + (transition loss) PLOSS VF +RDIO( ) VIN

• IO 2RDS(ON)• T + VIN •IOUT 5V • QGD +QGS( ) • 2•RG +RPU +RPD( )( )•fS where ρT is a temperature-dependant term of the MOS- FET’s on-resistance. Using 70°C as the maximum ambient operating temperature, ρT is roughly equal to 1.3. RPD and RPU are the LT3743 high side gate driver output imped- ance, 1.3Ω and 2.3Ω respectively. A good approach to MOSFET sizing is to select a high side MOSFET, then select the low side MOSFET. The trade- off between RDS(ON), QG, QGD and QGS for the high side MOSFET is shown in the following example. VO is equal to 4V. Comparing two N-channel MOSFETs, with a rated VDS of 40V and in the same package, but with 8× different RDS(ON) and 4.5× different QG and QGD: M1: RDS(ON) = 2.3mΩ, QG = 45.5nC, QGS = 13.8nC, QGD = 14.4nC , RG = 1Ω M2: RDS(ON) = 18mΩ, QG = 10nC, QGS = 4.5nC, QGD = 3.1nC , RG = 3.5Ω Power loss for both MOSFETs is shown in Figure 4. Ob- serve that while the RDS(ON) of M1 is eight times lower, the power loss at low input voltages is equal, but four times higher at high input voltages than the power loss for M2. Another power loss related to switching MOSFET selection is the power lost to driving the gates. The total gate charge, QG, must be charged and discharged each switching cycle. The power is lost to the internal LDO within the LT3743. The power lost to the charging of the gates is: PLOSS_LDO ≈ (VIN – 5V) • (QGLG + QGHG) • fS where QGLG is the low side gate charge and QGHG is the high side gate charge. APPLICATIONS INFORMATION

Table 3. Recommended Switching FETs current rating equal to half of the maximum output current. wide range of operating voltages and temperatures. series resistance) to allow the LED current to ramp quickly. more than 50nF to ensure proper operation of the LT3743.

3743 F04a

3743 F04b

charges larger than 10nC, use 0.5µF/nC of total gate charge. the inductor current is regulated to the high current state. currents is determined by the inductor size, VIN and VO. factory for optimized component selection.

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Figure 6. LED Current vs CTRL Voltage Figure 7. Analog Control of LED Current Figure 8. LED Current vs CTRL Voltage

3743 F06

of the high current output capacitor. ference of approximately 2V + VTH. Figure 9. Body Diode of High Current FET Figure 10. With a Drain-to-Drain Configuration, the Body Figure 11. Application for Large Differences

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3743 F10

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current, use a sense resistor.

charge, QG of the external switching MOSFETs selected. Table 4. Switching Frequency Figure 12. Output Voltage Regulation and Overvoltage Protection

3743 F12

ground. Do not leave this pin open under any condition.

3743 F13

Figure 13. Frequency vs RT Resistance

start is allowed to charge once the PWM signal is asserted. is determined by the resistor at the RT pin. has a precision shutdown at 1.55V on the EN/UVLO pin. age and hysteresis as configured in Figure 14.

3743 F14

Figure 14. UVLO Configuration current based on the analog voltage at the CTRL_T pin. at the CTRL_L and CTRL_H pins.

3743 F15CTRL_T

Figure 15. LED Current Derating vs Temperature

a current source and a 3k resistor. slope during the switch off-time. value, VIN is the input voltage and RS is the sense resistor. wide as physically possible and minimize the trace length. Table 6. Recommended Compensation Values

3743 F16

Figure 16. LT3743 Average Current Mode Control Scheme

12V, 20A LED Driver EN/UVLO PWM CTRL_SEL EN/UVLO PWM CTRL_SEL HG V IN CBOOT VREF CTRL_L CTRL_H CTRL_T L T3743 RT SYNC SW LG GND VCHVCL SENSE+ SENSE– PWMGH PWMGL VCC_INT 100nF 1.0µH 22µF 330µF 2.5m/uni03A9 33nF FB 10nF 34k 4.7nF 34k D1: LUMINUS PT120 L1: IHLP4040DZER1R0M01 M1: RJK0365DPA M2: RJK0346DPA M3, M4: Si7236DP C1, C2, C3: PTPR330M9L (THREE IN PARALLEL) 4.7nF 82.5k 50k 50k 330µF 60.4k

3743 TA02

1µF2.2nF RNTC 10k 220µF VIN 12V OUTPUT 20A MAXIMUM 1µF 330µF SS RHOT 499Ω 10Ω 10Ω CTRL_SEL DIMMING DUTY CYCLE (%)

3743 TA02b

EFFIENCY (%) VIN = 12V GREEN LED Efficiency (Stepping from 2A to 20A)

6V to 36V, 2A LED Driver With Shunted Output EN/UVLO PWM CTRL_SEL EN/UVLO INTV CC CTRL_SEL HG VIN CBOOT VREF CTRL_L CTRL_H CTRL_T L T3743 RT SYNC SW LG GND VCHVCL SENSE+ SENSE– PWMGH PWMGL VCC_INT 100nF 10µH 22µF 25m/uni03A9 FB 10nF 34k 4.7nF 34k 4.7nF 82.5k 40.2k D1: LUMINUS CBT-40 L1: MSS1048-103MLB M1, M2: Si7848BDP M3: Si2312BDS

3743 TA03

2.2nF RNTC 10k 8.2µF VIN 6V TO 36V OUTPUT 2A MAXIMUM 2.2µF 1µF SS RHOT 499Ω CONTROL INPUT Shunted Output with CTRL_H Equal to CTRL_L 6V to 36V, 2A LED Driver With Current Limited Shunted Output Shunted Output with CTRL_L at GND EN/UVLO PWM CTRL_SEL EN/UVLO INTV CC CTRL_SEL HG VIN CBOOT VREF CTRL_H CTRL_L CTRL_T L T3743 RT SYNC SW LG GND VCHVCL SENSE+ SENSE– PWMGH PWMGL VCC_INT 100nF 10µH 22µF 25m/uni03A9 FB 10nF 34k 4.7nF 34k 4.7nF 82.5k 40.2k

3743 TA04

2.2nF RNTC 10k 8.2µF VIN 6V TO 36V OUTPUT 2A MAXIMUM 2.2µF 1µF SS RHOT 499Ω CONTROL INPUT D1: LUMINUS CBT-40 L1: IHLP4040DZE10R0M01 M1, M2: Si7848BDP M3: Si2312BDS SW 2V/DIV IL 2A/DIV CTRL_SEL 5V/DIV ILED 1A/DIV 20µs/DIV

3743 TA03b

CTRL_SEL 5V/DIV ILED 1A/DIV 20µs/DIV

3743 TA04b

6V to 30V, 20A LED Driver with Switched Cathode EN/UVLO PWM CTRL_SEL EN/UVLO PWM V CC_INT HG VIN CBOOT VREF CTRL_L CTRL_H CTRL_T L T3743 RT SYNC SW LG GND VCHVCL SENSE+ SENSE– PWMGL PWMGH VCC_INT 150nF 1.1µH 22µF 2.5m/uni03A9 FB 10nF 34k 4.7nF 82.5k 60.4k

3743 TA05

2.2nF RNTC 10k 82µF 10/uni03A9 D1: LUMINUS PT121 L1: MVR1261C-112ML M1: RJK0365DPA M2: RJK0328DPB M3: SiR496DP C1: PTPR330M9L (THREE IN PARALLEL) V IN 6V TO 30V OUTPUT 20A MAXIMUM 330µF 1µF SS RHOT 499Ω CONTROL INPUT 10/uni03A9 33nF Switched Cathode PWM Dimming (100:1) 0A to 20A PWM 5V/DIV ILED 10A/DIV SW 10V/DIV 10µs/DIV

3743 TA05b

PWM DIMMING DUTY CYCLE (%) EFFICIENCY (%) 100

3743 TA05c

VIN = 12V GREEN LED

24V, 20A 3-LED Driver EN/UVLO PWM CTRL_SEL EN/UVLO PWM V CC_INT HG VIN CBOOT VREF CTRL_H CTRL_L CTRL_T L T3743 RT SYNC SW LG GND VCHVCL SENSE+ SENSE– PWMGH PWMGL VCC_INT 100nF 1.2µH 20µF 470µF 10Ω RED LEDs 2.5m/uni03A9 FB 10nF 24.3k 4.7nF 82.5k 20k 60.4k 316k L1: 1HLP5050FDER1R2M01 M1: Si7848BDP M2, M3: RJK0330DPB

3743 TA07

2.2nF RNTC 10k 82µF VIN 24V OUTPUT 20A MAXIMUM 1µF SS RHOT 499Ω 10Ω 33nF Efficiency DUTY CYCLE (%) EFFICIENCY (%) 100

3743 TA07b

VIN = 24V

3 RED LEDs

28-Lead Plastic QFN (4mm × 5mm) (Reference L TC DWG # 05-08-1712 Rev B) 4.00 ± 0.10 (2 SIDES)

2.50 REF

5.00 ± 0.10 (2 SIDES) NOTE: 1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X). 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE PIN 1 TOP MARK (NOTE 6) 0.40 ± 0.10 27 28 BOTTOM VIEW—EXPOSED PAD

3.50 REF

0.75 ± 0.05 R = 0.115 TYP R = 0.05 TYP PIN 1 NOTCH R = 0.20 OR 0.35 × 45° CHAMFER 0.25 ± 0.05

0.50 BSC

0.200 REF

0.00 – 0.05 (UFD28) QFN 0506 REV B RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 0.70 ±0.05 0.25 ±0.05 4.10 ± 0.05 5.50 ± 0.05 2.65 ± 0.05 3.10 ± 0.05 4.50 ± 0.05 PACKAGE OUTLINE 2.65 ± 0.10 3.65 ± 0.10 3.65 ± 0.05 Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. FE28 (EB) TSSOP REV I 0211 0.09 – 0.20 (.0035 – .0079) 0° – 8° 0.25 REF 0.50 – 0.75 (.020 – .030) 4.30 – 4.50* (.169 – .177) 1 3 4 5 6 7 8 9 10 11 12 13 14 19 20 22 21 15 16 18 17 9.60 – 9.80* (.378 – .386) 4.75 (.187) 2.74 (.108) 28 27 26 2524 23 1.20 (.047) MAX 0.05 – 0.15 (.002 – .006) 0.65 (.0256) BSC 0.195 – 0.30 (.0077 – .0118) TYP 2RECOMMENDED SOLDER PAD LAYOUT EXPOSED PAD HEAT SINK ON BOTTOM OF PACKAGE0.45 ±0.05

0.65 BSC

4.50 ±0.10 6.60 ±0.10 1.05 ±0.10 4.75 (.187) 2.74 (.108) MILLIMETERS (INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.150mm (.006") PER SIDE NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS 2. DIMENSIONS ARE IN 3. DRAWING NOT TO SCALE SEE NOTE 4 4. RECOMMENDED MINIMUM PCB METAL SIZE FOR EXPOSED PAD ATTACHMENT 6.40 (.252) BSC 28-Lead Plastic TSSOP (4.4mm) (Reference LTC DWG # 05-08-1663 Rev I) Exposed Pad Variation EB

Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

REVISION HISTORY

REV DATE DESCRIPTION PAGE NUMBER A 2/10 Revised Features and Typical Application Updated Electrical Characteristics values Revised values on curves G32 and G33 in the Typical Performance Characteristics section Revised the Block Diagram Changed value in equation and made minor text edit in the Inductor Selection section Revised Table 4 values Added text to Average Current Mode Control Compensation and Board Layout Considerations sections in the Applications Information section Revised all Typical Applications drawings 3, 4 21 to 25, 28 B 8/10 Updated Electrical Characteristics values and conditions Revised Pin Functions Revised Block Diagram Changed soft-start current in Operation section Revised units for M1 and M2 equations Removed 0.1MHz switching frequency from Table 4 Added text to Switching Frequency Synchronization, Shutdown and UVLO sections in the Applications Information section Corrected M2 and M3 part numbers on Typical Applications drawings 3, 4 9, 10 24, 28 C 9/11 Revised Feedback Regulation Voltage listing in Electrical Characteristics section 3 D 11/12 Clarified VCL and VCH pins Clarified Regulated Current vs VFB graph Clarified Minimum Off-Time graph 1, 2, 9, 11, 21-24

Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear .com  LINEAR TECHNOLOGY CORPORATION 2009 LT 1112 REV D • PRINTED IN USA RELATED PARTS TYPICAL APPLICATION PART NUMBER DESCRIPTION COMMENTS LT3755/LT3755-1 High Side 40V, 1MHz LED Controller with T rue Color 3000:1 PWM Dimming VIN: 4.5V to 40V, VOUT(MAX) = 60V, Dimming = 3000:1 T rue Color PWM™, ISD < 1µA, 3mm × 3mm QFN16, MSOP16E LT3756/LT3756-1 High Side 100V, 1MHz LED Controller with T rue Color 3000:1 PWM Dimming V IN: 6V to 100V, VOUT(MAX) = 100V, Dimming = 3000:1 T rue Color PWM, ISD < 1µA, 3mm × 3mm QFN16, MSOP16E LTC3783 High Side 36V, 1MHz LED Controller with T rue Color 3000:1 PWM Dimming V IN: 3V to 36V, VOUT(MAX) = 40V, Dimming = 3000:1 T rue Color PWM, ISD < 20µA, 4mm × 5mm DFN16, TSSOP16E LT3517 1.3A, 2.5MHz High Current LED Driver with 3000:1 Dimming V IN: 3V to 30V, Dimming = 3000:1 T rue Color PWM, ISD < 1µA, 4mm × 4mm QFN16 LT3518 2.3A, 2.5MHz High Current LED Driver with 3000:1 Dimming VIN: 3V to 30V, Dimming = 3000:1 T rue Color PWM, ISD < 1µA, 4mm × 4mm QFN16 LT3496 T riple Output 750mA, 2.1MHz High Current LED Driver with 3000:1 Dimming V IN: 3V to 30V, VOUT(MAX) = 40V, Dimming = 3000:1 T rue Color PWM, ISD < 1µA, 4mm × 5mm QFN28 LT3474/LT3474-1 36V, 1A (ILED), 2MHz Step-Down LED Driver VIN: 4V to 36V, VOUT(MAX) = 13.5V, Dimming = 400:1 T rue Color PWM, ISD < 1µA, TSSOP16E LT3475/LT3475-1 Dual 1.5A (ILED), 36V Step-Down LED Driver VIN: 4V to 36V, VOUT(MAX) = 13.5V, Dimming = 3000:1 T rue Color PWM, ISD < 1µA, TSSOP20E LT3476 Quad Output 1.5A, 2MHz High Current LED Driver with 1000:1 Dimming V IN: 2.8V to 16V, VOUT(MAX) = 36V, Dimming = 1000:1 T rue Color PWM, ISD < 10µA, 5mm × 7mm QFN10 LT3478/LT3478-1 4.5A, 2MHz High Current LED Driver with 3000:1 Dimming V IN: 2.8V to 36V, VOUT(MAX) = 40V, Dimming = 1000:1 T rue Color PWM, ISD < 10µA, 5mm × 7mm QFN10 12V, 40A Pulsed LED Driver EN/UVLO PWM CTRL_SEL EN/UVLO PWM CTRL_SEL HG V IN CBOOT VREF CTRL_L CTRL_H CTRL_T L T3743 RT SYNC SW LG GND VCHVCL SENSE+ SENSE– PWMGH PWMGL VCC_INT 220nF 1µH 22µF 33nF 330µF 1.25m/uni03A9 FB 1µF 51k 5.6nF 51k 5.6nF 150k 50k 50k C3 330µF 140k

3743 TA08

1µF 330µF 1µF RNTC 10k 220µF VIN 12V OUTPUT 40A MAXIMUM 220µF4.7µF 1µF 1µF 1nF SS 10/uni03A9 10/uni03A9 RHOT 499Ω L1: 1HLP5050FDER1R0M01 M1, M2: RJK0330DPB M3, M4: Si7234DP C1, C2, C3: PTPR33OM9L CTRL_SEL 5V/DIV ILED 20A/DIV SW 10V/DIV 20µs/DIV

3743 TA08b

VIN = 12V 4A to 40A LED Current Step