LT2216

LTC2192 LINER

Document overview

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• PDF pages: 28

Technical content

Electrical Specifications Subject to Change 219210p LTC2192 LTC2191/LTC2190

APPLICATIONS

n Portable Medical Imaging n Multi-Channel Data Acquisition n Nondestructive Testing TYPICAL APPLICATION

DESCRIPTION

16-Bit, 65Msps/40Msps/ 25Msps Low Power Dual ADCs The L TC®2192/L TC2191/L TC2190 are 2-channel, simul- taneous sampling 16-bit A/D converters designed for digitizing high frequency, wide dynamic range signals. They are perfect for demanding communications applications with AC performance that includes 77dB SNR and 90dB spurious free dynamic range (SFDR). Ultralow jitter of 0.07psRMS allows undersampling of IF frequencies with excellent noise performance. DC specs include ±2LSB INL (typ), ±0.5LSB DNL (typ) and no missing codes over temperature. The transition noise is 3.3LSBRMS. To minimize the number of data lines the digital outputs are serial LVDS. Each channel outputs one bit, two bits or four bits at a time. The LVDS drivers have optional internal termination and adjustable output levels to ensure clean signal integrity. The ENC+ and ENC– inputs may be driven differentially or single ended with a sine wave, PECL, LVDS, TTL or CMOS inputs. An internal clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles.

FEATURES

n 2-Channel Simultaneous Sampling ADC n Serial LVDS Outputs: 1, 2 or 4 Bits per Channel n 77dB SNR n 90dB SFDR n Low Power: 198mW/146mW/104mW Total n 99mW/73mW/52mW per Channel n Single 1.8V Supply n Selectable Input Ranges: 1VP-P to 2VP-P n 550MHz Full-Power Bandwidth S/H n Shutdown and Nap Modes n Serial SPI Port for Configuration n 52-Pin (7mm × 8mm) QFN Package 2-Tone FFT , fIN = 70MHz and 69MHz 16-BIT ADC CORE CH1 ANALOG INPUT CH2 ANALOG INPUT ENCODE INPUT S/H 16-BIT ADC CORE OUT1A OUT1B OUT1C OUT1D OUT2A OUT2B OUT2C OUT2D DATA CLOCK OUT FRAME S/H DATA SERIALIZER PLL OGND

219210 TA01a

1.8V1.8V L, L T , L TC, L TM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. FREQUENCY (MHz) –100 –110 –120 –70 –60 –80 –90AMPLITUDE (dBFS) –50 –30 –40 –20 –10 10 20 30

219210 G07

A IN+, AIN–, PAR/SER, SENSE Digital Input Voltage Operating Temperature Range (Notes 1, 2) 1615 17 18 19 TOP VIEW GND UKG PACKAGE 52-LEAD (7mm × 8mm) PLASTIC QFN 20 21 22 23 24 25 26 5152 50 49 48 47 46 45 44 43 42 41 CM1 GND AIN1+ AIN1– GND REFH REFL REFH REFL PAR/SER AIN2+ AIN2– GND VCM2 OUT1C+ OUT1C– OUT1D+ OUT1D– DCO+ DCO– OVDD OGND FR+ FR– OUT2A OUT2A– OUT2B+ OUT2B– VDD VDD SENSE GND V REF GND SDO GND OUT1A OUT1A– OUT1B+ OUT1B– VDD VDD ENC+ ENC– CS SCK SDI GND OUT2D– OUT2D+ OUT2C– OUT2C+ TJMAX = 150°C, θJA = 29°C/W EXPOSED PAD (PIN 53) IS GND, MUST BE SOLDERED TO PCB ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE L TC2192CUKG#PBF L TC2192CUKG#TRPBF L TC2192UKG 52-Lead (7mm × 8mm) Plastic QFN 0°C to 70°C L TC2192IUKG#PBF L TC2192IUKG#TRPBF L TC2192UKG 52-Lead (7mm × 8mm) Plastic QFN –40°C to 85°C L TC2191CUKG#PBF L TC2191CUKG#TRPBF L TC2191UKG 52-Lead (7mm × 8mm) Plastic QFN 0°C to 70°C L TC2191IUKG#PBF L TC2191IUKG#TRPBF L TC2191UKG 52-Lead (7mm × 8mm) Plastic QFN –40°C to 85°C L TC2190CUKG#PBF L TC2190CUKG#TRPBF L TC2190UKG 52-Lead (7mm × 8mm) Plastic QFN 0°C to 70°C L TC2190IUKG#PBF L TC2190IUKG#TRPBF L TC2190UKG 52-Lead (7mm × 8mm) Plastic QFN –40°C to 85°C Consult L TC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container . Consult L TC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear .com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear .com/tapeandreel/ PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS

CONVERTER CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) PARAMETER CONDITIONS L TC2192 L TC2191 L TC2190 UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX Resolution (No Missing Codes) l 16 16 16 Bits Integral Linearity Error Differential Analog Input (Note 6) l tbd ±2 tbd tbd ±2 tbd tbd ±2 tbd LSB Differential Linearity Error Differential Analog Input l –1 ±0.5 1 –1 ±0.5 1 –1 ±0.5 1 LSB Offset Error (Note 7) l –9 ±1.5 9 –9 ±1.5 9 –9 ±1.5 9 mV Gain Error Internal Reference External Reference l –2.1 ±1.5 –0.6 0.9 –2.1 ±1.5 –0.6 0.9 –2.1 ±1.5 –0.6 0.9 %FS %FS Offset Drift ±10 ±10 ±10 µV/°C Full-Scale Drift Internal Reference External Reference ±30 ±10 ±30 ±10 ±30 ±10 ppm/°C ppm/°C Gain Matching ±0.3 ±0.3 ±0.3 %FS Offset Matching ±1.5 ±1.5 ±1.5 mV T ransition Noise 3.3 3.3 3.2 LSBRMS ANALOG INPUT The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VIN Analog Input Range (AIN+ – AIN–) 1.7V < VDD < 1.9V l 1 to 2 VP-P VIN(CM) Analog Input Common Mode (AIN+ + AIN–)/2 Differential Analog Input (Note 8) l 0.7 VCM 1.25 V VSENSE External Voltage Reference Applied to SENSE External Reference Mode l 0.625 1.250 1.300 V IINCM Analog Input Common Mode Current Per Pin, 65Msps Per Pin, 40Msps Per Pin, 25Msps 104 µA µA µA IIN1 Analog Input Leakage Current (No Encode) 0 < AIN+, AIN– < VDD l –1 1 µA IIN2 PAR/SER Input Leakage Current 0 < PAR/SER < VDD l –3 3 µA IIN3 SENSE Input Leakage Current 0.625V < SENSE < 1.3V l –6 6 µA tAP Sample-and-Hold Acquisition Delay Time 0 ns tJITTER Sample-and-Hold Acquisition Delay Jitter Single-Ended Encode Differential Encode 0.07 0.09 psRMS psRMS CMRR Analog Input Common Mode Rejection Ratio 80 dB BW–3B Full-Power Bandwidth Figure 6 Test Circuit 550 MHz

DYNAMIC ACCURACY The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 5) SYMBOL PARAMETER CONDITIONS L TC2192 L TC2191 L TC2190 UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX SNR Signal-to-Noise Ratio 5MHz Input 30MHz Input 70MHz Input 140MHz Input l tbd 76.9 76.8 76.3 tbd 76.9 76.8 76.7 76.2 tbd 77.1 76.9 76.4 dBFS dBFS dBFS dBFS SFDR Spurious Free Dynamic Range 2nd or 3rd Harmonic 5MHz Input 30MHz Input 70MHz Input 140MHz Input l tbd tbd tbd dBFS dBFS dBFS dBFS Spurious Free Dynamic Range 4th Harmonic or Higher 5MHz Input 30MHz Input 70MHz Input 140MHz Input l tbd tbd tbd dBFS dBFS dBFS dBFS S/(N+D) Signal-to-Noise Plus Distortion Ratio 5MHz Input 30MHz Input 70MHz Input 140MHz Input l tbd 76.8 76.7 76.4 76.3 tbd 76.7 76.6 76.3 75.2 tbd 76.9 76.8 76.5 76.4 dBFS dBFS dBFS dBFS Crosstalk 10MHz Input –110 –110 –110 dBc INTERNAL REFERENCE CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) PARAMETER CONDITIONS MIN TYP MAX UNITS VCM Output Voltage IOUT = 0 0.5 • VDD – 25mV 0.5 • VDD 0.5 • VDD + 25mV V VCM Output Temperature Drift ±25 ppm/°C VCM Output Resistance –600µA < IOUT < 1mA 4 Ω VREF Output Voltage IOUT = 0 1.225 1.250 1.275 V VREF Output Temperature Drift ±25 ppm/°C VREF Output Resistance –400µA < IOUT < 1mA 7 Ω VREF Line Regulation 1.7V < VDD < 1.9V 0.6 mV/V DIGITAL INPUTS AND OUTPUTS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS ENCODE INPUTS (ENC+, ENC–) Differential Encode Mode (ENC– Not Tied to GND) VID Differential Input Voltage (Note 8) l 0.2 V VICM Common Mode Input Voltage Internally Set Externally Set (Note 8) l 1.1 1.2 1.6 V V VIN Input Voltage Range ENC+, ENC– to GND l 0.2 3.6 V RIN Input Resistance See Figure 10 10 kΩ CIN Input Capacitance (Note 8) 3.5 pF Single-Ended Encode Mode (ENC– Tied to GND) VIH High Level Input Voltage VDD =1.8V l 1.2 V VIL Low Level Input Voltage VDD =1.8V l 0.6 V

DIGITAL INPUTS AND OUTPUTS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VIN Input Voltage Range ENC+ to GND l 0 3.6 V RIN Input Resistance See Figure 11 30 kΩ CIN Input Capacitance (Note 8) 3.5 pF DIGITAL INPUTS (CS, SDI, SCK in Serial or Parallel Programming Mode. SDO in Parallel Programming Mode) VIH High Level Input Voltage VDD =1.8V l 1.3 V VIL Low Level Input Voltage VDD =1.8V l 0.6 V IIN Input Current VIN = 0V to 3.6V l –10 10 µA CIN Input Capacitance (Note 8) 3 pF SDO OUTPUT (Serial Programming Mode. Open-Drain Output. Requires 2k Pull-Up Resistor if SDO is Used) ROL Logic Low Output Resistance to GND VDD =1.8V , SDO = 0V 200 Ω IOH Logic High Output Leakage Current SDO = 0V to 3.6V l –10 10 µA COUT Output Capacitance (Note 8) 3 pF DIGITAL DATA OUTPUTS VOD Differential Output Voltage 100Ω Differential Load, 3.5mA Mode 100Ω Differential Load, 1.75mA Mode l l 247 125 350 175 454 250 mV mV VOS Common Mode Output Voltage 100Ω Differential Load, 3.5mA Mode 100Ω Differential Load, 1.75mA Mode l l 1.125 1.125 1.250 1.250 1.375 1.375 V V RTERM On-Chip Termination Resistance Termination Enabled, OVDD = 1.8V 100 Ω POWER REQUIREMENTS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 9) SYMBOL PARAMETER CONDITIONS L TC2192 L TC2191 L TC2190 UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX IVDD Analog Supply Current Sine Wave Input l 99 tbd 72 tbd 49 tbd mA IOVDD Digital Supply Current 1-Lane Mode, 1.75mA Mode 1-Lane Mode, 3.5mA Mode 2-Lane Mode, 1.75mA Mode 2-Lane Mode, 3.5mA Mode 4-Lane Mode, 1.75mA Mode 4-Lane Mode, 3.5mA Mode l l l l 10.2 17.6 13.6 24.7 21.1 39.6 tbd tbd tbd tbd tbd tbd 9.2 16.6 12.8 23.9 20.3 38.8 tbd tbd tbd tbd tbd tbd 8.7 16.1 12.3 23.4 19.9 38.4 tbd tbd tbd tbd tbd tbd mA mA mA mA mA mA PDISS Power Dissipation 1-Lane Mode, 1.75mA Mode 1-Lane Mode, 3.5mA Mode 2-Lane Mode, 1.75mA Mode 2-Lane Mode, 3.5mA Mode 4-Lane Mode, 1.75mA Mode 4-Lane Mode, 3.5mA Mode l l l l 198 211 203 223 217 250 tbd tbd tbd tbd tbd tbd 146 159 152 172 166 199 tbd tbd tbd tbd tbd tbd 104 118 111 131 124 158 tbd tbd tbd tbd tbd tbd mW mW mW mW mW mW PSLEEP Sleep Mode Power 1 1 1 mW PNAP Nap Mode Power 50 50 50 mW PDIFFCLK Power Increase with Diffential Encode Mode Enabled (No Increase for Sleep Mode) 20 20 20 mW

TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS L TC2192 L TC2191 L TC2190 UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX fS Sampling Frequency (Notes 10, 11) l 5 65 5 40 5 25 MHz tENCL ENC Low Time (Note 8) Duty Cycle Stabilizer Off Duty Cycle Stabilizer On l l 7.3 7.69 7.69 100 100 11.88 12.5 12.5 100 100 100 100 ns ns tENCH ENC High Time (Note 8) Duty Cycle Stabilizer Off Duty Cycle Stabilizer On l l 7.3 7.69 7.69 100 100 11.88 12.5 12.5 100 100 100 100 ns ns tAP Sample-and-Hold Acquistion Delay Time 0 0 0 ns SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Digital Data Outputs (RTERM = 100Ω Differential, CL = 2pF to GND On Each Output) tSER Serial Data Bit Period 4-Lane Output Mode 2-Lane Output Mode 1-Lane Output Mode 1/(4 • fS) 1/(8 • fS) 1/(16 • fS) Sec tFRAME FR to DCO Delay (Note 8) l 0.35 • tSER 0.5 • tSER 0.65 • tSER Sec tDATA Data to DCO Delay (Note 8) l 0.35 • tSER 0.5 • tSER 0.65 • tSER Sec tPD Propagation Delay (Note 8) l 0.7n + 2 • tSER 1.1n + 2 • tSER 1.5n + 2 • tSER Sec tr Output Rise Time Data, DCO, FR, 20% to 80% 0.17 ns tf Output Fall Time Data, DCO, FR, 20% to 80% 0.17 ns DCO Cycle-Cycle Jitter tSER = 1ns 60 psP-P Pipeline Latency 7 Cycles SPI Port Timing (Note 8) tSCK SCK Period Write Mode Readback Mode, CSDO = 20pF , RPULLUP = 2k l l 250 ns ns tS CS-to-CLK Setup Time l 5 ns tH SCK-to-CS Setup Time l 5 ns tDS SDI Setup Time l 5 ns tDH SDI Hold Time l 5 ns tDO SCK Falling to SDO Valid Readback Mode, CSDO = 20pF , RPULLUP = 2k l 125 ns Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to GND with GND and OGND shorted (unless otherwise noted). Note 3: When these pin voltages are taken below GND or above VDD, they will be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND or above VDD without latchup. Note 4: When these pin voltages are taken below GND they will be clamped by internal diodes. When these pin voltages are taken above VDD they will not be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND without latchup. Note 5: VDD = OVDD = 1.8V , fSAMPLE = 65MHz (L TC2192), 40MHz (L TC2191), or 25MHz (L TC2190), 2-lane output mode, differential ENC+/ENC– = 2VP-P sine wave, input range = 2VP-P with differential drive, unless otherwise noted. Note 6: Integral nonlinearity is defined as the deviation of a code from a best fit straight line to the transfer curve. The deviation is measured from the center of the quantization band. Note 7: Offset error is the offset voltage measured from –0.5LSB when the output code flickers between 0000 0000 0000 0000 and 1111 1111 1111 1111 in 2’s complement output mode. Note 8: Guaranteed by design, not subject to test. Note 9: VDD = OVDD=1.8V , fSAMPLE = 65MHz (L TC2192), 40MHz (L TC2191), or 25MHz (L TC2190), 2-lane output mode, ENC+ = single-ended 1.8V square wave, ENC– = 0V , input range = 2VP-P with differential drive, unless otherwise noted. The supply current and power dissipation specifications are totals for the entire IC, not per channel. Note 10: Recommended operating conditions. Note 11: The maximum sampling frequency depends on the speed grade of the part and also which serialization mode is used. The maximum serial data rate is 1000Mbps, so tSER must be greater than or equal to 1ns.

ENC– N tENCH tAP N+1 ENC+ DCO– FR– OUT#A– D15 D13 D11 D9 D15 D13 D11 D9 D15 OUT#A+ OUT#B– D14 D12 D10 D8 D14 D12 D10 D8 D14 OUT#B+ OUT#C– D7 D5 D3 D1 D7 D5 D3 D1 D7 OUT#C+ OUT#D– D6 D4 D2 D0 D6 D4 D2 D0 D6 OUT#D+ SAMPLE N–7 SAMPLE N–6 SAMPLE N–5

219210 TD01

D7 D5 D3 D1 D15 D13 D11 D9 D7 D5 D3 D1 D15 D13 D11 D6 D4 D2 D0 D14 D12 D10 D8 D6 D4 D2 D0 D14 D12 D10 ANALOG INPUT ENC– N tENCH tAP N+1 ENC+ DCO– FR+ OUT#A– OUT#A+ OUT#B– OUT#B+ DCO+ FR– tENCL tSER tSERtDATAtFRAME tPD tSER SAMPLE N–5

219210 TD02

SAMPLE N–6SAMPLE N–7 OUT#C+, OUT#C–, OUT#D+, OUT#D– ARE DISABLED

D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 N+1N D15 D14 D13 D12 ANALOG INPUT ENC– tENCH tAP ENC+ DCO– FR+ OUT#A– OUT#A+ DCO+ FR– tENCL tFRAME tDATA tSER tSERtPD tSER SAMPLE N–7 SAMPLE N–6 SAMPLE N–5

219210 TD03

OUT#B+, OUT#B–, OUT#C+, OUT#C–, OUT#D+, OUT#D– ARE DISABLED tS tDS A5 A4 A3 A2 A1 A0 XX D7 D6 D5 D4 D3 D2 D1 D0 XX XX XX XX XX XX XX CS SCK SDI R/W SDO HIGH IMPEDANCE SPI Port Timing (Readback Mode) SPI Port Timing (Write Mode) tDH tDO tSCK tH A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

219210 TD04

TYPICAL PERFORMANCE CHARACTERISTICS L TC2192: 64k Point FFT , fIN = 30MHz, –1dBFS, 65Msps L TC2192: 64k Point FFT , fIN = 70MHz, –1dBFS, 65Msps L TC2192: 64k Point FFT , fIN = 140MHz, –1dBFS, 65Msps L TC2192: 64k Point 2-Tone FFT , fIN = 69MHz, 70MHz, –7dBFS, 65Msps L TC2192: Shorted Input Histogram L TC2192: SNR vs Input Frequency, –1dBFS, 65Msps, 2V Range L TC2192: Integral Nonlinearity (INL) L TC2192: Differential Nonlinearity (DNL) L TC2192: 64k Point FFT , fIN = 5MHz, –1dBFS, 65Msps OUTPUT CODE –4.0 –3.0 –2.0 –1.0INL ERROR (LSB) 1.0 4.0 3.0 2.0 16384 32768 49152 65536

219210 G01

–1.0 –0.4 –0.2 –0.6 –0.8 DNL ERROR (LSB) 0.4 0.2 0.6 0.8 1.0

219210 G02

FREQUENCY (MHz) –100 –110 –120 –70 –60 –80 –90AMPLITUDE (dBFS) –50 –30 –40 –20 –10

219210 G03

FREQUENCY (MHz) –100 –110 –120 –70 –60 –80 –90AMPLITUDE (dBFS) –50 –30 –40 –20 –10

219210 G04

FREQUENCY (MHz) –100 –110 –120 –70 –60 –80 –90AMPLITUDE (dBFS) –50 –30 –40 –20 –10

219210 G05

FREQUENCY (MHz) –100 –110 –120 –70 –60 –80 –90AMPLITUDE (dBFS) –50 –30 –40 –20 –10

219210 G06

FREQUENCY (MHz) –100 –110 –120 –70 –60 –80 –90AMPLITUDE (dBFS) –50 –30 –40 –20 –10 10 20 30

2000 COUNT

219210 G08

INPUT FREQUENCY (MHz) SNR (dBFS) 50 100 150 200 250 300

219210 G09

TYPICAL PERFORMANCE CHARACTERISTICS L TC2192: IVDD vs Sample Rate, 5MHz, –1dBFS Sine Wave on Each Channel L TC2192: IOVDD vs Sample Rate, 5MHz, –1dBFS Sine Wave on Each Input L TC2192: SNR vs SENSE, fIN = 5MHz, –1dBFS L TC2192: 2nd, 3rd Harmonic vs Input Frequency, –1dBFS, 65Msps, 2V Range L TC2192: SFDR vs Input Level, fIN = 70MHz, 65Msps, 2V Range L TC2191: Integral Nonlinearity (INL) L TC2191: Differential Nonlinearity (DNL) L TC2191: 64k Point FFT , fIN = 5MHz, –1dBFS, 40Msps L TC2192: 2nd, 3rd Harmonic vs Input Frequency, –1dBFS, 65Msps, 1V Range 0 50 100 150 200 250 300 INPUT FREQUENCY (MHz) 100 2ND AND 3RD HARMONIC (dBFS)

219210 G10

INPUT FREQUENCY (MHz) 100 2ND AND 3RD HARMONIC (dBFS)

219210 G11

INPUT LEVEL (dBFS) –80 SFDR (dBc AND dBFS) 100 130 120 110

219210 G12

SAMPLE RATE (Msps) IVDD (mA) 100 110 10 20 30 40

219210 G13

SAMPLE RATE (Msps) IOVDD (mA)25 20 40

219210 G14

4 LANE, 3.5mA 2 LANE, 3.5mA 4 LANE, 1.75mA 1 LANE, 3.5mA 2 LANE, 1.75mA 1 LANE, 1.75mA SENSE PIN (V) 0.6 SNR (dBFS)

219210 G15

–4.0 –3.0 –2.0 –1.0INL ERROR (LSB) 1.0 4.0 3.0 2.0 16384 32768 49152 65536

219210 G16

–1.0 –0.4 –0.2 –0.6 –0.8 DNL ERROR (LSB) 0.4 0.2 0.6 0.8 1.0

219210 G17

FREQUENCY (MHz) –100 –110 –120 –70 –60 –80 –90AMPLITUDE (dBFS) –50 –30 –40 –20 –10 105 15 20

219210 G18

TYPICAL PERFORMANCE CHARACTERISTICS L TC2191: 64k Point FFT , fIN = 30MHz, –1dBFS, 40Msps L TC2191: 64k Point FFT , fIN = 70MHz, –1dBFS, 40Msps L TC2191: 64k Point FFT , fIN = 140MHz, –1dBFS, 40Msps L TC2191: Shorted Input Histogram L TC2191: SNR vs Input Frequency, –1dBFS, 40Msps, 2V Range L TC2191: SFDR vs Input Level, fIN = 70MHz, 40Msps, 2V Range L TC2191: 64k Point 2-Tone FFT , fIN = 69MHz, 70MHz, –7dBFS, 40Msps L TC2191: 2nd, 3rd Harmonic vs Input Frequency, –1dBFS, 40Msps, 2V Range L TC2191: 2nd, 3rd Harmonic vs Input Frequency, –1dBFS, 40Msps, 1V Range FREQUENCY (MHz) –100 –110 –120 –70 –60 –80 –90AMPLITUDE (dBFS) –50 –30 –40 –20 –10

219210 G19

FREQUENCY (MHz) –100 –110 –120 –70 –60 –80 –90AMPLITUDE (dBFS) –50 –30 –40 –20 –10

219210 G20

FREQUENCY (MHz) –100 –110 –120 –70 –60 –80 –90AMPLITUDE (dBFS) –50 –30 –40 –20 –10

219210 G21

FREQUENCY (MHz) –100 –110 –120 –70 –60 –80 –90AMPLITUDE (dBFS) –50 –30 –40 –20 –10

219210 G22

219210 G23

INPUT FREQUENCY (MHz) SNR (dBFS) 50 100 150 200 250 300

219210 G24

INPUT FREQUENCY (MHz) 100 2ND AND 3RD HARMONIC (dBFS)

219210 G25

INPUT FREQUENCY (MHz) 100 2ND AND 3RD HARMONIC (dBFS)

219210 G26

INPUT LEVEL (dBFS) –80 SFDR (dBc AND dBFS) 100 130 120 110

219210 G27

TYPICAL PERFORMANCE CHARACTERISTICS L TC2191: IVDD vs Sample Rate, 5MHz, –1dBFS Sine Wave Input on Each Channel L TC2191: IOVDD vs Sample Rate, 5MHz, –1dBFS Sine Wave on Each Input L TC2191: SNR vs SENSE, fIN = 5MHz, –1dBFS L TC2190: Integral Nonlinearity (INL) L TC2190: Differential Nonlinearity (DNL) L TC2190: 64k Point FFT , fIN = 5MHz, –1dBFS, 25Msps L TC2190: 64k Point FFT , fIN = 30MHz, –1dBFS, 25Msps L TC2190: 64k Point FFT , fIN = 70MHz, –1dBFS, 25Msps L TC2190: 64k Point FFT , fIN = 140MHz, –1dBFS, 25Msps SAMPLE RATE (Msps) IVDD (mA) 10 20 30 40

219210 G28

SAMPLE RATE (Msps) IOVDD (mA)25

219210 G29

4 LANE, 3.5mA 2 LANE, 3.5mA 4 LANE, 1.75mA 1 LANE, 3.5mA 2 LANE, 1.75mA 1 LANE, 1.75mA SENSE PIN (V) 0.6 SNR (dBFS)

219210 G30

–4.0 –3.0 –2.0 –1.0INL ERROR (LSB) 1.0 4.0 3.0 2.0 16384 32768 49152 65536

219210 G31

–1.0 –0.4 –0.2 –0.6 –0.8 DNL ERROR (LSB) 0.4 0.2 0.6 0.8 1.0

219210 G32

FREQUENCY (MHz) –100 –110 –120 –70 –60 –80 –90AMPLITUDE (dBFS) –50 –30 –40 –20 –10 105

219210 G33

FREQUENCY (MHz) –100 –110 –120 –70 –60 –80 –90AMPLITUDE (dBFS) –50 –30 –40 –20 –10

219210 G34

FREQUENCY (MHz) –100 –110 –120 –70 –60 –80 –90AMPLITUDE (dBFS) –50 –30 –40 –20 –10

219210 G35

FREQUENCY (MHz) –100 –110 –120 –70 –60 –80 –90AMPLITUDE (dBFS) –50 –30 –40 –20 –10

219210 G36

TYPICAL PERFORMANCE CHARACTERISTICS L TC2190: 64k Point, 2-Tone FFT , fIN = 69MHz, 70MHz, –7dBFS, 25Msps L TC2190: Shorted Input Histogram L TC2190: SNR vs Input Frequency, –1dBFS, 25Msps, 2V Range L TC2190: 2nd, 3rd Harmonic vs Input Frequency, –1dBFS, 25Msps, 2V Range L TC2190: SFDR vs Input Level, fIN = 70MHz, 25Msps, 2V Range L TC2190: 2nd, 3rd Harmonic vs Input Frequency, –1dBFS, 25Msps, 1V Range L TC2190: IVDD vs Sample Rate, 5MHz, –1dBFS Sine Wave Input on Each Channel L TC2190: IOVDD vs Sample Rate, 5MHz, –1dBFS Sine Wave on Each Input L TC2190: SNR vs SENSE, fIN = 5MHz, –1dBFS FREQUENCY (MHz) –100 –110 –120 –70 –60 –80 –90AMPLITUDE (dBFS) –50 –30 –40 –20 –10

219210 G37

219210 G38

INPUT FREQUENCY (MHz) SNR (dBFS) 50 100 150 200 250 300

219210 G39

INPUT FREQUENCY (MHz) 100 2ND AND 3RD HARMONIC (dBFS)

219210 G40

INPUT FREQUENCY (MHz) 100 2ND AND 3RD HARMONIC (dBFS)

219210 G41

INPUT LEVEL (dBFS) –80 SFDR (dBc AND dBFS) 100 130 120 110

219210 G42

SAMPLE RATE (Msps) IVDD (mA)45

219210 G43

SAMPLE RATE (Msps) I0VDD (mA)35

219210 G44

4 LANE, 3.5mA 2 LANE, 3.5mA 4 LANE, 1.75mA 1 LANE, 3.5mA 2 LANE, 1.75mA 1 LANE, 1.75mA SENSE PIN (V) 0.6 SNR (dBFS)

219210 G45

VCM1 (Pin 1): Common Mode Bias Output, Nominally Equal to VDD/2. VCM1 should be used to bias the common mode of the analog inputs of channel 1. Bypass to ground with a 0.1µF ceramic capacitor . GND (Pins 2, 5, 13, 22, 45, 47, 49, Exposed Pad Pin 65): ADC Power Ground. The exposed pad must be soldered to the PCB ground. AIN1+ (Pin 3): Channel 1 Positive Differential Analog Input. AIN1– (Pin 4): Channel 1 Negative Differential Analog Input. REFH (Pins 6, 8): ADC High Reference. See the Reference section in the Applications Information for recommended bypassing cIrcuits for REFH and REFL. REFL (Pins 7, 9): ADC Low Reference. See the Reference section in the Applications Information for recommended bypassing cIrcuits for REFH and REFL. PAR/SER (Pin 10): Programming Mode Selection Pin. Connect to ground to enable the serial programming mode. CS, SCK, SDI, SDO become a serial interface that control the A/D operating modes. Connect to V DD to enable the parallel programming mode where CS, SCK, SDI, SDO become parallel logic inputs that control a reduced set of the A/D operating modes. PAR/SER should be connected directly to ground or the VDD of the part and not be driven by a logic signal. AIN2+ (Pin 11): Channel 2 Positive Differential Analog Input. AIN2– (Pin 12): Channel 2 Negative Differential Analog Input. VCM2 (Pin 14): Common Mode Bias Output, Nominally Equal to VDD/2. VCM2 should be used to bias the common mode of the analog inputs of channel 2. Bypass to ground with a 0.1µF ceramic capacitor . VDD (Pins 15, 16, 51, 52): Analog Power Supply, 1.7V to 1.9V . Bypass to ground with 0.1µF ceramic capacitors. Adjacent pins can share a bypass capacitor . ENC+ (Pin 17): Encode Input. Conversion starts on the rising edge. ENC– (Pin 18): Encode Complement Input. Conversion starts on the falling edge. Tie to GND for single-ended encode mode. CS (Pin 19): In serial programming mode, (PAR/ SER = 0V), CS is the serial interface chip select input. When CS is low, SCK is enabled for shifting data on SDI into the mode control registers. In the parallel programming mode (PAR/SER = V DD), CS along with SCK selects 1-, 2- or 4-lane output mode (see Table 3). CS can be driven with 1.8V to 3.3V logic. SCK (Pin 20): In serial programming mode, (PAR/SER = 0V), SCK is the serial interface clock input. In the parallel programming mode (PAR/SER = VDD), SCK along with CS selects 1-, 2- or 4-lane output mode (see Table 3). SCK can be driven with 1.8V to 3.3V logic. SDI (Pin 21): In Serial Programming Mode, (PAR/SER = 0V), SDI is the Serial Interface Data Input. Data on SDI is clocked into the mode control registers on the rising edge of SCK. In the parallel programming pode (PAR/SER = VDD), SDI can be used to power down the part. SDI can be driven with 1.8V to 3.3V logic. OGND (Pin 33): Output Driver Ground. This pin must be shorted to the ground plane by a very low inductance path. Use multiple vias close to the pin. OVDD (Pin 34): Output Driver Supply. Bypass to ground with a 0.1µF ceramic capacitor . SDO (Pin 46): In serial programming mode, (PAR/ SER = 0V), SDO is the optional serial interface data output. Data on SDO is read back from the mode control regis - ters and can be latched on the falling edge of SCK. SDO is an open-drain NMOS output that requires an external 2k pull-up resistor to 1.8V to 3.3V . If read back from the mode control registers is not needed, the pull-up resistor is not necessary and SDO can be left unconnected. In the parallel programming mode (PAR/SER = VDD), SDO selects 3.5mA or 1.75mA LVDS output currents. When used as an input, SDO can be driven with 1.8V to 3.3V logic through a 1k series resistor .

VREF (Pin 48): Reference Voltage Output. Bypass to ground with a 2.2µF ceramic capacitor . The reference output is nominally 1.25V . SENSE (Pin 50): Reference Programming Pin. Connecting SENSE to VDD selects the internal reference and a ±1V input range. Connecting SENSE to ground selects the internal reference and a ±0.5V input range. An external reference between 0.625V and 1.3V applied to SENSE selects an input range of ±0.8 • VSENSE. LVDS Outputs The following pins are differential LVDS outputs. The output current level is programmable. There is an optional internal 100Ω termination resistor between the pins of each LVDS output pair . PIN FUNCTIONS OUT2D–/OUT2D+, OUT2C –/OUT2C+, OUT2B –/OUT2B+, OUT2A–/OUT2A+ (Pins 23/24, 25/26, 27/28, 29/30): Serial Data Outputs for Channel 2. In 1-lane output mode only OUT2A–/OUT2A+ are used. In 2-Lane output mode only OUT2A–/OUT2A+ and OUT2B–/OUT2B+ are used. FR–/FR+ (Pins 31/32): Frame Start Outputs. DCO–/DCO+ (Pins 35/36): Data Clock Outputs. OUT1D–/OUT1D+, OUT1C –/OUT1C+, OUT1B –/OUT1B+, OUT1A–/OUT1A+ (Pins 37/38, 39/40, 41/42, 43/44): Serial Data Outputs for Channel 1. In 1-lane output mode only OUT1A–/OUT1A+ are used. In 2-lane output mode only OUT1A–/OUT1A+ and OUT1B–/OUT1B+ are used.

219210 F01

Figure 1. Functional Block Diagram

ferentially or single ended for lower power consumption. VCM1 or VCM2 output pins, which are nominally V DD/2. difference between the inputs.

219210 F02

Figure 2. Equivalent Input Circuit. Only One of T wo Analog Channels Is Shown

219210 F03

Figure 3. Analog Input Circuit Using a T ransformer .

219210 F04

Figure 4. Recommended Front-End Circuit for Input Frequencies

219210 F05

Figure 5. Recommended Front-End Circuit for Input Frequencies

219210 F06

Figure 6. Recommended Front-End Circuit for Input Frequencies

219210 F07

Figure 7. Front-End Circuit Using a High Speed resulting in lower A/D distortion. voltage can be optimally set to minimize distortion.

using the internal reference, connect SENSE to ground. 1.25V reference voltage to SENSE (Figure 9).

219210 F09

Figure 9. Using an External 1.25V Reference

219210 F08a

219210 F08b

219210 F08c

219210 F08d

ENC+ should have fast rise and fall times. Figure 12. Sinusoidal Encode Drive

219210 F13

Figure 13. PECL or LVDS Encode Drive

219210 F12

219210 F10

Figure 10. Equivalent Encode Input Circuit

219210 F11

Figure 11. Equivalent Encode Input Circuit requires 25µs to lock onto the input clock. of the applied encode signal to vary from 30% to 70%.

cycle stabilizer must be enabled. isolated from the A/D core power and ground. Table 1. Maximum Sampling Frequency for All Serialization In LVDS mode, the default output driver current is 3.5mA. Table 2. Output Codes vs Input Voltage inductive coupling or coupling through the ground plane.

but the differential impedance may remain low. ming mode), or by SDI (parallel programming mode). A/D will stabilize after 2ms. register A1 in the serial programming mode. the more commonly used modes. modes set by CS, SCK, SDI and SDO. Table 3. Parallel Programming Mode Control Bits (PAR/SER = VDD) SCK. Any SCK rising edges after the first 16 are ignored. The data transfer ends when CS is taken high again.

next seven bits are the address of the register (A6:A0). The final eight bits are the register data (D7:D0). not updated and data on SDI is ignored. through SDO, an external 2k pull-up resistor is required. Table 4. Serial Programming Mode Register Map (PAR/SER = GND) 1 = Software Reset. All Mode Control Registers are Reset to 00h. The ADC is Momentarily Placed in Sleep Mode. Bits 6-0 Unused, Don’t Care Bits. 1 = Clock Duty Cycle Stabilizer Off. This is not recommended. 1XX = Sleep Mode. Both Channels are Disabled. Table 4 shows a map of the mode control registers. complete, bit D7 is automatically set back to zero.

REGISTER A2: OUTPUT MODE REGISTER (ADDRESS 02h) D7 D6 D5 D4 D3 D2 D1 D0 ILVDS2 ILVDS1 ILVDS0 TERMON OUTOFF OUTTEST OUTMODE1 OUTMODE0 Bits 7-5 ILVDS2:ILVDS0 LVDS Output Current Bits 000 = 3.5mA LVDS Output Driver Current 001 = 4.0mA LVDS Output Driver Current 010 = 4.5mA LVDS Output Driver Current 011 = Not Used 100 = 3.0mA LVDS Output Driver Current 101 = 2.5mA LVDS Output Driver Current 110 = 2.1mA LVDS Output Driver Current 111 = 1.75mA LVDS Output Driver Current Bit 4 TERMON LVDS Internal Termination Bit 0 = Internal Termination Off 1 = Internal Termination On. LVDS Output Driver Current is 2× the Current Set by ILVDS2:ILVDS0 Bit 3 OUTOFF Output Disable Bit 0 = Digital Outputs are Enabled 1 = Digital Outputs are Disabled Bit 2 OUTTEST Digital Output Test Pattern Control Bit 0 = Digital Output Test Pattern Off 1 = Digital Output Test Pattern On Bits 1-0 OUTMODE1:OUTMODE0 Digital Output Mode Control Bits 00 = 2-Lane Output Mode 01 = 4-Lane Output Mode 10 = 1-Lane Output Mode 11 = Not Used REGISTER A3: TEST PATTERN MSB REGISTER (ADDRESS 03h) D7 D6 D5 D4 D3 D2 D1 D0 TP15 TP14 TP13 TP12 TP11 TP10 TP9 TP8 Bits 7-0 TP15:TP8 Test Pattern Data Bits (MSB) TP15:TP8 Set the Test Pattern for Data Bit 15 (MSB) Through Data Bit 8. REGISTER A4: TEST PATTERN LSB REGISTER (ADDRESS 04h) D7 D6 D5 D4 D3 D2 D1 D0 TP7 TP6 TP5 TP4 TP3 TP2 TP1 TP0 Bits 7-0 TP7:TP0 Test Pattern Data Bits (LSB) TP7:TP0 Set the Test Pattern for Data Bit 7 Through Data Bit 0 (LSB).

The L TC2192/L TC2191/L TC2190 require a printed circuit board with a clean unbroken ground plane. A multilayer board with an internal ground plane in the first layer be - neath the ADC is recommended. Layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. In particular , care should be taken not to run any digital track alongside an analog signal track or underneath the ADC. High quality ceramic bypass capacitors should be used at the VDD, OVDD, VCM, VREF, REFH and REFL pins. Bypass capacitors must be located as close to the pins as possible. Size 0402 ceramic capacitors are recommended. The traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible. Of particular importance is the capacitor between REFH and REFL. This capacitor should be on the same side of the circuit board as the A/D, and as close to the device as possible. The analog inputs, encode signals, and digital outputs should not be routed next to each other . Ground fill and grounded vias should be used as barriers to isolate these signals from each other . HEAT TRANSFER Most of the heat generated by the L TC2192/L TC2191/ L TC2190 is transferred from the die through the bottom- side exposed pad and package leads onto the printed circuit board. For good electrical and thermal performance, the exposed pad must be soldered to a large grounded pad on the PC board. This pad should be connected to the internal ground planes by an array of vias. TYPICAL APPLICATIONS LTC2192 VCM1 GND AIN1+ AIN1– GND REFH REFL REFH REFL PAR/SER A IN2+ AIN2– GND VCM2 OUT1C+ OUT1C– OUT1D+ OUT1D– DCO+ DCO– OVDD OGND FR+ FR– OUT2A+ OUT2A– OUT2B+ OUT2B– VDD VDD SENSE GND VREF GND SDO GND OUT1A+ OUT1A– OUT1B+ OUT1B– V DD VDD ENC+ ENC– CS SCK SDI GND OUT2D OUT2D+ OUT2C– OUT2C+ + – CN1 C3 0.1µF C29 0.1µF 2.2µF C2 0.1µF C16 0.1µF

219210 TA02

0.1µF 0.1µF 0.1µF VDD SENSE SDO VDD ENCODE INPUT SPI PORT PAR/SER A IN1+ AIN1– AIN2+ AIN2–

Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However , no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. PACKAGE DESCRIPTION 52-Lead Plastic QFN (7mm × 8mm) (Reference L TC DWG # 05-08-1729 Rev Ø) 7.00 ± 0.10 (2 SIDES) NOTE: 1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE PIN 1 TOP MARK (SEE NOTE 6) PIN 1 NOTCH R = 0.30 TYP OR 0.35 × 45°C CHAMFER 0.40 ± 0.10 5251 BOTTOM VIEW—EXPOSED PAD TOP VIEW SIDE VIEW

6.50 REF

(2 SIDES) 8.00 ± 0.10 (2 SIDES)

5.50 REF

(2 SIDES)0.75 ± 0.05 0.75 ± 0.05 R = 0.115 TYP R = 0.10 TYP 0.25 ± 0.05

0.50 BSC

0.200 REF

0.00 – 0.05 6.45 ±0.10 5.41 ±0.10 0.00 – 0.05 (UKG52) QFN REV Ø 0306 (2 SIDES) 5.41 ±0.05 6.45 ±0.05 RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 0.70 ±0.05 6.10 ±0.05 7.50 ±0.05 0.25 ±0.05

Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear .com  LINEAR TECHNOLOGY CORPORA TION 2011 LT 0111 • PRINTED IN USA TYPICAL APPLICATION 2-Tone FFT , fIN = 70MHz and 69MHz 16-BIT ADC CORE CH1 ANALOG INPUT CH2 ANALOG INPUT ENCODE INPUT S/H 16-BIT ADC CORE OUT1A OUT1B OUT1C OUT1D OUT2A OUT2B OUT2C OUT2D DATA CLOCK OUT FRAME S/H DATA SERIALIZER PLL OGND V DD OVDD 1.8V1.8V FREQUENCY (MHz) –100 –110 –120 –70 –60 –80 –90AMPLITUDE (dBFS) –50 –30 –40 –20 –10 10 20 30 PART NUMBER DESCRIPTION COMMENTS ADCs L TC2259-14/L TC2260-14/ L TC2261-14 14-Bit, 80Msps/105Msps/125Msps 1.8V ADCs, Ultralow Power 89mW/106mW/127mW , 73.4dB SNR, 85dB SFDR, DDR LVDS/DDR CMOS/CMOS Outputs, 6mm × 6mm QFN-36 L TC2262-14 14-Bit, 150Msps 1.8V ADC, Ultralow Power 149mW , 72.8dB SNR, 88dB SFDR, DDR LVDS/DDR CMOS/CMOS Outputs, 6mm × 6mm QFN-36 L TC2266-14/L TC2267-14/ L TC2268-14 14-Bit, 80Msps/105Msps/125Msps 1.8V Dual ADCs, Ultralow Power 216mW/250mW/293mW , 73.4dB SNR, 85dB SFDR, Serial LVDS Outputs, 6mm × 6mm QFN-36 L TC2266-12/L TC2267-12/ L TC2268-12 12-Bit, 80Msps/105Msps/125Msps 1.8V Dual ADCs, Ultralow Power 216mW/250mW/293mW , 70.5dB SNR, 85dB SFDR, Serial LVDS Outputs, 6mm × 6mm QFN-36 L TC2208 16-Bit, 130Msps 3.3V ADC 1250mW , 77.7dB SNR, 100dB SFDR, CMOS/LVDS Outputs, 9mm × 9mm QFN-64 L T2207/L T2206 16-Bit, 105Msps/80Msps 3.3V ADCs 900mW/725mW , 77.9dB SNR, 100dB SFDR, CMOS Outputs, 7mm × 7mm QFN-48 L T2217/L T2216 16-Bit, 105Msps/80Msps 3.3V ADCs 1190mW/970mW , 81.2dB SNR, 100dB SFDR, CMOS/LVDS Outputs, 9mm × 9mm QFN-64 RF Mixers/Demodulators L TC5517 40MHz to 900MHz Direct Conversion Quadrature Demodulator High IIP3: 21dBm at 800MHz, Integrated LO Quadrature Generator L TC5527 400MHz to 3.7GHz High Linearity Downconverting Mixer 24.5dBm IIP3 at 900MHz, 23.5dBm IIP3 at 3.5GHz, NF = 12.5dB, 50Ω Single-Ended RF and LO Ports L TC5557 400MHz to 3.8GHz High Linearity Downconverting Mixer Operation, Integrated T ransformer L TC5575 800MHz to 2.7GHz Direct Conversion Quadrature Demodulator High IIP3: 28dBm at 900MHz, Integrated LO Quadrature Generator , Integrated RF and LO T ransformer Amplifiers/Filters L TC6412 800MHz, 31dB Range, Analog-Controlled Variable Gain Amplifier Continuously Adjustable Gain Control, 35dBm OIP3 at 240MHz, 10dB Noise Figure, 4mm × 4mm QFN-24 L TC6420-20 1.8GHz Dual Low Noise, Low Distortion Differential ADC Drivers for 300MHz IF Fixed Gain 10V/V , 1nV/√Hz Total Input Noise, 80mA Supply Current per Amplifier , 3mm × 4mm QFN-20 L TC6421-20 1.3GHz Dual Low Noise, Low Distortion Differential ADC Drivers Fixed Gain 10V/V , 1nV/√Hz Total Input Noise, 40mA Supply Current per Amplifier , 3mm × 4mm QFN-20 L TC6605-7/L TC6605-10/ L TC6605-14 Dual Matched 7MHz/10MHz/14MHz Filters with ADC Drivers Dual Matched 2nd Order Lowpass Filters with Differential Drivers, Pin-Programmable Gain, 6mm × 3mm DFN-22 Signal Chain Receivers L TM9002 14-Bit Dual Channel IF/Baseband Receiver Subsystem Integrated High Speed ADC, Passive Filters and Fixed Gain Differential Amplifiers