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∆∑ RMS-to-DC Converter
applicaTions
L, L T , L TC, L TM, Linear Technology and the Linear logo are registered trademarks and No Latency DS is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents including 6359576, 6362677, 6516291 and 6651036. n Simple to Use, Requires One Capacitor n True RMS DC Conversion Using DS T echnology n High Accuracy: 1% Gain Accuracy from 50Hz to 1kHz 25% Total Error from 50Hz to 1kHz n High Linearity: 02% Linearity Allows Simple System Calibration n Low Supply Current: 5µA Typ, 170µA Max n Ultralow Shutdown Current: 0.1 µA n Constant Bandwidth: In dependent of Input Voltage 0kHz –3dB, 6kHz ±1% n Flexible Supplies: 7V to 5.5V Single Supply Up t o ±5.5V Dual Supply n Flexible Inputs: Di fferential or Single-Ended Ra il-to-Rail Common Mode Voltage Range Up t o 1VPEAK Differential Voltage n Flexible Output: Rai l-to-Rail Output Se parate Output Reference Pin Allows Level Shifting n Wide Temperature Range: 5°C to 125°C n Small Size: Sp ace Saving 8-Pin MSOP Package The L TC®1966 is a true RMS-to-DC converter that utilizes an innovative patented DS computational technique. The internal delta sigma cir cuitry of the L TC1966 makes it sim- pler to use, more accurate, lower power and dramatically more flexible than conventional log antilog RMS-to-DC converters. The L TC1966 accepts single-ended or differential input signals (for EMI/RFI rejection) and supports crest factors up to 4. Common mode input range is rail-to-rail. Differential input range is 1V PEAK, and offers unprecedented linearity. Unlike previously available RMS-to-DC converters, the superior linearity of the L TC1966 allows hassle free system calibration at any input voltage. The L TC1966 also has a rail-to-rail output with a separate output reference pin providing flexible level shifting. The L TC1966 operates on a single power supply from 2.7V to 5.5V or dual supplies up to ±5.5V . A low power shutdown mode reduces supply current to 0.5µA. The L TC1966 is insensitive to PC board soldering and stresses, as well as operating temperature. The L TC1966 is packaged in the space saving MSOP package which is ideal for portable applications. n T rue RMS Digital Multimeters and Panel Meters n T rue RMS AC + DC Measurements Single Supply RMS-to-DC Converter Quantum Leap in Linearity Performance CAVE 1µF VOUT
1966 TA01
2.7V TO 5.5V OUTPUT DIFFERENTIAL INPUT L TC1966 VDD 0.1µF OPT . AC COUPLING VSSEN GND OUT RTN IN1 IN2 VIN (mV ACRMS) –1.0LINEARITY ERROR (VOUT mV DC – VIN mV ACRMS) –0.6 –0.2 0.2 –0.8 –0.4 100 200 300 400
1966 TA01b
LTC1966, ∆∑ 60Hz SINEWAVES CONVENTIONAL LOG/ANTILOG
pin conFiguraTionabsoluTe MaxiMuM raTings (Note 1) GND IN1 IN2 V SS ENABLE V DD OUT RTN V OUT TOP VIEW MS8 PACKAGE 8-LEAD PLASTIC MSOP TJMAX = 150°C, θJA = 220°C/W orDer inForMaTion LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE L TC1966CMS8#PBF L TC1966CMS8#TRPBF LTT G 8-Lead Plastic MSOP 0°C to 70°C L TC1966IMS8#PBF L TC1966IMS8#TRPBF LTT H 8-Lead Plastic MSOP –40°C to 85°C L TC1966HMS8#PBF L TC1966HMS8#TRPBF LTT G 8-Lead Plastic MSOP –40°C to 125°C L TC1966MPMS8#PBF L TC1966MPMS8#TRPBF LTT G 8-Lead Plastic MSOP –55°C to 125°C Consult L TC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container . For more information on lead free part marking, go to: http://www.linear .com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear .com/tapeandreel/
elecTrical characTerisTics
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Conversion Accuracy GERR Conversion Gain Error 50Hz to 1kHz Input (Notes 6, 7) L TC1966C, L TC1966I L TC1966H, L TC1966MP l l ±0.1 ±0.3 ±0.4 ±0.7 V OOS Output Offset Voltage (Notes 6, 7) L TC1966C, L TC1966I L TC1966H, L TC1966MP l l 0.1 0.2 0.4 0.6 mV mV mV LIN ERR Linearity Error 50mV to 350mV (Notes 7, 8) l 0.02 0.15 % The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VDD = 5V , VSS = – 5V , VOUTRTN = 0V , CAVE = 10µF , VIN = 200mVRMS, VENABLE = 0.5V unless otherwise noted. Supply Voltage mA 10mA Operating Temperature Range (Note 4) LT 40°C to 85°C LT 40°C to 125°C LT 55°C to 125°C Specified Temperature Range (Note 5) LT 40°C to 85°C LT 40°C to 125°C LT 55°C to 125°C 0°C 65°C to 150°C 00°C
elecTrical characTerisTics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VDD = 5V , VSS = – 5V , VOUTRTN = 0V , CAVE = 10µF , VIN = 200mVRMS, VENABLE = 0.5V unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS PSRR Power Supply Rejection (Note 9) L TC1966C, L TC1966I L TC1966H, L TC1966MP l l 0.02 0.15 0.20 0.3 V IOS Input Offset Voltage (Notes 6, 7, 10) l 0.02 0.8 1.0 mV mV Accuracy vs Crest Factor (CF) CF = 4 60Hz Fundamental, 200mV RMS (Note 11) l –1 2 mV CF = 5 60Hz Fundamental, 200mVRMS (Note 11) l –20 30 mV Input Characteristics IVR Input Voltage Range (Note 14) l VSS VDD V ZIN Input Impedance Average, Differential (Note 12) Average, Common Mode (Note 12) 100 MΩ MΩ CMRRI Input Common Mode Rejection (Note 13) l 7 200 µV/V VIMAX Maximum Input Swing Accuracy = 1% (Note 14) l 1 1.05 V VIMIN Minimum RMS Input l 5 mV PSRRI Power Supply Rejection VDD Supply (Note 9) VSS Supply (Note 9) l l 250 120 600 300 µV/V µV/V Output Characteristics OVR Output Voltage Range l VSS VDD V ZOUT Output Impedance VENABLE = 0.5V (Note 12) VENABLE = 4.5V l 75 85 95 kΩ kΩ CMRRO Output Common Mode Rejection (Note 13) l 16 200 µV/V VOMAX Maximum Differential Output Swing Accuracy = 2%, DC Input (Note 14) l 1.0 0.9 1.05 V V PSRRO Power Supply Rejection V DD Supply (Note 9) VSS Supply (Note 9) l l 250 1000 500 µV/V µV/V Frequency Response f1P 1% Additional Error (Note 15) C AVE = 10µF 6 kHz f10P 10% Additional Error (Note 15) C AVE = 10µF 20 kHz f– 3dB ±3dB Frequency (Note 15) 800 kHz Power Supplies V DD Positive Supply Voltage l 2.7 5.5 V VSS Negative Supply Voltage (Note 16) l –5.5 0 V IDD Positive Supply Current IN1 = 20mV , IN2 = 0V IN1 = 200mV , IN2 = 0V l 155 158 170 µA µA I SS Negative Supply Current IN1 = 20mV , IN2 = 0V l 12 20 µA Shutdown Characteristics IDDS Supply Currents VENABLE = 4.5V l 0.5 10 µA ISSS Supply Currents VENABLE = 4.5V L TC1966H, L TC1966MP l l –0.1 µA µA I IH ENABLE Pin Current High VENABLE = 4.5V l –0.3 –0.05 µA
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The inputs (IN1, IN2) are protected by shunt diodes to V SS and VDD. If the inputs are driven beyond the rails, the current should be limited to less than 10mA. Note 3: The L TC1966 output (V OUT) is high impedance and can be overdriven, either sinking or sourcing current, to the limits stated. Note 4: The L TC1966C/L TC1966I are guaranteed functional over the operating temperature range of – 40°C to 85°C. The L TC1966H/ L TC1966MP are guaranteed functional over the operating temperature range of –55°C to 125°C. Note 5: The L TC1966C is guaranteed to meet specified performance from 0°C to 70°C. The L TC1966C is designed, characterized and expected to meet specified performance from –40°C to 85°C but is not tested nor QA sampled at these temperatures. The L TC1966I is guaranteed to meet specified performance from –40°C to 85°C. The L TC1966H is guaranteed to meet specified performance from –40°C to 125°C. The L TC1966MP is guaranteed to meet specified performance from –55°C to 125°C. Note 6: High speed automatic testing cannot be performed with C AVE = 10µF . The L TC1966 is 100% tested with CAVE = 22nF . Correlation tests have shown that the performance limits above can be guaranteed with the additional testing being performed to guarantee proper operation of all the internal circuitry. Note 7: High speed automatic testing cannot be performed with 60Hz inputs. The L TC1966 is 100% tested with DC and 10kHz input signals. Measurements with DC inputs from 50mV to 350mV are used to calculate the four parameters: G ERR, VOOS, VIOS and linearity error . Correlation tests have shown that the performance limits above can be guaranteed with the additional testing being performed to guarantee proper operation of all internal circuitry. Note 8: The L TC1966 is inherently very linear . Unlike older log/antilog circuits, its behavior is the same with DC and AC inputs, and DC inputs are used for high speed testing. Note 9: The power supply rejections of the L TC1966 are measured with DC inputs from 50mV to 350mV . The change in accuracy from V DD = 2.7V to VDD = 5.5V with VSS = 0V is divided by 2.8V . The change in accuracy from VSS = 0V to VSS = –5.5V with VDD = 5.5V is divided by 5.5V . Note 10: Previous generation RMS-to-DC converters required nonlinear input stages as well as a nonlinear core. Some parts specify a DC reversal error , combining the effects of input nonlinearity and input offset voltage. The L TC1966 behavior is simpler to characterize and the input offset voltage is the only significant source of DC reversal error . Note 11: High speed automatic testing cannot be performed with 60Hz inputs. The L TC1966 is 100% tested with DC stimulus. Correlation tests have shown that the performance limits above can be guaranteed with the additional testing being performed to verify proper operation of all internal circuitry. Note 12: The L TC1966 is a switched capacitor device and the input/ output impedance is an average impedance over many clock cycles. The input impedance will not necessarily lead to an attenuation of the input signal measured. Refer to the Applications Information section titled Input Impedance for more information. Note 13: The common mode rejection ratios of the L TC1966 are measured with DC inputs from 50mV to 350mV . The input CMRR is defined as the change in V IOS measured between input levels of VSS to VSS + 350mV and input levels of VDD – 350mV to VDD divided by VDD – VSS – 350mV . The output CMRR is defined as the change in VOOS measured with OUT RTN = VSS and OUT RTN = VDD – 350mV divided by VDD – VSS – 350mV . Note 14: Each input of the L TC1966 can withstand any voltage within the supply range. These inputs are protected with ESD diodes, so going beyond the supply voltages can damage the part if the absolute maximum current ratings are exceeded. Likewise for the output pins. The L TC1966 input and output voltage swings are limited by internal clipping. The maximum differential input of the L TC1966 (referred to as maximum input swing) is 1V . This applies to either input polarity, so it can be thought of as ±1V . Because the differential input voltage gets processed by the L TC1966 with gain, it is subject to internal clipping. Exceeding the 1V maximum can, depending on the input crest factor , impact the accuracy of the output voltage, but does not damage the part. Fortunately, the L TC1966’s ∆∑ topology is relatively tolerant of momentary internal clipping. The input clipping is tested with a crest factor of 2, while the output clipping is tested with a DC input. Note 15: The L TC1966 exploits oversampling and noise shaping to reduce the quantization noise of internal 1-bit analog-to-digital conversions. At higher input frequencies, increasingly large portions of this noise are aliased down to DC. Because the noise is shifted in frequency, it becomes a low frequency rumble and is only filtered at the expense of increasingly long settling times. The L TC1966 is inherently wideband, but the output accuracy is degraded by this aliased noise. These specifications apply with C AVE = 10µF and constitute a 3-sigma variation of the output rumble. Note 16: The L TC1966 can operate down to 2.7V single supply but cannot operate at ±2.7V . This additional constraint on V SS can be expressed mathematically as – 3 • (VDD – 2.7V) ≤ VSS ≤ Ground. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS IIL ENABLE Pin Current Low VENABLE = 0.5V L TC1966H, L TC1966MP l l –10 –1 –0.1 µA µA VTH ENABLE Threshold Voltage VDD = 5V , VSS = –5V VDD = 5V , VSS = GND VDD = 2.7V , VSS = GND 2.4 2.1 1.3 V V V V HYS ENABLE Threshold Hysteresis 0.1 V The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VDD = 5V , VSS = – 5V , VOUTRTN = 0V , CAVE = 10µF , VIN = 200mVRMS, VENABLE = 0.5V unless otherwise noted.
Typical perForMance characTerisTics Gain and Offsets vs Input Common Mode INPUT COMMON MODE (V) –0.5 GAIN ERROR (%) OFFSET VOLTAGE (mV) –0.4 –0.2 –0.1 0.5 0.2
1966 G02
–0.3 0.3 0.4 0.1 –0.5 –0.4 –0.2 –0.1 0.5 0.2 –0.3 0.3 0.4 0.1 VDD = 5V VSS = GND VIOS VOOS GAIN ERROR Gain and Offsets vs Input Common Mode INPUT COMMON MODE (V) –0.5 GAIN ERROR (%) OFFSET VOLTAGE (mV) –0.4 –0.2 –0.1 0.5 0.2 –3 –1 0 5 4
1966 G03
–0.3 0.3 0.4 0.1 –0.5 –0.4 –0.2 –0.1 0.5 0.2 –0.3 0.3 0.4 0.1 –4 –2 1 2 3 VDD = 5V VSS = –5V VIOS VOOS GAIN ERROR Gain and Offsets vs Output Common Mode OUTPUT COMMON MODE (V) –0.5 GAIN ERROR (%) OFFSET VOLTAGE (mV) –0.4 –0.2 –0.1 0.5 0.2
1966 G05
–0.3 0.3 0.4 0.1 –0.5 –0.4 –0.2 –0.1 0.5 0.2 –0.3 0.3 0.4 0.1 VDD = 5V VSS = GND VIOS VOOS GAIN ERROR Gain and Offsets vs Output Common Mode OUTPUT COMMON MODE (V) –0.5 GAIN ERROR (%) OFFSET VOLTAGE (mV) –0.4 –0.2 –0.1 0.5 0.2 –3 –1 0 5 4
1966 G06
–0.3 0.3 0.4 0.1 –0.5 –0.4 –0.2 –0.1 0.5 0.2 –0.3 0.3 0.4 0.1 –4 –2 1 2 3 VDD = 5V VSS = –5V VIOS VOOSGAIN ERROR Gain and Offsets vs Input Common Mode INPUT COMMON MODE (V) –0.5 GAIN ERROR (%) OFFSET VOLTAGE (mV) –0.4 –0.2 –0.1 0.5 0.2 0.6 1.2 1.5 2.7
1966 G01
–0.3 0.3 0.4 0.1 –1.0 –0.8 –0.4 –0.2 1.0 0.4 –0.6 0.6 0.8 0.2 VDD = 2.7V VSS = GND VIOS VOOS GAIN ERROR Gain and Offsets vs Output Common Mode OUTPUT COMMON MODE (V) –0.5 GAIN ERROR (%) OFFSET VOLTAGE (mV) –0.4 –0.2 –0.1 0.5 0.2 0.6 1.2 1.5 2.7
1966 G04
–0.3 0.3 0.4 0.1 –1.0 –0.8 –0.4 –0.2 1.0 0.4 –0.6 0.6 0.8 0.2 VDD = 2.7V VSS = GND VIOS VOOS GAIN ERROR Gain and Offsets vs Temperature TEMPERATURE (°C) –60 –0.5 GAIN ERROR (%) OFFSET VOLTAGE (mV) –0.4 –0.2 –0.1 0.5 0.2 –40 –20 0 140
1966 G08
–0.3 0.3 0.4 0.1 –0.5 –0.4 –0.2 –0.1 0.5 0.2 –0.3 0.3 0.4 0.1 4020 60 80 100 120 VDD = 5V VSS = GND VIOS VOOS GAIN ERROR Gain and Offsets vs Temperature TEMPERATURE (°C) –60 –0.5 GAIN ERROR (%) OFFSET VOLTAGE (mV) –0.4 –0.2 –0.1 0.5 0.2 –40 –20 0 140
1966 G09
–0.3 0.3 0.4 0.1 –0.5 –0.4 –0.2 –0.1 0.5 0.2 –0.3 0.3 0.4 0.1 40 6020 80 100 120 VDD = 5V VSS = –5V VIOS VOOSGAIN ERROR Gain and Offsets vs Temperature TEMPERATURE (°C) –60 –0.5 GAIN ERROR (%) OFFSET VOLTAGE (mV) –0.4 –0.2 –0.1 0.5 0.2 –40 –20 0 140
1966 G07
–0.3 0.3 0.4 0.1 –1.0 –0.8 –0.4 –0.2 1.0 0.4 –0.6 0.6 0.8 0.2 4020 60 80 100 120 VDD = 2.7V VSS = GND VIOS VOOS GAIN ERROR
Typical perForMance characTerisTics Gain and Offsets vs VSS Supply VSS (V) –0.5 GAIN ERROR (%) OFFSET VOLTAGE (mV) –0.4 –0.2 –0.1 0.5 0.2 –5 –4 0
1966 G11
–0.3 0.3 0.4 0.1 –0.5 – 0.4 – 0.2 – 0.1 0.5 0.2 – 0.3 0.3 0.4 0.1 –2–3 –1 VDD = 5V VIOSVOOSGAIN ERROR NOMINAL SPECIFIED CONDITIONS VDD (V) 2.5 –0.5 GAIN ERROR (%) OFFSET VOLTAGE (mV) –0.4 –0.2 –0.1 0.5 0.2 3.0 3.5 5.5
1966 G10
–0.3 0.3 0.4 0.1 –1.0 – 0.8 – 0.4 – 0.2 0.4 – 0.6 0.6 0.8 0.2 4.54.0 5.0 VSS = GND VIOS VOOS GAIN ERROR AC Linearity Performance vs Crest FactorGain and Offsets vs VDD Supply VIN1 (VRMS) –20 VOUT (mV DC) – VIN (mVRMS) –15 –10 0.5 1 1.5 2
1966 G24
2.5 1% ERROR AC INPUTS = 60Hz SINEWAVES V IN2 = GND –1% ERROR AC INPUT VDD = 3V AC INPUT V DD = 5V DC INPUT VDD = 5V Output Accuracy vs Signal Amplitude CREST FACTOR 1.0
199.8 OUTPUT VOLTAGE (mV DC)
200.0 200.2 200.4 200.6 2.0 3.0 4.0 5.0
1966 G15
200.8 201.0 1.5 2.5 3.5 4.5 20Hz 60Hz 100Hz 200mVRMS SCR WAVEFORMS CAVE = 10µF VDD = 5V O.1%/DIV Performance vs Large Crest Factors CREST FACTOR OUTPUT VOLTAGE (mV DC) 220
1966 G12
CAVE = 4.7µF VDD = 5V 5%/DIV 20Hz 100Hz 60Hz 250Hz FUNDAMENTAL FREQUENCY DC Linearity VIN1 (mV) –500 VOUTDC – |VINDC| (mV)0.02 0.06 0.10 300
1966 G14
–0.02 –0.06 0.04 0.08 –0.04 –0.08 –0.10 –300 –100 100 500 EFFECT OF OFFSETS MAY BE POSITIVE OR NEGATIVE CAVE = 1µF VIN2 = GND Quiescent Supply Currents vs Supply Voltage VDD SUPPLY VOLTAGE (V) –25 SUPPLY CURRENT (µA) 100 200
1966 G16
VSS = GND IDD ISS Shutdown Currents vs ENABLE Voltage ENABLE PIN VOLTAGE (V) 250 200 IDD IEN 150 100 –50 –100 500 250 –250 –500 3 5
1966 G18
SUPPLY CURRENT (µA) ENABLE PIN CURRENT (nA) VDD = 5V ISS VIN1 (mV ACRMS) VOUT (mV DC) – VIN (mV ACRMS) 0.20 0.15 0.10 0.05 –0.05 –0.10 –0.15 –0.20 400
1966 G13
100 200 300 50035050 150 250 450 60Hz SINEWAVES CAVE = 1µF VIN2 = GND
Typical perForMance characTerisTics Input Signal Bandwidth INPUT SIGNAL FREQUENCY (Hz) 100 1K OUTPUT DC VOLTAGE (mV) 1000 10K 100K 1M
1966 G19
0.1% ERROR ERROR 10% ERROR –3dB VIN1 (mV DC) –20 VOUT (mV DC)10
1966 G22
–10 –10 0 10–15 –5 5 15 VIN2 = GND THREE REPRESENTITIVE UNITS DC T ransfer Function Near Zero Quiescent Supply Currents vs Temperature Input Signal Bandwidth INPUT FREQUENCY (kHz) 190OUTPUT DC VOLTAGE (mV) 192 194 196 198 10 100 1000
1966 G20
1%/DIV CAVE = 2.2µF Bandwidth to 100kHz INPUT FREQUENCY (kHz)
195 OUTPUT DC VOLTAGE (mV)
1966 G21
0.5%/DIV C AVE = 47µF Common Mode Rejection Ratio vs Frequency FREQUENCY (Hz) COMMON MODE REJECTION RATIO (dB) 100 110 10 1k 10k 1M
1966 G23
VDD = 5V VSS = –5V ±5V INPUT CONVERSION TO DC OUTPUT TEMPERATURE (°C) – 60 IDD (µA) ISS (µA) 160 0 20
1966 G17
–40 –20 60 40 170 150 140 80 100 120 140 VDD = 5V, VSS = –5V VDD = 5V, VSS = –5V VDD = 5V, VSS = GND VDD = 5V, VSS = GND VDD = 2.7V, VSS = GND VDD = 2.7V, VSS = GND
GND (Pin 1): Ground. A power return pin. IN1 (Pin 2): Differential Input. DC coupled (polarity is irrelevant). IN2 (Pin 3): Differential Input. DC coupled (polarity is irrelevant). VSS (Pin 4): Negative Voltage Supply. GND to – 5.5V . VOUT (Pin 5): Output Voltage. This is high impedance. The RMS averaging is accomplished with a single shunt capacitor from this node to OUT RTN. The transfer func- tion is given by: V OUT RTN Average IN INOUT ––() = () 21 2 OUT RTN (Pin 6): Output Return. The output voltage is created relative to this pin. The V OUT and OUT RTN pins are not balanced and this pin should be tied to a low impedance, both AC and DC. Although it is typically tied to GND, it can be tied to any arbitrary voltage, V SS < OUT RTN < (VDD – Max Output). Best results are obtained when OUT RTN = GND. VDD (Pin 7): Positive Voltage Supply. 2.7V to 5.5V . ENABLE (Pin 8): An Active Low Enable Input. L TC1966 is debiased if open circuited or driven to VDD. For normal operation, pull to GND, a logic low or even VSS.
1966 TA02
CONVERSION? READ RMS-TO-DC CONVERSION NO NO YES YES YES NO NO YES YES YES DO YOU HAVE ANY LTC1966s YET? DID YOU ALREADY TRY OUT THE LTC1966? DID YOUR CIRCUIT WORK? NOW DOES YOUR RMS CIRCUIT WORK WELL ENOUGH THAT YOU ARE READY TO BUY THE LTC1966? DO YOU WANT TO KNOW HOW TO USE THE LTC1966 FIRST? CONTACT LTC BY PHONE OR AT www.linear.com AND GET SOME NOW READ THE TROUBLESHOOTING GUIDE. IF NECESSARY, CALL LTC FOR APPLICATIONS SUPPORT CONTACT LTC AND PLACE YOUR ORDER READ THE DESIGN COOKBOOK READ THE TROUBLESHOOTING GUIDE AGAIN OR CALL LTC FOR APPLICATIONS SUPPORT FIND SOMEONE WHO DOES AND GIVE THEM THIS DATA SHEET
conversion with real SCR waveforms as well. is only with a nonsinusoidal waveform that errors occur . will generate the same heat in a resistive load as will 1V DC. Table 1. Errors with Average Rectification vs T rue RMS
1966 F01
1966 F02a
1966 F02b
putation to calculate the RMS value of an input signal. Figure 3. RMS-to-DC Converter with Implicit Computation Figure 4. Topology of LTC1966 which, as shown above, results in RMS-to-DC conversion.
1966 F03
processes: squaring and square rooting. a whole range of input values together . necessarily present for at most 6.25% (1/16) of the time. ity throughout the L TC1966. mon with traditional log/antilog RMS-to-DC converters. introduced by rectification. Calibration section following the Design Cookbook. Figure 5. Linearity Model of an RMS-to-DC Converter
- VIOS
- INPUT NONLINEARITY IDEAL RMS-TO-DC CONVERTER OUTPUT CIRCUITRY
- V OOS
- OUTPUT NONLINEARITY INPUT OUTPUT
1966 F05
- It is appropriate for most applications, in which
Figure 6. DC Error vs Input Frequency Figure 7. Output Ripple Exceeds DC Error Figure 7. The ripple is at twice the frequency of the input because of the computation of the square of the input. AVE = 1µF and fINPUT = 10Hz. simplest solution is to use a larger averaging capacitor .
1966 F06
1966 F07
A 1µF capacitor is a good choice for many applications. will be <0.1% with frequencies of 10Hz or more. AVE will generally be required. See Crest Factor and AC + DC Waveforms. The L TC1966 can operate with many types of capacitors. parasitics, package styles and costs. to assure the low frequency accuracy desired. again dependent on voltage and particularly temperature. value of capacitance and at high temperature. tor can be an issue with the switched capacitor L TC1966. dielectric such as X7R or NPO/COG. input is left floating, a zero volt output will result. Figure 8. Peak Error vs Input Frequency with One Cap Averaging
1966 F08
the second L TC1966 input can be connected to that point. can be created with two resistors as shown in Figure 9b. to follow the DC average of the input voltage. the two inputs can be connected through a series capacitor . ceramic chip capacitor will usually suffice. to ground (Pin 1), and this will result in the best accuracy. AC and DC, for proper operation of the L TC1966. Figure 9. Single-Ended AC-Coupled Input Connection Alternatives
1966 F09
with respect to OUT RTN (Pin 6). can, of course, be inexpensive ceramic types. the device by grounding Pin 8, or driving it with a logic low. (such as a dual slope integrating ADC) should be used. top DMM with the ability to disconnect the 10MΩ shunt. ahead a few pages and review the T roubleshooting Guide. log/antilog circuit output does. Figure 10. VSS Limits vs VDD
1966 F10
rise and fall characteristics will converge to as the input frequency is increased. is a necessary consequence of RMS-to-DC calculation. that of the rising edge and falling edge cases of Figure 11. it goes to zero, and it can be used as a design guide. gives an acceptable settling time, your design is done. Figure 12. LTC1966 Settling Time with One Cap Averaging
1966 F12
1966 F11a
1966 F11b
seconds is just 5.7 cycles of this extremely low frequency. Averaging very low frequency signals takes a long time. simply increasing the averaging capacitor . errors for four of Linear Technology’s op amps. output stages (and even some input stages) will not. for the circuitry that follows. a net 3rd order filtering of the L TC1966 RMS calculation. for the filter , thus the (relatively) low noise requirement. Figure 14. DC Accurate Post FilterFigure 13. Buffered Post Filter
1966 F13
1066 F14
case, and both have the same relative (Bessel-like) shape. by a common multiple, and leave the resistors unchanged. edge makes for a better intuitive comparison. accuracy improves due to the initial speedup. double frequency output ripple is just 180µV . 3:1 or 216:1 for a 6:1 change in frequency. tion of capacitors for the two different filter topologies. Figure 16. Step Responses with 60Hz BurstFigure 15. Step Responses with 10Hz Burst
1966 F15
1966 F16
is simple because the capacitors are in a 10:1:10 ratio. Table 2. One Decade of Capacitor Scaling for Figure 14 with EIA in overall bandwidth as mentioned earlier . output impedance can be enough to cause some ringing. capacitors and ±1% resistors are used. Figure 18. Peak Error vs Input Frequency with DC Accurate Post Filter Figure 17. Peak Error vs Input Frequency with Buffered Post Filter
1966 F17
1966 F18
presented in Figures 6, 8, 17 and 18. averaging has to ride out the long lull in signal activity.
- –32
Figure 20. Settling Time with DC Accurate Post Filter Figure 19. Settling Time with Buffered Post Filter
1066 F20
using the same design curves presented in Figures 6, 8, 17 and 18. For the worst-case of square top pulse trains, that are always either zero volts or the peak voltage, base the selection on the lowest fundamental input frequency divided by twice as much: f f CF DESIGN INPUT MIN= ()
- –62 The effects of crest factor and DC offsets are cumulative. So for example, a 10% duty cycle pulse train from 0V PEAK to 1VPEAK (CF = √10 = 3.16) repeating at 16.67ms (60Hz) input is effectively only 30Hz due to the DC asymmetry and is effectively only: fH zDESIGN == 30 63 16 2 37 8
- . – for the purposes of Figures 6, 8, 17 and 18. Obviously, the effect of crest factor is somewhat simplified above given the factor of 2 difference based on a subjec- tive description of the waveform type. The results will vary somewhat based on actual crest factor and waveform dynamics and the type of filtering used. The above method is conservative for some cases and about right for others. The L TC1966 works well with signals whose crest factor is 4 or less. At higher crest factors, the internal ∆∑ modulator will saturate, and results will vary depending on the exact frequency, shape and (to a lesser extent) amplitude of the input waveform. The output voltage could be higher or lower than the actual RMS of the input signal. The ∆∑ modulator may also saturate when signals with crest factors less than 4 are used with insufficient averaging. This will only occur when the output droops to less than 1/4 of the input voltage peak. For instance, a DC-coupled pulse train with a crest factor of 4 has a duty cycle of 6.25% and a 1V PEAK input is 250mVRMS. If this input is 50Hz, repeating every 20ms, and C AVE = 1µF , the output will droop during the inactive 93.75% of the waveform. This droop is calculated as: V V eMIN RMS INACTIVE TIME 2 1– 2 • Z• COUT AVE For the L TC1966, whose output impedance (ZOUT) is 85kΩ, this droop works out to – 5.22%, so the output would be reduced to 237mV at the end of the inactive portion of the input. When the input signal again climbs to 1V PEAK, the peak/output ratio is 4.22. With CAVE = 10µF , the droop is only –0.548% to 248.6mV and the peak/output ratio is just 4.022, which the L TC1966 has enough margin to handle without error . For crest factors less than 3.5, the selection of C AVE as previously described should be sufficient to avoid this droop and modulator saturation effect. But with crest factors above 3.5, the droop should also be checked for each design. Error Analyses Once the RMS-to-DC conversion circuit is working, it is time to take a step back and do an analysis of the accuracy of that conversion. The L TC1966 specifications include three basic static error terms, V OOS, VIOS and GAIN. The output offset is an error that simply adds to (or subtracts from) the voltage at the output. The conversion gain of the L TC1966 is nominally 1.000 V DCOUT/VRMSIN and the gain error reflects the extent to which this conversion gain is not perfectly unity. Both of these affect the results in a fairly obvious way. Input offset on the other hand, despite its conceptual simplicity, effects the output in a nonobvious way. As its name implies, it is a constant error voltage that adds directly with the input. And it is the sum of the input and V IOS that is RMS converted. This means that the effect of V IOS is warped by the nonlinear RMS conversion. With 0.2mV (typ) VIOS, and a 200mVRMS AC input, the RMS calculation will add the DC and AC terms in an RMS fashion and the effect is negligible: VOUT = √(200mV AC)2 + (0.2mV DC)2 = 200.0001mV = 200mV + 1/2ppm
But with 10× less AC input, the error caused by V IOS is 100× larger: VOUT = √(20mV AC)2 + (0.2mV DC)2 = 20.001mV = 20mV + 50ppm This phenomena, although small, is one source of the L TC1966’s residual nonlinearity. On the other hand, if the input is DC-coupled, the input offset voltage adds directly. With +200mV and a +0.2mV V IOS, a 200.2mV output will result, an error of 0.1% or 1000ppm. With DC inputs, the error caused by V IOS can be positive or negative depending if the two have the same or opposing polarity. The total conversion error with a sine wave input using the typical values of the L TC1966 static errors is computed as follows: V OUT = (√(500mV AC)2 + (0.2mV DC)2) • 1.001 + 0.1mV = 500.600mV = 500mV + 0.120% VOUT = (√(50mV AC)2 + (0.2mV DC)2) • 1.001 + 0.1mV = 50.150mV = 50mV + 0.301% VOUT = (√(5mV AC)2 + (0.2mV DC)2) • 1.001 + 0.1mV = 5.109mV = 5mV + 2.18% As can be seen, the gain term dominates with large inputs, while the offset terms become significant with smaller inputs. In fact, 5mV is the minimum RMS level needed to keep the L TC1966 calculation core functioning normally, so this represents the worst-case of usable input levels. Using the worst-case values of the L TC1966 static errors, the total conversion error is: VOUT = (√(500mV AC)2 + (0.8mV DC)2) • 1.003 + 0.2mV = 501.70mV = 500mV + 0.340% VOUT = (√(50mV AC)2 + (0.8mV DC)2) • 1.003 + 0.2mV = 50.356mV = 50mV + 0.713% VOUT = (√(5mV AC)2 + (0.8mV DC)2) • 1.003 + 0.2mV = 5.279mV = 5mV + 5.57% These static error terms are in addition to dynamic error terms that depend on the input signal. See the Design Cookbook for a discussion of the DC conversion error with low frequency AC inputs. The L TC1966 bandwidth limitations cause additional errors with high frequency inputs. Another dynamic error is due to crest factor . The L TC1966 performance versus crest factor is shown in the Typical Performance Characteristics. Monotonicity and Linearity The L TC1966, like all implicit RMS-to-DC convertors (Figure 3), has a division with the output in the denominator . This works fine most of the time, but when the output is zero or near zero this becomes problematic. The L TC1966 has multiple switched capacitor amplifier stages, and depending on the different offsets and their polarity, the DC transfer curve near zero input can take a few different forms, as shown in the Typical Performance Characteristics graph titled DC T ransfer Function Near Zero. Some units (about 1 of every 16) will even be well behaved with a transfer function that is the upper half of a unit rectangular hyperbola with a focal point on the y-axis of a few millivolts.
3 For AC inputs, these units will have a
monotonic transfer function all the way down to zero input. The L TC1966 is trimmed for offsets as small as practical, and the resulting behavior is the best statistical linearity provided the zero region troubles are avoided. It is possible, and even easy, to force the zero region to be well behaved at the price of additional (though predict- able) V OOS and some linearity error . For large enough input signals, this linearity error may be negligible. 3In general, every L TC1966 will have a DC transfer function that is essentially a unit rectangular hyperbola (the gain is not always exactly unity, but the gain error is small) with an X- and Y- offset equal to VIOS and VOOS, respectively, until the inputs are small enough that the delta sigma section gets confused. While some units will be the north half of a north south pair , other units will have two upper halfs of the conjugate, east west, hyperbolas. The circuit of Figure 23 will assure a continuous transfer function.
as is the nominal 2.5mV offset, by the L T1494 op amp. either digitally, or by an analog means. Figure 21. Behavioral Block Diagram of LTC1966 Figure 23. Monotonic AC Response with Offset
1966 F23
1966 F21
1966 F22a
1966 F22b
The two 10MΩ resistors not connected to the supply can be any value as long as they match and the feed voltage is changed for 30nA injection. The op amp gain is only 1.00845, so the output is dominated by the L TC1966 RMS results, which keeps errors low. With the values shown, the resistors can be ±2% and only introduce ±170ppm of gain error . The 84.5k resistor is the closest match in the 1% EIA values but if the 2% EIA value of 82k were used instead, the gain would only be reduced by 248ppm. This low error sensitivity is important because the L TC1966 output impedance is 85kΩ ±11.8%, which can create a gain error of ±0.1%; enough to degrade the overall gain accuracy somewhat. This gain variation term is increased with lower value feed resistors, and decreased with higher value feed resistors. A bigger error caused by the variation of the L TC1966 output impedance is imperfect cancelation of the output offset introduced by the injected current. The offset correc- tion provided by the L T1494 will be based on a consistent 84.5kΩ times the injected current, while the L TC1966 output impedance will vary enough that the output offset will have a ±300µV range about the nominal 2.5mV . If this level of output offset is not acceptable, either system calibration or a potentiometer in the L T1494 feedback may be needed. If the two 10MΩ feed resistors to the L T1494 have signifi- cant mismatch, cancellation of the 2.5mV offset would be further impacted, so it is probably worth paying an extra penny or so for 1% resistors or even the better temperature stability of thin film devices. The 300mV feed voltage is not particularly critical because it is nominally cancelled, but the offset errors due to these resistance mismatches is scaled by that voltage. Note that the input bias current of the op amp used in Figure 23 is also nominally cancelled, but it will add or subtract to the total current injected into the L TC1966 output. With the 1nA I BIAS of the L T1494 this is negligible. While it is possible to eliminate the feed resistors by using an op amp with a PNP input stage whose I BIAS is 30nA or more, IBIAS is usually only specified for maximum and this circuit needs a minimum of 30nA, therefore such an approach may not always work. Because the circuit of Figure 23 subtracts the offset cre- ated by the injected current, the L T1494 output with zero L TC1966 input will rest at +2.5mV , nominal before offsets, rather then the 5mV seen in Figure 22. Output Errors Versus Frequency As mentioned in the Design Cookbook, the L TC1966 per- forms very well with low frequency and very low frequency inputs, provided a large enough averaging capacitor is used. However , the L TC1966 will have additional dynamic errors as the input frequency is increased. The L TC1966 is designed for high accuracy RMS-to-DC conversion of signals into the audible range. The input sampling amplifiers have a – 3dB frequency of 800kHz or so. However , the switched capacitor circuitry samples the inputs at a modest 100kHz nominal. The response versus frequency is depicted in the Typical Performance Characteristics titled Input Signal Bandwidth. Although there is a pattern to the response versus frequency that repeats every sample frequency, the errors are not overwhelming. This is because L TC1966 RMS calculation is inherently wideband, operating properly with minimal oversampling, or even undersampling, using sev- eral proprietary techniques to exploit the fact that the RMS value of an aliased signal is the same as the RMS value of the original signal. However , a fundamental feature of the S modulator is that sample estimation noise is shaped such that minimal noise occurs with input frequencies much less than the sampling frequency , but such noise peaks when input frequency reaches half the sampling frequency. Fortunately the L TC1966 output averaging filter greatly reduces this error , but the RMS-to-DC topology frequency shifts the noise to low (baseband) frequencies. So with input frequencies above 5kHz to 10kHz, the output will slowly wander around ±a few percent.
frequency. This accounts for the 8MΩ input impedance. edge as the sample capacitor is connected to be charged. that are used to compute the RMS value. Figure 24. LTC1966 Equivalent Analog Input Circuit spikes over several clock cycles. driven by a low impedance. Keep time constant < < 2.5µs. a high value series resistor to any test point is advisable. in half to the nominal 85kΩ specified.
1966 F24
than the specified limit of the L TC1966 itself. Figure 23. The summing node of the L T1494 has the same to the same nominal voltage.
1966 F24a
1966 F24b
The L TC1966 output impedance and the RMS averaging ripple need to be considered when using an analog-to- digital converter (ADC) to digitize the L TC1966 RMS result. The simplest configuration is to connect the L TC1966 directly to the input of a type 7106/7136 ADC as shown in Figure 25a. These devices are designed specifically for DVM/DPM use and include display drivers for a 3 1/2 digit LCD segmented display. Using a dual slope conversion, the input is sampled over a long integration window, which results in rejection of line frequency ripple when integration time is an integer number of line cycles. Finally, these parts have an input impedance in the GΩ range, with specified input leakage of 10pA to 20pA. Such a leakage, combined with the L TC1966 output impedance, results in just 1µV to 2µV of additional output offset voltage. for are the input impedance, and any input sampling cur- rents. The input sampling currents drawn by ∆∑ ADCs often have large spikes of current with short durations that can confuse some op amps, but with the large C AVE needed by the L TC1966 these are not an issue. The average current is important, as it can create L TC1966 errors; if it is constant it will create an offset, while aver- age currents that change with the voltage level create gain errors. Some converters run continuously, others only sample upon demand, and this will change the results in ways that need to be understood. The L TC1966 output impedance has a loose tolerance relative to the usual re- sistors and the same can be true for the input impedance of ∆∑ ADC, resulting in gain errors from part-to-part. The system calibration techniques described in the following section should be used in applications that demand tight tolerances. One example of driving an oversampling ∆∑ ADC is shown in Figure 25b. In this circuit, the L TC2420 is used with a 1V V REF. Since the L TC1966 output voltage range is about 1V , and the L TC2420 has a ±12.5% extended input range, this configuration matches the two ranges with room to spare. The L TC2420 has an input impedance of 16.6MΩ, resulting in a gain error of –0.4% to –0.6%. In fact, the L TC2420 DC input current is not zero at 0V , but rather at one half its reference, so both an output offset and a gain error will result. These errors will vary from part to part, but with a specific L TC1966 and L TC2420 combination, the errors will be fixed, varying less than ±0.05% over temperature. So a system that has digital calibration can be quite accurate despite the nominal gain and offset error . With 20 bits of resolution, this part is more accurate than the L TC1966, but the extra resolution is helpful because it reduces nonlinearity at the LSB transitions as a digital gain correction is made. Furthermore, its small size and ease of use make it attractive. Figure 25a. Interfacing to DVM/DPM ADC Figure 25b. Interfacing to LTC2420 Another type of ADC that has inherent rejection of RMS averaging ripple is an oversampling ∆∑. With most, but not all, of these devices, it is possible to connect the L TC1966 output directly to the converter input. Issues to look out CAVE LTC1966 OUTPUT OUT RTN
7106 TYPE
1966 F25a
1966 F25b
As is shown in Figure 25b, where the L TC2420 is set to continuously convert by grounding the CS pin. The gain error will be less if CS is driven at a slower rate, however , the rate should either be consistent or at a rate low enough that the L TC1966 and its output capacitor have fully settled by the beginning of each conversion, so that the loading errors are consistent. Note that in this circuit, the input current of the L TC2420 is being used to assure monotonicity. The L TC2420 Z IN of 16.6MΩ is effectively connected to half the reference volt- age, so when the L TC1966 has zero signal, 500mV/16.6MΩ = 30nA is provided. Alternatively, a 5V V REF can be used, but in this case the L TC1966 output span will only use 20% of the L TC2420’s input voltage range. Furthermore, if the OUTRTN remains grounded, the injected current with zero signal will be 150nA, resulting in 5× the offset error and nonlinearity shown in Figure 22. In both of the circuits of Figure 25, a guard ring only has to encircle three terminals, the L TC1966 output, the top of the averaging capacitor , and the ADC input. Figure 26 shows the top copper patterns for example PCB layouts of each. The low power consumption of the L TC1966 makes it well suited for battery powered applications, and its slow output (DC) makes it an ideal candidate for a micropower ADC. applicaTions inForMaTion Figure 26b. PCB Layout of Figure 25b with Guard Ring Figure 26a. PCB Layout of Figure 25a with Guard Ring Figure 10 in Application Note 75, for instance, details a 10-bit ADC with a 35ms conversion time that uses just 29µA of supply current. Such an ADC may also be of use within a 4mA to 20mA loop. Other types of ADCs sample the input signal once and perform a conversion on that one sample. With these ADCs (Nyquist ADCs), a post filter will be needed in most cases to reduce the peak error with low input frequencies. The DC accurate filter of Figure 14 is attractive from an error standpoint, but it increases the impedance at the ADC input. In most cases, the buffered post filter of Figure 13 will be more appropriate for use with Nyquist analog-to- digital converters. S YSTEM CALIBRA TION The L TC1966 static accuracy can be improved with end system calibration. T raditionally, calibration has been done at the factory, or at a service depot only, typically using manually adjusted potentiometers. Increasingly, systems are being designed for electronic calibration where the accuracy corrections are implemented in digital code wherever possible, and with calibration DACs where necessary. Additionally, many systems are now designed for self calibration, in which the calibration occurs inside the machine, automatically without user intervention. LTC1966 MS8
1966 F26b
1µf CAVE
1966 F26a
1µf CAVE LTC1966 MS8 ICL7106 MQFP
Whatever calibration scheme is used, the linearity of the L TC1966 will improve the calibrated accuracy over that achievable with older log/antilog RMS-to-DC converters. Additionally, calibration using DC reference voltages are essentially as accurate with the L TC1966 as those using AC reference voltages. Older log/antilog RMS-to-DC converters required nonlinear input stages (rectifiers) whose linearity would typically render DC based calibra- tion unworkable. The following are four suggested calibration methods. Implementations of the suggested adjustments are de- pendent on the system design, but in many cases, gain and output offset can be corrected in the digital domain, and will include the effect of all gains and offsets from the L TC1966 output through the ADC. Input offset voltage, on the other hand, will have to be corrected with adjustment to the actual analog input to the L TC1966. The methods below assume the unaltered linearity of the L TC1966, i.e. without the monotonicity fix of Figure 21. If this is present, the V OOS shift it introduces should be taken out before using either method for which V OOS is not calibrated. Also, the nonlinearity it introduces will increase the 20mV readings discussed below by 0.78% but increase the 200mV readings only 78ppm. There are a variety of ways to deal with these errors, including possibly ignoring them, but the specifics will depend on system requirements. Designers are cautioned to avoid the temptation to digitally take out the hyperbolic transfer function introduced because if the offsets are not exactly the nominals assumed, the system will end up right back where it began with a potential discontinuity with zero input, either from a divide by zero or from a square root of a negative number in the calculations to undo the hy- perobic transfer function. An adaptive algorithm would most likely be necessary to safely take out more than half of the introduced nonlinearity. If a 5V reference is used in the connection of Figure 25b, the V OOS and nonlinearity created would be even larger , and will no doubt be more tempting to correct for . Design- ers are likewise cautioned against correcting for all of the nonlinearity. AC-Only, 1 Point The dominant error at full-scale will be caused by the gain error , and by applying a full-scale sine wave input, this error can be measured and corrected for . Unlike older log/antilog RMS-to-DC converters, the correction should be made for zero error at full scale to minimize errors through out the dynamic range. The best frequency for the calibration signal is roughly ten times the – 0.1% DC error frequency. For 1µF , –0.1% DC error occurs at 8Hz, so 80Hz is a good calibration frequency, although anywhere from 60Hz to 100Hz should suffice. The trade-off here is that on the one hand, the DC error is input frequency dependent, so a calibration signal frequency high enough to make the DC error negligible should be used. On the other hand, as low a frequency as can be used is best to avoid attenuation of the calibrated AC signal, either from parasitic RC loading or insufficient op amp gain. For instance, with a 1kHz calibration signal, a 1MHz op amp will typically only have 60dB of open loop gain, so it could attenuate the calibration signal a full 0.1%. AC-Only, 2 Point The next most significant error for AC-coupled applications will be the effect of output offset voltage, noticeable at the bottom end of the input scale. This too can be calibrated out if two measurements are made, one with a full-scale sine wave input and a second with a sine wave input (of the same frequency) at 10% of full-scale. The trade-off in selecting this second level is that it should be small enough that the gain error effect becomes small compared to the gain error effect at full-scale, while on the other hand, not using so small an input that the input offset voltage becomes an issue. applicaTions inForMaTion
The calculations of the error terms for a 200mV full-scale case are: Gain = Reading at 200mV – Reading at 20mV 180mV Output Offset = Reading at 20mV Gain –2 0mV DC, 2 Point DC based calibration is preferable in many cases because a DC voltage of known, good accuracy is easier to generate than such an AC calibration voltage. The only down side is that the L TC1966 input offset voltage plays a role. It is therefore suggested that a DC based calibration scheme check at least two points: ±full-scale. Applying the –full- scale input can be done by physically inverting the voltage or by applying the same +full-scale input to the opposite L TC1966 input. For an otherwise AC-coupled application, only the gain term may be worth correcting for , but for DC-coupled ap- plications, the input offset voltage can also be calculated and corrected for . The calculations of the error terms for a 200mV full-scale case are: Gain = Reading at 200mV + Reading at – 200mV 400mV Input Offset = Reading at – 200mV – Reading at 200mV 2•Gain applicaTions inForMaTion Note: Calculation of and correction for input offset voltage are the only way in which the two L TC1966 inputs (IN1, IN2) are distinguishable from each other . The calculation above assumes the standard definition of offset; that a positive offset is the case of a positive voltage error inside the device that must be corrected by applying a like nega- tive voltage outside. The offset is referred to whichever pin is driven positive for the +full-scale reading. DC, 3 Point One more point is needed with a DC calibration scheme to determine output offset voltage: +10% of full scale. The calculation of the input offset is the same as for the -point calibration above, while the gain and output offset are calculated for a 200mV full-scale case as: Gain = Reading at 200mV – Reading at 20mV 180mV Output Offset = Reading at 200mV +Reading at – 200mV – 400mV•Gain
en L TC1966 Application Mistakes 1. Circuit won’t work–Dead On Arrival–no power drawn. – Probably forgot to enable the L TC1966 by pulling Pin 8 low. Solution: Tie Pin 8 to Pin 1. . Circuit won’t work, but draws power . Zero or very little output, single-ended input application. – Probably didn’t connect both input pins. Solution: Tie both inputs to something. See Input Connections in the Design Cookbook. applicaTions inForMaTion 4. Gain is low by a few percent, along with other screwy results. – Probably tried to use output in a floating, differential manner Solution: Tie Pin 6 to a low impedance. See Output Connections in the Design Cookbook. TYPE 7136 ADC LTC1966 HI31 6 LO V OUT OUT RTN
1966 TS04
1966 TS02
- Screwy results, particularly with respect to linearity or high crest factors; differential input application. Probably AC-coupled both input pins. Solution: Make at least one input DC-coupled. See Input Connections in the Design Cookbook. LTC1966 IN12
3 IN2
1966 TS03
- Offsets perceived to be out of specification because 0V in ≠ 0V out. – The offsets are not specified at 0V in. No RMS-to-DC converter works well at 0 due to a divide-by-zero calculation. Solution: Measure VIOS/VOOS by extrapolating readings > ±5mVDC. 6. Linearity perceived to be out of specification particularly with small input signals. – This could again be due to using 0V in as one of the measurement points. Solution: Check Linearity from 5mVRMS to 500mVRMS. – The input offset voltage can cause small AC linearity errors at low input amplitudes as well. See Error Analyses section. Possible Solution: Include a trim for input offset.
- Output is noisy with >10kHz inputs. – This is a fundamental characteristic of this topol- ogy . The L TC1966 is designed to work very well with inputs of 1kHz or less. It works okay as high as 1MHz, but it is limited by aliased ∆ S noise. Solution: Bandwidth limit the input or digitally filter the resulting output. Large errors occur at crest factors approaching, but less than 4. – Insufficient averaging. Solution: Increase CAVE. See Crest Factor and AC + DC Waveforms section for discussion of output droop. 9. Screwy results, errors > spec limits, typically 1% to 5%. – High impedance (85kΩ) and high accuracy (0.1%) require clean boards! Flux residue, finger grime, etc. all wreak havoc at this level. Solution: Wash the board. Helpful Hint: Sensitivity to leakages can be reduced significantly through the use of guard traces. LTC1966 KEEP BOARD CLEAN 10. Gain is low by ≅ 1% or more, no other problems. – Probably due to circuit loading. With a DMM or a 10× scope probe, Z IN = 10MΩ. The L TC1966 output is 85kΩ, resulting in – 0.85% gain error . Output impedance is higher with the DC accurate post filter . Solution: Remove the shunt loading or buffer the output. Loading can also be caused by cheap averaging capacitors. Solution: Use a high quality metal film capacitor for C AVE. 200mVRMS IN –0.85% DMM DCV LTC1966 10M 85k VOUT OUT RTN
1966 TS10
±5V Supplies, Differential, DC-Coupled RMS-to-DC Converter VDD –5V LTC1966 IN1 DC OUTPUT CAVE 1µFIN2
1966 TA03
(1VPEAK DIFFERENTIAL) OUT RTN GND ENVSS 5V Single Supply, Differential, AC-Coupled RMS-to-DC Converter VDD LTC1966 IN1 DC OUTPUT CAVE 1µF CC 0.1µF IN2
1966 TA05
(1VPEAK DIFFERENTIAL) OUT RTN GND ENVSS 2.7V Single Supply, Single Ended, AC-Coupled RMS-to-DC Converter with Shutdown VDD 2.7V 2.7V/3V CMOS LTC1966 IN1 DC OUTPUT CAVE 1µF CC 0.1µF IN2
1966 TA04
(1VPEAK) OUT RTN GND EN VSS OFF ON ±2.5V Supplies, Single Ended, DC-Coupled RMS-to-DC Converter with Shutdown VDD 2.5V –2.5V –2.5V –2.5V LTC1966 IN1 DC OUTPUT CAVE 1µF 0.1µF X7R IN2
1966 TA06
(1VPEAK) OUT RTN GND EN VSS OFF2V –2VON Battery Powered Single-Ended AC-Coupled RMS-to-DC Converter VDD AC INPUT (1VPEAK) LTC1966 IN1 DC OUTPUTCAVE 1µF CC 0.1µF 0.1µF X7R IN2
1966 TA07
2nd ORDER ∆∑ MODULATOR IN1 IN2 EN VDD OUTPUT OUT RTN 30k BLEED RESISTOR FOR C AVE CAVE 1966 SS TO BIAS CONTROL VSS GND Y1 Y2 C12 C11 CLOSED DURING SHUTDOWN C10 C5C3 A2A1
(Reference L TC DWG # 05-08-1660 Rev F) MSOP (MS8) 0307 REV F 0.53 ± 0.152 (.021 ± .006) SEATING PLANE NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 0.18 (.007) 0.254 (.010) 1.10 (.043) MAX 0.22 – 0.38 (.009 – .015) TYP 0.1016 ± 0.0508 (.004 ± .002) 0.86 (.034) REF 0.65 (.0256) BSC 0° – 6° TYP DETAIL “A” DETAIL “A” GAUGE PLANE 1 2 3 4 4.90 ± 0.152 (.193 ± .006) 8 7 6 5 3.00 ± 0.102 (.118 ± .004) (NOTE 3) 3.00 ± 0.102 (.118 ± .004) (NOTE 4) 0.52 (.0205) REF 5.23 (.206) MIN 3.20 – 3.45 (.126 – .136) 0.889 ± 0.127 (.035 ± .005) RECOMMENDED SOLDER PAD LAYOUT 0.42 ± 0.038 (.0165 ± .0015) TYP 0.65 (.0256) BSC
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However , no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
revision hisTory
REV DATE DESCRIPTION PAGE NUMBER B 5/11 Revised entire data sheet to add H- and MP- grades 1 to 38 (Revision history begins at Rev B)
Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear .com LINEAR TECHNOLOGY CORPORA TION 2001 LT 0511 REV B • PRINTED IN USA relaTeD parTs Typical applicaTion PART NUMBER DESCRIPTION COMMENTS LT®1077 Micropower , Single Supply Precision Op Amp 48µA ISY, 60µV VOS(MAX), 450pA IOS(MAX) L T1175-5 Negative, –5V Fixed, Micropower LDO Regulator 45µA I Q, Available in SO-8 or SOT-223 L T1494 1.5µA Max, Precision Rail-to-Rail I/O Op Amp 375µV VOS(MAX), 100pA IOS(MAX) L T1782 General Purpose SOT-23 Rail-to-Rail Op Amp 40µA ISY, 800µV VOS(MAX), 2nA IOS(MAX) L T1880 SOT-23 Rail-to-Rail Output Precision Op Amp 1.2mA ISY, 150µV VOS(MAX), 900pA IOS(MAX) L TC1967 Precision, Extended Bandwidth RMS to DC Converter 330µA I SY, ∆∑ RMS Conversion to 4MHz L TC1968 Precision, Wide Bandwidth RMS to DC Converter 2.3mA I SY, ∆∑ RMS Conversion to 15MHz L TC2050 Zero Drift Op Amp in SOT-23 750µA ISY, 3µV VOS(MAX), 75pA IB(MAX) L T2178/L T2178A 17µA Max, Single Supply Precision Dual Op Amp 14µA I SY, 120µV VOS(MAX), 350pA IOS(MAX) L TC2402 2-Channel, 24-bit, Micropower , No Latency ∆S™ ADC 200µA ISY, 4ppm INL, 10ppm TUE L TC2420 20-bit, Micropower , No Latency ∆S ADC in SO-8 200µA ISY, 8ppm INL, 16ppm TUE L TC2422 2-Channel, 20-bit, Micropower , No Latency ∆S ADC Dual Channel V ersion of L TC2420 RMS Noise Measurement 70A Current Measurement Single Supply RMS Current Measurement LTC1966 IN1 VOUT 4mVDC/ARMSCAVE 1µFIN2
1966 TA09
71.2A MAX 50Hz TO 400Hz OUT RTN GND ENVSS 10/uni03A9 T1: CR MAGNETICS CR8348-2500-N www.crmagnetics.com –5V LTC1966 IN1 VOUT = 4mVDC/ARMSCAVE 1µF 0.1µF IN2
1966 TA08
71.2A MAX 50Hz TO 400Hz OUT RTN GND ENVSS100k 100k 10/uni03A9 T1: CR MAGNETICS CR8348-2500-N www.crmagnetics.com VDD –5V –5V LTC1966 IN1 CAVE 1µF 0.1µF 1.5µF IN2
1966 TA10
1µVRMS NOISEVOUT = 10k 100/uni03A9 100/uni03A9100k BW 1kHz TO 100kHz INPUT SENSITIVITY = 1µV RMS TYP L TC6203