LT1712CGN

LT1711 LINER

Document overview

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Technical content

Single/Dual 4.5ns, 3V/5V/–5V, Rail-to-Rail Comparators The LT 1711/LT1712 are UltraFast TM 4.5ns comparators featuring rail-to-rail inputs, rail-to-rail complementary out- puts and an output latch. Optimized for 3V and 5V power supplies, they operate over a single supply voltage range from 2.4V to 12V or from –2.4V to –6V dual supplies. The LT1711/LT1712 are designed for ease of use in a variety of systems. In addition to wide supply voltage flexibility, rail-to-rail input common mode range extends 100mV beyond both supply rails, and the outputs are protected against phase reversal for inputs extending further beyond the rails. Also, the rail-to-rail inputs may be taken to opposite rails with no significant increase in input current. The rail-to-rail matched complementary outputs interface directly to TTL or CMOS logic and can sink 10mA to within 0.5V of GND or source 10mA to within 0.7V of V The LT1711/LT1712 have internal TTL/CMOS compatible latches for retaining data at the outputs. Each latch holds data as long as the latch pin is held high. Latch pin hysteresis provides protection against slow moving or noisy latch signals. The LT1711 is available in the 8-pin MSOP package. The LT1712 is available in the 16-pin narrow SSOP package. , LTC and LT are registered trademarks of Linear Technology Corporation. n High Speed Automatic Test Equipment n Current Sense for Switching Regulators n Crystal Oscillator Circuits n High Speed Sampling Circuits n High Speed A/D Converters n Pulse Width Modulators n Window Comparators n Extended Range V/F Converters n Fast Pulse Height/Width Discriminators n Line Receivers n High Speed Triggers UltraFast is a trademark of Linear Technology Corporation. LT1711/LT1712 Propagation Delay vs Input Overdrive n Ultrafast: 4.5ns at 20mV Overdrive 5.5ns at 5mV Overdrive n Rail-to-Rail Inputs n Rail-to-Rail Complementary Outputs (TTL/CMOS Compatible) n Specified at 2.7V, 5V and –5V Supplies n Output Latch n Inputs Can Exceed Supplies Without Phase Reversal n LT1711: 8-Lead MSOP Package n LT1712: 16-Lead Narrow SSOP Package

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200pF * 1% FILM RESISTOR ** NORTHERN ENGINEERING LABS C-2350N-14.31818MHz FREQUENCY OUTPUT 3.9k* VIN 0V TO 5V MV-209 VARACTOR DIODE 100pF 15pFY1** 100pF 0.047µF C SELECT (CHOOSE FOR CORRECT PLL LOOP RESPONSE) 1M 1M* 1N4148 LT1004-2.547k* 1k* A 4· NTSC Subcarrier Voltage-Tunable Crystal Oscillator INPUT OVERDRIVE (mV) PROPAGATION DELAY (ns) 3.5 4.0 4.5 tPD+ tPD– 30 50

171112 TA02

3.0 10 20 40 5.0 5.5 6.0 TA = 25°C V+ = 5V V– = 0V VSTEP = 100mV FEATURES DESCRIPTIO U APPLICATIO SU TYPICAL APPLICATIO U

ABSOLUTE AXI U RATI GSW WW U ORDER PART NUMBER LT1711CMS8 LT1711IMS8 Consult factory for parts specified with wider operating temperature ranges. TJMAX = 150°C, qJA = 250°C/ W (NOTE 12) PACKAGE/ORDER I FOR ATIOUU W MS8 PART MARKING LTTC LTTD V +IN –IN Q Q GND LATCH ENABLE TOP VIEW MS8 PACKAGE 8-LEAD PLASTIC MSOP (Note 1) Specified Temperature Range (Note 2) ... – 40°C to 85°C GN PACKAGE 16-LEAD PLASTIC SSOP TOP VIEW –IN A +IN A V +IN B –IN B GND Q A Q A Q B Q B GND LATCH ENABLE A LATCH ENABLE B TJMAX = 150°C, qJA = 120°C/ W (NOTE 12) ORDER PART NUMBER LT1712CGN LT1712IGN GN PART MARKING 1712 1712I

ELECTRICAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V+ Positive Supply Voltage Range l 2.4 7 V VOS Input Offset Voltage (Note 4) R S = 50W , VCM = V+/2 0.5 5.0 mV RS = 50W , VCM = V+/2 l 6.0 mV RS = 50W , VCM = 0V 0.7 mV RS = 50W , VCM = V+ 1m V DVOS/DT Input Offset Voltage Drift l 10 mV/°C IOS Input Offset Current 0.2 3 mA l 6 mA IB Input Bias Current (Note 5) – 18 –5 5 mA l –3 5 1 0 mA VCM Input Voltage Range (Note 9) l –0.1 V + + 0.1 V CMRR Common Mode Rejection Ratio V + = 5V, 0V £ VCM £ 5V 56 65 dB V + = 5V, 0V £ VCM £ 5V l 53 dB V + = 2.7V, 0V £ VCM £ 2.7V 54 65 dB V + = 2.7V, 0V £ VCM £ 2.7V l 50 dB PSRR+ Positive Power Supply Rejection Ratio 2.4V £ V+ £ 7V, VCM = 0V 58 75 dB l 56 dB The l denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. V+ = 2.7V or V+ = 5V, V– = 0V, VCM = V+/2, VLATCH = 0.8V, CLOAD = 10pF, VOVERDRIVE = 20mV, unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS PSRR– Negative Power Supply Rejection Ratio –7V £ V– £ 0V, V+ = 5V, VCM = 5V 60 80 dB l 58 dB AV Small-Signal Voltage Gain (Note 10) 1 15 V/mV VOH Output Voltage Swing HIGH I OUT = 1mA, VOVERDRIVE = 50mV l V+– 0.5 V +– 0.2 V IOUT = 10mA, VOVERDRIVE = 50mV l V+– 0.7 V +– 0.4 V VOL Output Voltage Swing LOW I OUT = –1mA, V OVERDRIVE = 50mV l 0.20 0.4 V IOUT = –10mA, V OVERDRIVE = 50mV l 0.35 0.5 V I+ Positive Supply Current (Per Comparator) V + = 5V, VOVERDRIVE = 1V 15 19 mA l 26 mA I– Negative Supply Current (Per Comparator) V + = 5V, VOVERDRIVE = 1V 8 10 mA l 13 mA VIH Latch Pin High Input Voltage l 2.4 V VIL Latch Pin Low Input Voltage l 0.8 V IIL Latch Pin Current V LATCH = V+ l 15 mA tPD Propagation Delay (Note 6) DVIN = 100mV, VOVERDRIVE = 20mV 4.5 6.0 ns DVIN = 100mV, VOVERDRIVE = 20mV l 8.5 ns DVIN = 100mV, VOVERDRIVE = 5mV 5.5 ns DtPD Differential Propagation Delay (Note 6) DVIN = 100mV, VOVERDRIVE = 20mV 0.5 1.5 ns tr Output Rise Time 10% to 90% 2 ns tf Output Fall Time 90% to 10% 2 ns tLPD Latch Propagation Delay (Note 7) 5n s tSU Latch Setup Time (Note 7) 1n s tH Latch Hold Time (Note 7) 0n s tDPW Minimum Latch Disable Pulse Width (Note 7) 5 ns fMAX Maximum Toggle Frequency V IN = 100mVP-P Sine Wave 100 MHz tJITTER Output Timing Jitter V IN = 630mVP-P (0dBm) Sine Wave, f = 30MHz 11 ps RMS The l denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. V+ = 2.7V or V+ = 5V, V– = 0V, VCM = V+/2, VLATCH = 0.8V, CLOAD = 10pF, VOVERDRIVE = 20mV, unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V+ Positive Supply Voltage Range l 2.4 7 V V– Negative Supply Voltage Range (Note 3) l –7 0 V VOS Input Offset Voltage (Note 4) R S = 50W , VCM = 0V 0.5 5.0 mV RS = 50W , VCM = 0V l 6.0 mV RS = 50W , VCM = 5V 0.7 mV RS = 50W , VCM = –5V 1 mV DVOS/DT Input Offset Voltage Drift 10 mV/°C IOS Input Offset Current 0.2 3 mA l 6 mA IB Input Bias Current (Note 5) – 18 –5 5 mA l –3 5 1 0 mA VCM Input Voltage Range l –5.1 5.1 V CMRR Common Mode Rejection Ratio –5V £ VCM £ 5V 61 75 dB l 58 dB PSRR+ Positive Power Supply Rejection Ratio 2.4V £ V+ £ 7V, VCM = – 5V 58 85 dB l 56 dB PSRR– Negative Power Supply Rejection Ratio –7V £ V– £ 0V, VCM = 5V 60 80 dB l 58 dB The l denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. V+ = 5V, V– = – 5V, VCM = 0V, VLATCH = 0.8V, CLOAD = 10pF, VOVERDRIVE = 20mV, unless otherwise specified.

Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: The LT1711C/LT1712C are guaranteed to meet specified performance from 0°C to 70°C. They are designed, characterized and expected to meet specified performance from –40 °C to 85°C but are not tested or QA sampled at these temperatures. The LT1711I/LT1712I are guaranteed to meet specified performance from –40°C to 85°C. Note 3: The negative supply should not be greater than the ground pin voltage and the maximum voltage across the positive and negative supplies should not be greater than 12V. Note 4: Input offset voltage (V OS) is measured with the LT1711/LT1712 in a configuration that adds external hysteresis. It is defined as the average of the two hysteresis trip points. Note 5: Input bias current (I B) is defined as the average of the two input currents. Note 6: Propagation delay (tPD) is measured with the overdrive added to the actual VOS. Differential propagation delay is defined as: DtPD = tPD+ – tPD–. Load capacitance is 10pF. Due to test system requirements, the LT1711/LT1712 propagation delay is specified with a 1kW load to ground for –5V supplies, or to mid-supply for 2.7V or 5V single supplies. Note 7: Latch propagation delay (t LPD) is the delay time for the output to respond when the latch pin is deasserted. Latch setup time (tSU) is the SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS AV Small-Signal Voltage Gain 1 15 V/mV VOH Output Voltage Swing HIGH (Note 8) I OUT = 1mA, VOVERDRIVE = 50mV l 4.5 4.8 V IOUT = 10mA, VOVERDRIVE = 50mV l 4.3 4.6 V VOL Output Voltage Swing LOW (Note 8) I OUT = –1mA, V OVERDRIVE = 50mV l 0.20 0.4 V IOUT = –10mA, V OVERDRIVE = 50mV l 0.30 0.5 V I+ Positive Supply Current (Per Comparator) V OVERDRIVE = 1V 17 22 mA l 30 mA I– Negative Supply Current (Per Comparator) V OVERDRIVE = 1V 9 12 mA l 15 mA VIH Latch Pin High Input Voltage l 2.4 V VIL Latch Pin Low Input Voltage l 0.8 V IIL Latch Pin Current V LATCH = V+ l 15 mA tPD Propagation Delay (Notes 6, 11) DVIN = 100mV, VOVERDRIVE = 20mV 4.5 6.0 ns DVIN = 100mV, VOVERDRIVE = 20mV l 8.5 ns DVIN = 100mV, VOVERDRIVE = 5mV 5.5 ns DtPD Differential Propagation Delay (Notes 6, 11) DVIN = 100mV, VOVERDRIVE = 20mV 0.5 1.5 ns tr Output Rise Time 10% to 90% 2 ns tf Output Fall Time 90% to 10% 2 ns tLPD Latch Propagation Delay (Note 7) 5n s tSU Latch Setup Time (Note 7) 1n s tH Latch Hold Time (Note 7) 0n s tDPW Minimum Latch Disable Pulse Width (Note 7) 5 ns fMAX Maximum Toggle Frequency V IN = 100mVP-P Sine Wave 100 MHz tJITTER Output Timing Jitter V IN = 630mVP-P (0dBm) Sine Wave, f = 30MHz 11 ps RMS The l denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. V+ = 5V, V– = – 5V, VCM = 0V, VLATCH = 0.8V, CLOAD = 10pF, VOVERDRIVE = 20mV, unless otherwise specified. interval in which the input signal must remain stable prior to asserting the latch signal. Latch hold time (tH) is the interval after the latch is asserted in which the input signal must remain stable. Latch disable pulse width DPW) is the width of the negative pulse on the latch enable pin that latches in new data on the data inputs. Note 8: Output voltage swings are characterized and tested at V+ = 5V and V– = 0V. They are guaranteed by design and correlation to meet these specifications at V– = –5V. Note 9: The input voltage range is tested under the more demanding conditions of V+ = 5V and V– = –5V. The LT1711/LT1712 are guaranteed by design and correlation to meet these specifications at V– = 0V. Note 10: The LT1711/LT1712 voltage gain is tested at V+ = 5V and V– = –5V only. Voltage gain at single supply V+ = 5V and V+ = 2.7V is guaranteed by design and correlation. Note 11: The LT1711/LT1712 tPD is tested at V+ = 5V and 2.7V with V– = 0V. Propagation delay at V+ = 5V, V– = –5V is guaranteed by design and correlation. Note 12: Care must be taken to make sure that the LT1711/LT1712 do not exceed TJMAX when operating with –5V supplies over the industrial temperature range. TJMAX is not exceeded for DC inputs, but supply current increases with switching frequency (see Typical Performance Characteristics).

TYPICAL PERFOR A CE CHARACTERISTICS UW Propagation Delay vs Load Capacitance Propagation Delay vs Input Common Mode Voltage Propagation Delay vs Positive Supply Voltage Positive Supply Current vs Positive Supply Voltage Negative Supply Current vs Negative Supply Voltage Positive Supply Current vs Switching Frequency Input Bias Current vs Input Common Mode Voltage Input Offset Voltage vs Temperature Propagation Delay vs Temperature TEMPERATURE (°C) –50 INPUT OFFSET VOLTAGE (mV) 2.5 2.0 1.5 1.0 0.5 – 0.5 – 1.0 – 1.5 – 2.0 – 2.5 0 50 75

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–25 25 100 125 VCM = 2.5V VCM = 5V VCM = 0V V+ = 5V V– = 0V LOAD CAPACITANCE (pF) 0 60 100

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t PD+ 40 80 120 PROPAGATION DELAY (ns) tPD– TA = 25°C V+ = 5V V– = 0V VCM = 2.5V VOD = 20mV VSTEP = 100mV TEMPERATURE (°C) –50 PROPAGATION DELAY (ns) 100

171112 G03

–25 25 75 125 tPD+ tPD V+ = 5V V– = 0V VCM = 2.5V VOD = 20mV VSTEP = 100mV CLOAD = 10pF INPUT COMMON MODE (V) PROPAGATION DELAY (ns) 5.5

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4.5 01 3 3.5 3.0 6.0 5.0 4.0 456 tPD– tPD+ TA = 25°C V+ = 5V V– = 0V VOD = 20mV VSTEP = 100mV CLOAD = 10pF 2 4 68 1 0 POSITIVE SUPPLY VOLTAGE (V) PROPAGATION DELAY (ns) 5.5

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4.0 3.0 6.0 5.0 4.5 3.5 tPD– tPD+ TA = 25°C V– = 0V VCM = 2.5V VOD = 20mV VSTEP = 100mV CLOAD = 10pF POSITIVE SUPPLY VOLTAGE (V) POSITIVE SUPPLY CURRENT (PER COMPARATOR) (mA) 2 468

171112 G06

V– = – 5V ∆VIN = 100mV IOUT = 0mA I+ AT –55°C I+ AT 25°C I+ AT 85°C V– = 0V SWITCHING FREQUENCY (MHz) POSITIVE SUPPLY CURRENT (PER COMPARATOR) (mA) 10 20 30 40

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TA = 25°C V+ = 5V V– = 0V CLOAD = 10pF NEGATIVE SUPPLY VOLTAGE (V) –3 –5

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NEGATIVE SUPPLY CURRENT (PER COMPARATOR) (mA) I– AT –55°C I– AT 25°C I– AT 85°C V+= 5V ∆VIN = 100mV IOUT = 0mA INPUT COMMON MODE VOLTAGE (V) INPUT BIAS CURRENT (µA) 246

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–14 –20 01 3 5 V+ = 5V V– = 0V ∆VIN = 0mV IB AT –55°C IB AT 25°C IB AT 125°C

TYPICAL PERFOR A CE CHARACTERISTICS UW Output High Voltage vs Source Current Output Timing Jitter vs Switching Frequency Output Rising Edge, 5V Supply Output Falling Edge, 5V Supply VIN Q VIN Q Output Low Voltage vs Sink Current Input Bias Current vs Temperature UUUPI FU CTIO S V+ (Pins 1): Positive Supply Voltage, Usually 5V. +IN (Pin 2): Noninverting Input. –IN (Pin 3): Inverting Input. V– (Pins 4): Negative Supply Voltage, Usually 0V or – 5V. LATCH ENABLE (Pin 5): Latch Enable Input. With a logic high, the output is latched. TEMPERATURE (°C) –50 INPUT BIAS CURRENT (µA) 100

171112 G10

–25 25 75 125 V+ = 5V V– = 0V VCM = 2.5V SOURCE CURRENT (mA) 0.1 OUTPUT VOLTAGE (V) 5.0 4.9 4.8 4.7 4.6 4.5 4.4 4.3 4.2 4.1 4.0 1.0 10 100

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V+ = 5V V– = 0V ∆VIN = 100mV VOH AT –55°C VOH AT 25°C VOH AT 125°C SINK CURRENT (mA) 0.1 OUTPUT VOLTAGE (V) 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 1.0 10 100

171112 G12

VOL AT –55°C VOL AT 25°C VOL AT 125°C V+ = 5V V– = 0V ∆VIN = 100mV FREQUENCY (MHz) OUTPUT TIMING JITTER (psRMS) 100

171112 G13

TA = 25°C V+ = 5V V– = 0V VCM = 2.5V VIN = 630mVP-P (0dBm) SINE WAVE GND (Pin 6): Ground Supply Voltage, Usually 0V. Q (Pin 7): Noninverting Output. Q (Pin 8): Inverting Output. LT1711

171112 G14 171112 G15

– IN A (Pin 1): Inverting Input of A Channel Comparator. + IN A (Pin 2): Noninverting Input of A Channel Comparator. V– (Pins 3, 6): Negative Supply Voltage, Usually – 5V. Pins 3 and 6 should be connected together externally. V+ (Pins 4, 5): Positive Supply Voltage, Usually 5V. Pins 4 and 5 should be connected together externally. + IN B (Pin 7): Noninverting Input of B Channel Comparator. –IN B (Pin 8): Inverting Input of B Channel Comparator. LATCH ENABLE B (Pin 9): Latch Enable Input of B Channel Comparator. With a logic high, the B output is latched. GND (Pin 10): Ground Supply Voltage of B Channel Comparator, Usually 0V. Q B (Pin 11): Noninverting Output of B Channel Comparator. Q B (Pin 12): Inverting Output of B Channel Comparator. Q A (Pin 13): Inverting Output of A Channel Comparator. Q A (Pin 14): Noninverting Output of A Channel Comparator. GND (Pin 15): Ground Supply Voltage of A Channel Comparator, Usually 0V LATCH ENABLE A (Pin 16): Latch Enable Input of A Channel Comparator. With a logic high, the A output is latched. APPLICATIO S I FOR ATIOWU UU Common Mode Considerations The LT1711/LT1712 are specified for a common mode range of – 5.1V to 5.1V on a –5V supply, or a common mode range of – 0.1V to 5.1V on a single 5V supply. A more general consideration is that the common mode range is from 100mV below the negative supply to 100mV above the positive supply, independent of the actual supply voltage. The criteria for common mode limit is that the output still responds correctly to a small differential input signal. When either input signal falls outside the common mode limit, the internal PN diode formed with the substrate can turn on resulting in significant current flow through the die. Schottky clamp diodes between the inputs and the supply rails speed up recovery from excessive overdrive conditions by preventing these substrate diodes from turning on. Input Bias Current Input bias current is measured with the outputs held at 2.5V with a 5V supply voltage. As with any rail-to-rail differential input stage, the LT1711/LT1712 bias current flows into or out of the device depending upon the com- mon mode level. The input circuit consists of an NPN pair and a PNP pair. For inputs near the negative rail, the NPN pair is inactive, and the input bias current flows out of the device; for inputs near the positive rail, the PNP pair is inactive, and these currents flow into the device. For inputs far enough away from the supply rails, the input bias current will be some combination of the NPN and PNP bias currents. As the differential input voltage increases, the input current of each pair will increase for one of the inputs and decrease for the other input. Large differential input voltages result in different input currents as the input stage enters various regions of operation. To reduce the influence of these changing input currents on system operation, use a low source resistance. Latch Pin Dynamics The internal latches of the LT1711/LT1712 comparators retain the input data (output latched) when their respec- tive latch pin goes high. The latch pin will float to a low state when disconnected, but it is better to ground the

comparators in the same package. the finite supply impedances. portant for the proper operation of ultra high speed circuits. they are both connected directly to the ground plane.

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Figure 1. Typical LT1712 Topside Metal erations. Figure 2 shows several configurations.

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Figure 2. Various Configurations for Introducing Hysteresis

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Figure 3. 75Mbaud Full Duplex Interface on Two Wires characteristic impedance, Z O, of the twisted-pair cable.

• | | ( )

Figure 4. Performance of Figure 3’s Circuit When

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Figure 5. Performance When Operated Simultaneous Bidirectionally (Full Duplex). Crosstalk Appears as Noise.

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• (± )
• ·| | ( ) 231 231 2123 This amounts to an attenuation factor of 0.0978 with the values shown. (The actual voltage on the lines will be cut in half again due to the 120 W Z O.) The reason this attenuation factor is important is that it is the key to deciding the ratio between the R2-R3 resistor divider in the receiver path. This divider allows the receiver to reject the large signal of the local transmitter and instead sense the attenuated signal of the remote transmitter. Note that in the above equations, R2 and R3 are not yet fully determined because they only appear as a sum. This allows the designer to now place an additional constraint on their values. The R2-R3 divide ratio should be set to equal half the attenuation factor mentioned above or: R3/R2 = 1/2 • 0.0976 Having already designed R2 + R3 to be 2.653k (by allocat- ing input impedance across RO, R1 and R2 + R3 to get the requisite 120 W ), R2 and R3 then become 2529 W and 123.5W respectively. The nearest 1% value for R2 is 2.55k and that for R3 is 124W . Voltage-Tunable Crystal Oscillator The front page application is a variant of a basic crystal oscillator that permits voltage tuning of the output fre- quency. Such voltage-controlled crystal oscillators (VCXO) are often employed where slight variation of a stable carrier is required. This example is specifically intended to provide a 4· NTSC sub-carrier tunable oscillator suitable for phase locking. The LT1711 is set up as a crystal oscillator. The varactor diode is biased from the tuning input. The tuning network is arranged so a 0V to 5V drive provides a reasonably symmetric, broad tuning range around the 14.31818MHz center frequency. The indicated selected capacitor sets tuning bandwidth. It should be picked to complement loop response in phase locking applications. Figure 6 is a plot of tuning input voltage versus frequency deviation. Tuning deviation from the 4 · NTSC 14.31818MHz center fre- quency exceeds –240ppm for a 0V to 5V input. INPUT VOLTAGE (V) FREQUENCY DEVIATION (kHz) 2 4 5

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Figure 6. Control Voltage vs Output Frequency for the

Dimensions in inches (millimeters) unless otherwise noted. 8-Lead Plastic MSOP (LTC DWG # 05-08-1660) UPACKAGE DESCRIPTIO Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 16-Lead Plastic SSOP (Narrow 0.150) (LTC DWG # 05-08-1641) GN16 (SSOP) 1098 * DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 12 3 4 5 6 7 8 0.229 – 0.244 (5.817 – 6.198) 0.150 – 0.157 (3.810 – 3.988) 16 15 14 13 0.189 – 0.196* (4.801 – 4.978) 12 11 10 9 0.016 – 0.050 (0.406 – 1.270) 0.015 – 0.004 0° – 8° TYP0.007 – 0.0098 (0.178 – 0.249) 0.053 – 0.068 (1.351 – 1.727) 0.008 – 0.012 (0.203 – 0.305) 0.004 – 0.0098 (0.102 – 0.249) 0.0250 (0.635) BSC 0.009 (0.229) REF MSOP (MS8) 1100 * DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE ** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE 0.021 – 0.006 (0.53 – 0.015) 0° – 6° TYP SEATING PLANE 0.007 (0.18) 0.043 (1.10) MAX 0.009 – 0.015 (0.22 – 0.38) 0.005 – 0.002 (0.13 – 0.05) 0.034 (0.86) REF 0.0256 (0.65) BSC 12 3 4 0.193 – 0.006 (4.90 – 0.15) 8 7 6 5 0.118 – 0.004* (3.00 – 0.102) 0.118 – 0.004** (3.00 – 0.102)

Figure 7. LT1711 Comparator is Configured as a Series Figure 8. Oscillator Waveforms with VS = 3V. Top is dal oscillators are not necessary.

2 The sine wave is filtered

on the second and third harmonics, respectively.

2 Amplitude will be a linear function of comparator output swing, which is supply dependent

nonoscillation versus clipping.

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