LT1203

LT1203 LINER

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n –3dB Bandwidth: 150MHz n 0.1dB Gain Flatness: 30MHz n Channel-to-Channel Switching Time: 25ns n Turn-On/Turn-Off Time: 25ns n High Slew Rate: 300V/µs n Disabled Output Impedance: 10MΩ n 50mV Switching Transient n Channel Separation at 10MHz: >90dB n Differential Gain: 0.02% n Differential Phase: 0.02° n Wide Supply Range: ±5V to ± 15V n Output Short-Circuit Protected n Push-Pull Output SFEATURE D UESCRIPTIO The LT1203 is a wideband 2-input video multiplexer designed for pixel switching and broadcast quality rout- ing. The LT1205 is a dual version that is configured as a 4-input, 2-output multiplexer. These multiplexers act as SPDT video switches with 10ns transition times at toggle rates up to 30MHz. The – 3dB bandwidth is 150MHz and 0.1dB gain flatness is 30MHz. Many parts can be tied together at their outputs by using the enable feature which reduces the power dissipation and raises the output impedance to 10MΩ . Output capaci- tance when disabled is only 3pF and the LT1203 peaks less than 3dB into a 50pF load. Channel crosstalk and disable isolation are greater than 90dB up to 10MHz. An on-chip buffer interfaces to fast TTL or CMOS logic. Switching transients are only 50mV with a 25ns duration. The LT1203 and LT1205 outputs are protected against shorts to ground. The LT1203/LT1205 are manufactured using Linear Technology’s proprietary complementary bipolar process. The LT1203 is available in both the 8-lead PDIP and SO package while the LT1205 is available in the 16-lead narrow body SO package. UA OPPLICATITYPICAL LT1205 LOGIC LOGIC VOUT RED VOUT GREEN VOUT BLUE LT1203 • TA01 EN RED 1 CHANNEL SELECT RED 2 GREEN 1 GREEN 2 BLUE 1 BLUE 2 EN LT1203 LOGIC EN High Speed RGB MUX Large-Signal Response USA OPPLICATI n Broadcast Quality Video Multiplexing n Picture-in-Picture Switching n HDTV n Computer Graphics n Title Generation n Video Crosspoint Matrices n Video Routers

A UGWA WU WARBSOLUTEX I T I S ORDER PART NUMBER LT1203CN8* LT1203CS8* S8 PART MARKING 1203 *See Note 4 Consult factory for Industrial and Military grade parts. ORDER PART NUMBER LT1205CS* TJMAX = 150°C, θJA = 100°C/W TOP VIEW S PACKAGE 16-LEAD PLASTIC SOIC VINO GND VIN1 V – VIN2 GND VIN3 V VOUT1 EN1 LOGIC 1 V VOUT2 EN2 LOGIC 2 TOP VIEW VIN0 GND VIN1 VOUT EN LOGIC N8 PACKAGE 8-LEAD PLASTIC DIP S8 PACKAGE 8-LEAD PLASTIC SOIC TJMAX = 150°C, θJA = 100°C/W (N) TJMAX = 150°C, θJA = 150°C/W (S) WU UPACKAGE/ORDER I FOR ATIO SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VOS Output Offset Voltage Any Input Selected l 10 30 mV Output Offset Matching Between Outputs l 0.3 5 mV ΔVOS/ΔT Output Offset Drift l 40 µV/°C IIN Input Current l 0.6 5 µA RIN Input Resistance V S = ±5V, VIN = ±2V l 15 M Ω VS = ±15V, VIN = ±2V l 25 M Ω CIN Input Capacitance Input Selected 2.6 pF Input Deselected 2.6 pF COUT Disabled Output Capacitance EN Pin Voltage ≤ 0.8V 2.8 pF VIN Input Voltage (Note 1) V S = ±5V l ± 2 ±2.8 V VS = ±15V l ± 2 ±3.0 V PSRR Power Supply Rejection Ratio V S = ±4.5 to ±15V l 60 70 dB Gain Error V S = ±15V, VIN = ±2V, RL = 1k l 24 % VS = ±15V, VIN = ±2V, RL = 400Ω l 61 0 % VS = ±5V, VIN = ±2V, RL = 1k l 36 % ELECTRICAL C CHARA TERISTICS 0°C ≤ TA ≤ 70°C, ±5V ≤ VS ≤ ± 15V, RL = 1k, pulse tested, EN pin open or high, unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS SR Slew Rate (Note 6) 180 300 V/ µs FPBW Full Power Bandwidth (Note 7) V OUT = 2VP-P 28.6 47.7 MHz tSEL Channel-to-Channel Select Time (Note 8) R L = 10k 25 35 ns Enable Time (Note 9) R L = 1k 25 35 ns Disable Time (Note 9) R L = 1k 20 35 ns tr, tf Small-Signal Rise and Fall Time V OUT = 250mVP-P, 10% to 90% 2.6 ns Propagation Delay V OUT = 250mVP-P 2.9 ns Overshoot V OUT = 250mVP-P 5% Crosstalk (Note 10) R S = 10Ω 90 dB Chip Disabled Crosstalk (Note 10) R L = 10Ω , EN Pin Voltage ≤ 0.8V 110 dB Channel Select Output Transient All V IN = 0V 50 mV P-P tS Settling Time 1%, V OUT = 1V 30 ns Differential Gain (Note 11) V S = ±15V, RL = 10k 0.02 % Differential Phase (Note 11) V S = ±15V, RL = 10k 0.02 DEG Insertion Loss R L = 100k, CL = 30pF, VOUT = 500mVP-P, f = 1MHz 0.02 dB ELECTRICAL C CHARA TERISTICS 0°C ≤ TA ≤ 70°C, ± 5V ≤ VS ≤ ±15V, RL = 1k, pulse tested, EN pin open or high, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VOUT Output Voltage V S = ±15V, VIN = ± 2V, RL = 400Ω l ±1.8 ±1.90 V VS = ±5V, VIN = ±2V, RL = 1k l ±1.8 ±1.94 V Overload Swing (Note 1) V S = ±15V, VIN = ± 5V l ±0.9 ±1.5 V VS = ±5V, VIN = ±5V l ±0.9 ±1.5 V IOUT Output Current V S = ±15V, VIN = ± 2V, RL = 400Ω l ±4.5 ±4.75 mA VS = ±5V, VIN = ±2V, RL = 1k l ±1.8 ±2.00 mA ROUT Enabled Output Resistance EN Pin Voltage = 2V, V OUT = ±2V, VS = ±15V l 20 42 Ω Disabled Output Resistance EN Pin Voltage = 0.5V, V OUT = ±2V, VS = ±15V l 11 0 M Ω IS Supply Current (LT1203) EN Pin Voltage = 2V l 10.0 14 mA EN Pin Voltage = 0.5V l 5.8 8 mA Supply Current (LT1205) EN Pin Voltage = 2V l 20.0 28 mA EN Pin Voltage = 0.5V l 11.6 16 mA VIL Logic Low Logic Pin l 0.8 V VIH Logic High Logic Pin l 2V Enable Low EN Pin l 0.5 V Enable High EN Pin l 2V IIL Digital Input Current Low LT1203 Pin 5, LT1205 Pins 9, 13 = 0V l 1.5 6.5 µA IIH Digital Input Current High LT1203 Pin 5, LT1205 Pins 9, 13 = 5V l 10 200 nA IEN Enable Pin Current LT1203 Pin 6, LT1205 Pins 10, 14 l 20 80 µA CCHARA TERISTICSAC TA = 25°C, VS = ±15V, RL = 1k, EN pin open or high, unless otherwise noted. The l denotes specifications which apply over the specified temperature range. Note 1: The analog inputs (pins 1, 3 for the LT1203, pins 1, 3, 5, 7 for the LT1205) are protected against ESD and overvoltage with internal SCRs. For inputs ≤± 2.8V the SCR will not fire. Voltages above 2.8V will fire the SCR and the DC current should be limited to 20mA. To turn off the SCR the pin voltage must be reduced to less than 1V or the current reduced to less than 600µA.

Note 2: The digital inputs (pins 5, 6 for the LT1203, pins 9, 10, 13, 14 for the LT1205) are protected against ESD and overvoltage with internal SCRs. For inputs ≤± 6V the SCR will not fire. Voltages above 6V will fire the SCR and the DC current should be limited to 50mA. To turn off the SCR the pin voltage must be reduced to less than 2V or the current reduced to less than 10mA. Note 3: A heat sink may be required depending on the power supply voltage. Note 4: Commercial grade parts are designed to operate over the temperature range of –40 °C to 85°C but are neither tested nor guaranteed beyond 0°C to 70°C. Industrial grade parts specified and tested over –40 °C to 85°C are available on special request, consult factory. Note 5: T J is calculated from the ambient temperature TA and the power dissipation PD according to the following formulas: LT1203CN8: TJ = TA + (PD × 100°C/W) LT1203CS8: TJ = TA + (PD × 150°C/W) LT1205CS: TJ = TA + (PD × 100°C/W) Note 6: Slew rate is measured at ±2.0V on a ±2.5V output signal while operating on ±15V supplies, RL = 1k. Note 7: Full power bandwidth is calculated from the slew rate measurement: FPBW = SR/2πVPEAK Note 8: For the LT1203, apply 1VDC to pin 1 and measure the time for the appearance of 0.5V at pin 7 when pin 5 goes from 5V to 0V. Apply 1VDC to pin 1 and measure the time for disappearance of 0.5V at pin 7 when pin 5 goes from 0V to 5V. Apply 1VDC to pin 3 and measure the time for the appearance of 0.5V at pin 7 when pin 5 goes from 0V to 5V. Apply 1VDC to pin 3 and measure the time for disappearance of 0.5V at pin 7 when pin 5 goes from 5V to 0V. For the LT1205 the same test is performed on both MUXs. Note 9: For the LT1203, apply 1VDC to pin 1 and measure the time for the appearance of 0.5V at pin 7 when pin 6 goes from 0V to 5V. Pin 5 voltage = 0V. Apply 1VDC to pin 1 and measure the time for disappearance of 0.2V at pin 7 when pin 6 goes from 5V to 0V. Pin 5 voltage = 0V. Apply 1VDC to pin 3 and measure the time for the appearance of 0.5V at pin 7 when pin 6 goes from 0V to 5V. Pin 5 voltage = 5V. Apply 1VDC to pin 3 and measure the time for disappearance of 0.2V at pin 7 when pin 5 goes from 5V to 0V. Pin 5 voltage = 5V. For the LT1205 the same test is performed on both MUXs. Note 10: V IN = 0dBm (0.223VRMS) at 10MHz on one input with the other input selected and RS = 10Ω . For disable crosstalk all inputs are driven simultaneously. In disable the output impedance is very high and signal couples across the package; the load impedance determines the crosstalk. Note 11: Differential gain and phase are measured using a Tektronix TSG120 YC/NTSC signal generator and a Tektronix 1780R video measurement set. The resolution of this equipment is 0.1% and 0.1°. Ten identical MUXs were cascaded giving an effective resolution of 0.01% and 0.01°. TYPICAL PERFOR A CE CHARACTERISTICSWU LOGIC EN V OUT 01V IN0 11V IN1 0 0* HIGH Z OUT 1 0 HIGH Z OUT *Must be ≤ 0.5V TRUTH TABLE FREQUENCY (MHz) GAIN (dB) PHASE (DEG) 10 100 1000 LT1203/05 • TPC02 –120 –100 –80 –60 –40 –140 –160 –180 –200 –20 VS = ±15V TA = 25°C RL = ∞ FREQUENCY (MHz) GAIN (dB) PHASE (DEG) 10 100 1000 LT1203/05 • TPC01 –120 –100 –80 –60 –40 –140 –160 –180 –200 –20 VS = ±5V TA = 25°C RL = ∞ ±5V Frequency Response ±15V Frequency Response

TYPICAL PERFOR A CE CHARACTERISTICSWU Frequency Response with Capacitive Loads Disable Rejection vs Frequency Crosstalk Rejection vs Frequency Output Impedance (Enabled) vs Frequency Crosstalk Rejection vs Frequency SUPPLY VOLTAGE (±V) FREQUENCY (MHz) 160 180 LT1203/05 • TPC03 140 120 2 6 8 10 12 14 164 200 TA = 25°C RL = 10k PEAKING ≤ 0.5dB FREQUENCY (MHz) GAIN (dB) 10 100 LT1203/05 • TPC04 VS = ±15V TA = 25°C RL = ∞ CL = 100pF CL = 50pF CL = 20pF CL = 10pF FREQUENCY (MHz) –110 CROSSTALK REJECTION (dB) –100 –90 –80 –70 –30 10 100 LT1203/05 • TPC05 –6 0 –50 –4 0 VS = ±15V TA = 25°C RL = ∞ RS = 0Ω RS = 10Ω RS = 37.5Ω RS = 75Ω FREQUENCY (MHz) –110 CROSSTALK REJECTION (dB) –100 –9 0 –80 –70 –30 10 100 LT1203/05 • TPC06 –6 0 –50 –4 0 TA = 25°C RS = 0Ω RL = ∞ VS = ±5V VS = ±15V FREQUENCY (MHz) –70 –80 –90 –100 –110 –120 DISABLE REJECTION (dB) –6 0 –50 –4 0 –30 10 100 LT1203/05 • TPC07 –20 VS = ±15V TA = 25°C RL = ∞ RL = 1k RL = 100Ω RL = 10Ω FREQUENCY (MHz) LT1203/05 • TPC08 POWER SUPPLY REJECTION RATIO (dB) 1 10010 VS = ±15V TA = 25°C RL = ∞ RS = 0Ω–PSRR +PSRR Supply Current vs Supply Voltage (Enabled) Supply Current vs Supply Voltage (Disabled) FREQUENCY (Hz) OUTPUT IMPEDANCE (Ω ) 100 10k 1M 100M 10M LT1203/05 • TPC09 100k VS = ±15V TA = 25°C SUPPLY VOLTAGE (±V) 7.6 SUPPLY CURRENT (mA) 8.4 9.6 4 8 10 18 LT1203/05 • TPC10 8.0 9.2 8.8 26 12 14 16 LT1203 RL = ∞ 125° 25° –55° SUPPLY VOLTAGE (±V) 4.4 SUPPLY CURRENT (mA) 4.8 4 8 10 18 LT1203/05 • TPC11 4.6 5.2 5.0 26 12 14 16 125° 25° LT1203 RL = ∞ –55° – 3dB Bandwidth vs Supply Voltage Power Supply Rejection Ratio vs Frequency

TYPICAL PERFOR A CE CHARACTERISTICSWU TEMPERATURE (°C) –50 25 75 LT1203/05 • TPC12 –25 0 50 100 125 GAIN ERROR (%) VS = ±15V VIN = –2V TO 2V RL = 400Ω RL = 1k Gain Error vs Temperature INPUT VOLTAGE (V) INPUT BIAS CURRENT (µA) 0.4 0.6 0.8 LT1203/05 • TPC13 0.2 – 0.4 –2 0 2 – 0.2 1.2 1.0 –3 –1 1 3 125°C 25°C –55°C VS = ±15V RL = ∞ INPUT VOLTAGE (V) OUTPUT VOLTAGE (V) LT1203/05 • TPC14 –3 –1 1 5 2–4 –2 0 4 VS = ±15V TA = 25°C RL = 1k Output Voltage vs Input Voltage Small-Signal Rise Time RL = 1k VIN0 to VIN1 Select TimeVIN1 to VIN0 Select Time Settling Time to 1mV and 10mV vs Output Step SETTLING TIME (ns) OUTPUT STEP (V) 1.0 2.0 400 LT1203/05 • TPC15 –1.0 –2.0 100 200 300 500 0.5 1.5 –0.5 –1.5 10mV 10mV 1mV 1mV VS = ±15V RL = 1k LT1203/05 • TPC16 VS = ±15V RL = 10k LT1203/05 • TPC17 LT1203/05 • TPC18VS = ±15V RL = 10k LOGIC (PIN 5) VOUT (PIN 7) LOGIC (PIN 5) VOUT (PIN 7) Input Bias Current vs Input Voltage VINO = 1V VIN1 = 0V VINO = 1V VIN1 = 0V

TYPICAL PERFOR A CE CHARACTERISTICSWU Channel 1 Disable VS = ±15V RL = 1k LT1203/05 • TPC19 VS = ±15V RL = 1k Channel 1 Enable LT1203/05 • TPC20 Input Protection The logic inputs have ESD protection (≥ 2kV) and short- ing them to 12V or 15V will cause excessive current to flow. Limit the current to less than 50mA when driving the logic above 6V. The analog inputs are protected against ESD and overvoltage with internal SCRs. For inputs ≥± 2.8V the SCRs will fire and the DC current should be limited to 20mA. Power Supplies The LT1203/LT1205 will operate from ± 5V (10V total) to ±15V (30V total) and is specified over this range. Charac- teristics change very little over this voltage range. It is not necessary to use equal value supplies however, the output offset voltage will change. The offset will change about 300µV per volt of supply mismatch. The LT1203/LT1205 have a very wide bandwidth yet are tolerant of power supply bypassing. The power supplies should be by- passed with a 0.1µF or 0.01µF ceramic capacitor within 0.5 inch of the part. Circuit Layout Use a ground plane to ensure a low impedance ground is available throughout the PCB layout. Separate the inputs USA OPPLICATI WU UI FOR ATIO LT1203 Channel-to-Channel Switching Transient with ground plane to ensure high channel separation. For minimum peaking, maximum bandwidth and maximum gain flatness sockets are not recommended because they can add considerable stray inductance and capacitance. If a socket must be used, use a low profile, low capacitance socket such as the SamTec ISO-308. Switching Transients The LT1203/LT1205 use input buffers to ensure switching transients do not couple to other video equipment sharing the input line. Output switching transients are about 50mV P-P with a 20ns duration and input transients are OUTPUT 50mV/DIV INPUT 20mV/DIV LOGIC (PIN 5) RS = 50Ω LT1203/05 • AI01 VINO = 1V VIN1 = 0V VINO = 1V VIN1 = 0V EN (PIN 6) VOUT (PIN 7) VOUT (PIN 7) EN (PIN 6)

same when switching between channels or between ICs. showing the Workstation output and RGB MUX output. pixel and removes the following pixels. Figure 1. RGB MUX

Figure 3. Demo Board #041 Layout

6 OUTPUT

Figure 5. 16-to-1 Multiplexer and Truth Table

output impedance of only 25Ω at 10MHz. This attenuator is responsible for the outstanding All Hostile Crosstalk Rejection of 90dB at 10MHz with 15 input signals. Several suggestions to attain this high rejection include: 1. Mount the feedback resistors for the surface mount LT1252 on the back side of the PC board. 2. Keep the feedback trace (pin 3) of the LT1252 as short as possible. 3. Route V+ and V– for the LT1205s on the component (top) side and under the devices (between inputs and outputs). 4. Use the backside of the PC board as a solid ground plane. Connect the LT1205 device grounds and by- pass capacitors grounds as vias to the backside ground plane. USA OPPLICATI WU UI FOR ATIO 16-to-1 MUX, Switching LT1205 Enable Lines RF = RG = 1.6k RL = 100Ω VIN4 = 0V VIN0 = 1V LT1203/05 • AI05 16-to-1 Multiplexer All Hostile Crosstalk Rejection 16-to-1 MUX Response FREQUENCY (MHz) GAIN (dB) 10 100 LT1203/05 • AI07 VS = ±15V RL = 100Ω RF = RG = 1.6k Each “off” switch has 2.8pF of output capacitance and 15 “off” switches tied together represent a 48pF load to the one active switch. In this case the active device will peak about 3dB at 50MHz. An attribute of current feedback amplifiers is that the bandwidth can easily be adjusted by changing the feedback resistors, and in this application the LT1252’s bandwidth is reduced to about 60MHz using 1.6k feedback resistors. This has the effect of reducing the peaking in the MUX to 0.25dB and flattening the response to 0.05dB at 30MHz. 4 × 4 Crosspoint The compact high performance 4 × 4 crosspoint shown in Figure 6 uses four LT1205s to route any input to any or all outputs. The complete crosspoint uses only six SO pack- ages and less than six square inches of PC board space. The LT1254 quad current feedback amplifier serves as a cable driver with a gain of 2. A ± 5V supply is used to ensure that the maximum 150 °C junction temperature of the LT1254 is not exceeded in the SO package. With this supply voltage the crosspoint can operate at a 70 °C ambient temperature and drive 2V (peak or DC) into a double-terminated 75Ω video cable. The feedback resis- tors of these output amplifiers have been optimized for this supply voltage. The –3dB bandwidth of the crosspoint is over 100MHz with only 0.8dB of peaking. All Hostile Crosstalk Rejection is 85dB at 10MHz when a shorted input is routed to all outputs. To obtain this level of performance it is necessary to follow techniques similar to SELECT LINE C FREQUENCY (MHz) –120HOSTILE CROSSTALK REJECTION (dB) –100 –80 –60 –40 10 100 LT1203/05 • AI06 –20 VS = ±15V RS = 10Ω RL = 100Ω

Figure 6. 4 × 4 Crosspoint and Truth Table

USA OPPLICATI WU UI FOR ATIO those used in the 16-to-1 crosspoint with one additional suggestion: Surround the LT1205 output traces by ground plane and route them away from the (–) inputs of the other three LT1254s. Each pair of logic inputs labeled Select Logic Output is used to select a particular output. The truth table is used to select the desired input and is applied to each pair of logic inputs. For example, to route Channel 1 Input to Output 3, the 4th pair of logic inputs labeled Select Logic Output 3 is coded A = Low and B = High. To route Channel 3 Input to all outputs, set all eight logic inputs High. Channel 3 is the default input with all logic inputs open. To shut off all channels a pair of LT1259s can be substituted for the LT1254. The LT1259 is a dual current feedback amplifier with a shutdown pin that reduces the supply current to 0µA. Response of All Four Inputs for the 4 × 4 Crosspoint FREQUENCY (MHz) GAIN (dB) 10 100 LT1203/05 • AI08 200 VS = ±5V RF = RG = 820Ω RL = 100Ω LT1203/05 • AI10CHANNEL 0 = 1V CHANNEL 2 = 0V 4 × 4 Crosspoint, Switching Channel 0 to Channel 2 INPUT A OF SELECT LOGIC OUTPUT 0 4 × 4 Crosspoint, All Hostile Rejection FREQUENCY (MHz) –120HOSTILE CROSSTALK REJECTION (dB) –100 –80 –60 –40 10 100 VS = ±5V RL = 100Ω RS = 0Ω LT1203/05 • AI09

LT1203/05 • SS OUTIN 1 –2V LOGIC SI PLIFIED SCHE ATICWW Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. Dimensions in inches (millimeters) unless otherwise noted.PACKAGE DESCRIPTIOU 8-Lead Plastic DIP N8 0392 0.045 ± 0.015 (1.143 ± 0.381) 0.100 ± 0.010 (2.540 ± 0.254) 0.065 (1.651) TYP 0.045 – 0.065 (1.143 – 1.651) 0.130 ± 0.005 (3.302 ± 0.127) 0.020 (0.508) MIN 0.018 ± 0.003 (0.457 ± 0.076) 0.125 (3.175) MIN 12 3 4 87 6 5 0.250 ± 0.010 (6.350 ± 0.254) 0.400 (10.160) MAX 0.009 – 0.015 (0.229 – 0.381) 0.300 – 0.320 (7.620 – 8.128) 0.325 +0.025 –0.015 +0.635 –0.3818.255()

Dimensions in inches (millimeters) unless otherwise noted. 8-Lead Plastic SOIC 1 2 3 4 0.150 – 0.157* (3.810 – 3.988) 8 7 6 5 0.189 – 0.197* (4.801 – 5.004) 0.228 – 0.244 (5.791 – 6.197) 0.016 – 0.050 0.406 – 1.270 0.010 – 0.020 0°– 8° TYP 0.008 – 0.010 (0.203 – 0.254) SO8 0294 0.053 – 0.069 (1.346 – 1.752) 0.014 – 0.019 (0.355 – 0.483) 0.004 – 0.010 (0.101 – 0.254) 0.050 (1.270) BSC *THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006 INCH (0.15mm). 0.016 – 0.050 0.406 – 1.270 0.010 – 0.020 0° – 8° TYP 0.008 – 0.010 (0.203 – 0.254) 1 2 3 4 5 6 7 8 0.150 – 0.157* (3.810 – 3.988) 16 15 14 13 0.386 – 0.394* (9.804 – 10.008) 0.228 – 0.244 (5.791 – 6.197) 12 11 10 9 SO16 0893 0.053 – 0.069 (1.346 – 1.752) 0.014 – 0.019 (0.355 – 0.483) 0.004 – 0.010 (0.101 – 0.254) 0.050 (1.270) TYP *THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006 INCH (0.15mm). S Package 16-Lead Plastic SOIC  LINEAR TECHNOLOGY CORPORA TION 1994 LT/GP 0494 10K • PRINTED IN USA Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7487 (408) 432-1900 l FAX: (408) 434-0507 l TELEX: 499-3977