LPV511 Micropower, Rail-to-Rail Input and Output Operational Amplifier datasheet (Rev. D)
Document overview
- Manufacturer or author: Texas Instruments, Incorporated [SNOSAG7,D]
- PDF pages: 26
Technical content
0.2 R SENSE R 1 2 N 2 N R 2 10 N R 3 Copyright © 2016, Texas Instruments Incorporated 3SENSE R OUT CHARGE CHARGE R V I 1 I R u u :u 0 4 10 0.2 0.4 0.6 0.8 1.6 SUPPLY CURRENT ( PA) SUPPLY VOLTAGE (V) 1.2 1.4 25°C 85ºC 125°C 2 6 8 12 -40°C Product Folder Sample & Buy T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LPV511 SNOSAG7D –AUGUST 2005–REVISED AUGUST 2016 LPV511Micropower,Rail-to-RailInputandOutputOperationalAmplifier
1 Features
1• Wide Supply Voltage Range: 2.7 V to 12 V
- Slew Rate: 7.7 V/ms
- Supply Current: 880 nA
- Output Short-Circuit Current: 1.35 mA
- Rail-to-Rail Input
- Rail-to-Rail Output: 100 mV from Rails
- Bandwidth (CL = 50 pF, RL = 1 MΩ): 27 kHz
- Unity Gain Stable
2 Applications
- Battery Powered Systems
- Security Systems
- Micropower Thermostats
- Solar Powered Systems
- Portable Instrumentation
- Micropower Filters
- Remote Sensor Amplifiers
3 Description
The LPV511 is a micropower operational amplifier that operates from a voltage supply range as wide as
2.7 V to 12 V with ensured specifications at 3 V, 5 V,
and 12 V. The ultra-low power LPV511 exhibits an excellent speed to power ratio, drawing only 880 nA of supply current with a bandwidth of 27 kHz. These specifications make the LPV511 an ideal choice for battery-powered systems that require long life through low supply current, such as instrumentation, sensor conditioning and battery current monitoring. The LPV511 has an input range that includes both supply rails for ground and high-side battery sensing applications. The LPV511 output swings within 100 mV of either rail to maximize the signal's dynamic range in low supply applications. In addition, the output is capable of sourcing 650 µA of current when powered by a 12-V battery. The LPV511 is fabricated on TI's advanced VIP50C process. The LPV511 is available in the space-saving SC70 package, which makes it ideal for portable electronics with area-constrained PC boards. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) LPV511 SC70 (5) 2.00 mm × 1.25 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Typical Supply Current High-Side Battery Current Sensor
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12 Mechanical, Packaging, and Orderable
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision C (March 2013) to Revision D Page
- Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Changes from Revision B (March 2013) to Revision C Page
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5 Pin Configuration and Functions
NO. NAME
1 VOUT O Output
2 V– P Negative supply voltage
3 VIN
+ I Noninverting input
4 VIN
– I Inverting input
5 V+ P Positive supply voltage
SNOSAG7D –AUGUST 2005–REVISED AUGUST 2016 www.ti.com Product Folder Links: LPV511 Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) If Military/Aerospace specified devices are required, contact the Texas Instruments Sales Office/ Distributors for availability and specifications. (3) Output short-circuit duration is infinite for V+ < 6 V at room temperature and below. For V+ > 6 V, allowable short-circuit duration is 1.5 ms. (4) The maximum power dissipation is a function of TJ(MAX), RθJA, and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) – TA) / RθJA. All numbers apply for packages soldered directly onto a PC board.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)(2) MIN MAX UNIT VIN Differential 2.1 V Supply voltage (V+ - V−) 13.2 V Voltage at input and output pins V+ + 0.3 V− − 0.3 V Short-circuit duration See(3) Junction temperature, TJ(4) 150 °C Storage temperature, Tstg –65 150 °C (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) Human Body Model: 1.5 kΩ in series with 100 pF. (3) Machine Model: 0 Ω in series with 200 pF.
6.2 ESD Ratings
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)(2) ±2000 V Machine model (MM)(3) ±200 (1) The maximum power dissipation is a function of TJ(MAX), RθJA, and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) – TA) / RθJA. All numbers apply for packages soldered directly onto a PC board.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT Temperature(1) –40 85 °C Supply voltage (V+ – V−) 2.7 12 V (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
6.4 Thermal Information
THERMAL METRIC(1) LPV511 UNITDCK (SC70)
5 PINS
RθJA Junction-to-ambient thermal resistance 278 °C/W RθJC(top) Junction-to-case (top) thermal resistance 105.8 °C/W RθJB Junction-to-board thermal resistance 56.4 °C/W ψJT Junction-to-top characterization parameter 3 °C/W ψJB Junction-to-board characterization parameter 55 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance n/a °C/W
www.ti.com SNOSAG7D –AUGUST 2005–REVISED AUGUST 2016 Product Folder Links: LPV511 Submit Documentation FeedbackCopyright © 2005–2016, Texas Instruments Incorporated (1) Electrical table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device. (2) Limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlations using the Statistical Quality Control (SQC) method. (3) Typical values represent the most likely parametric norm at the time of characterization. (4) Offset voltage drift is specified by design and/or characterization and is not tested in production. Offset voltage drift is determined by dividing the change in VOS at temperature extremes into the total temperature change. (5) Positive current corresponds to current flowing into the device. (6) The Short-Circuit Test is a momentary test. See Note 3 in Absolute Maximum Ratings. (7) Slew rate is the average of the rising and falling slew rates.
6.5 Electrical Characteristics: 3 V
Unless otherwise specified, all limits are specified for TJ = 25°C, V+ = 3 V, V− = 0 V, VCM = VO = V+/2, and RL = 100 kΩ to V+/2.(1) PARAMETER TEST CONDITIONS MIN(2) TYP(3) MAX(2) UNIT VOS Input offset voltage TJ = 25°C ±0.2 ±3 mV TJ = –40°C to 85°C ±3.8 TC VOS Input offset voltage drift(4) TJ = 25°C ±0.3 µV/°C TJ = –40°C to 85°C ±15 IB Input bias current(5) VCM = 0.5 V TJ = 25°C –1000 –320 pA TJ = –40°C to 85°C –1600 VCM = 2.5 V TJ = 25°C 110 800 TJ = –40°C to 85°C 1900 IOS Input offset current ±10 pA CMRR Common mode rejection ratio VCM Stepped from 0 V to 1.5 V TJ = 25°C 77 100 dB TJ = –40°C to 85°C 70 VCM Stepped from 2.4 V to 3 V TJ = 25°C 75 115 TJ = –40°C to 85°C 68 VCM Stepped from 0.5 V to 2.5 V TJ = 25°C 60 80 TJ = –40°C to 85°C 56 PSRR Power supply rejection ratio V+ = 2.7 V to 5 V, VCM = 0.5 V TJ = 25°C 72 114 dB TJ = –40°C to 85°C 68 V+ = 3 V to 5 V, VCM = 0.5 V TJ = 25°C 76 115 TJ = –40°C to 85°C 72 V+ = 5 V to 12 V, VCM = 0.5 V TJ = 25°C 84 117 TJ = –40°C to 85°C 80 CMVR Input common-mode voltage CMRR ≥ 50 dB TJ = 25°C −0.1 3.1 V TJ = –40°C to 85°C 0 3 AVOL Large signal voltage gain Sinking, VO = 2.5 V TJ = 25°C 75 105 dB TJ = –40°C to 85°C 70 Sourcing, VO = 0.5 V TJ = 25°C 75 105 TJ = –40°C to 85°C 70 VO Output swing high VID = 100 mV TJ = 25°C 2.85 2.9 V TJ = –40°C to 85°C 2.8 Output swing low VID = −100 mV TJ = 25°C 100 150 TJ = –40°C to 85°C 200 ISC Output short circuit current(6) Sourcing VID = 100 mV −500 −225 µA Sinking VID = −100 mV 225 1350 IS Supply current TJ = 25°C 0.88 1.2 µA TJ = –40°C to 85°C 1.5 SR Slew rate(7) AV = 1, VO ramps from 0.5 V to 2.5 V TJ = 25°C 5.25 7.7 V/ms TJ = –40°C to 85°C 3.10
SNOSAG7D –AUGUST 2005–REVISED AUGUST 2016 www.ti.com Product Folder Links: LPV511 Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated Electrical Characteristics: 3 V (continued) Unless otherwise specified, all limits are specified for TJ = 25°C, V+ = 3 V, V− = 0 V, VCM = VO = V+/2, and RL = 100 kΩ to V+/2.(1) PARAMETER TEST CONDITIONS MIN(2) TYP(3) MAX(2) UNIT GBW Gain bandwidth product RL = 1 MΩ, CL= 50 pF 27 kHz Phase margin RL = 1 MΩ, CL= 50 pF 53 º en Input-referred voltage noise f = 100 Hz 320 nV/√Hz in Input-referred current noise f = 10 Hz 0.02 pA/√Hz f = 1 kHz 0.01 (1) Electrical table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device. (2) Limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlations using the Statistical Quality Control (SQC) method. (3) Typical values represent the most likely parametric norm at the time of characterization. (4) Offset voltage drift is specified by design and/or characterization and is not tested in production. Offset voltage drift is determined by dividing the change in VOS at temperature extremes into the total temperature change. (5) Positive current corresponds to current flowing into the device.
6.6 Electrical Characteristics: 5 V
Unless otherwise specified, all limits are specified for TJ = 25°C, V+ = 5 V, V− = 0 V, VCM = VO = V+/2, and RL = 100 kΩ to V+/2.(1) PARAMETER TEST CONDITIONS MIN(2) TYP(3) MAX(2) UNIT VOS Input offset voltage TJ = 25°C ±0.2 ±3 mV TJ = –40°C to 85°C ±3.8 TC VOS Input offset voltage drift(4) TJ = 25°C ±0.3 µV/°C TJ = –40°C to 85°C ±15 IB Input bias current(5) VCM = 0.5 V TJ = 25°C –1000 –320 pA TJ = –40°C to 85°C –1600 VCM = 4.5 V TJ = 25°C 110 800 TJ = –40°C to 85°C 1900 IOS Input offset current ±10 pA CMRR Common mode rejection ratio VCM Stepped from 0 V to 2.5 V TJ = 25°C 80 115 dB TJ = –40°C to 85°C 73 VCM Stepped from 4.4 to 5 V TJ = 25°C 75 107 TJ = –40°C to 85°C 68 VCM Stepped from 0.5 to 4.5 V TJ = 25°C 65 87 TJ = –40°C to 85°C 62 PSRR Power supply rejection ratio V+ = 2.7 V to 5 V, VCM = 0.5 V TJ = 25°C 72 114 dB TJ = –40°C to 85°C 68 V+ = 3 V to 5 V, VCM = 0.5 V TJ = 25°C 76 115 TJ = –40°C to 85°C 72 V+ = 5 V to 12 V, VCM = 0.5 V TJ = 25°C 84 117 TJ = –40°C to 85°C 80 CMVR Input common-mode voltage CMRR ≥ 50 dB V TJ = –40°C to 85°C 0 5 AVOL Large signal voltage gain Sinking, VO = 4.5 V TJ = 25°C 78 110 dB TJ = –40°C to 85°C 73 Sourcing, VO = 0.5 V TJ = 25°C 78 110 TJ = –40°C to 85°C 73
www.ti.com SNOSAG7D –AUGUST 2005–REVISED AUGUST 2016 Product Folder Links: LPV511 Submit Documentation FeedbackCopyright © 2005–2016, Texas Instruments Incorporated Electrical Characteristics: 5 V (continued) Unless otherwise specified, all limits are specified for TJ = 25°C, V+ = 5 V, V− = 0 V, VCM = VO = V+/2, and RL = 100 kΩ to V+/2.(1) PARAMETER TEST CONDITIONS MIN(2) TYP(3) MAX(2) UNIT (6) The Short-Circuit Test is a momentary test. See Note 3 in Absolute Maximum Ratings. (7) Slew rate is the average of the rising and falling slew rates. VO Output swing high VID = 100 mV TJ = 25°C 4.8 4.89 V TJ = –40°C to 85°C 4.75 Output swing low VID = −100 mV TJ = 25°C 110 200 mV TJ = –40°C to 85°C 250 ISC Output short circuit current(6) Sourcing to V− VID = 100 mV –550 –225 µA Sinking to V+ VID = −100 mV 225 1350 IS Supply current TJ = 25°C 0.97 1.2 µA TJ = –40°C to 85°C 1.5 SR Slew rate(7) AV = 1, VO ramps from 0.5 V to 4.5 V TJ = 25°C 5.25 7.5 V/ms TJ = –40°C to 85°C 3.1 GBW Gain bandwidth product RL = 1 MΩ, CL= 50 pF 27 kHz Phase margin RL = 1 MΩ, CL= 50 pF 53 ° en Input-referred voltage noise f = 100 Hz 320 nV/√Hz in Input-referred current noise f = 10 Hz 0.02 pA/√Hz f = 1 kHz 0.01 (1) Electrical table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device. (2) Limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlations using the Statistical Quality Control (SQC) method. (3) Typical values represent the most likely parametric norm at the time of characterization. (4) Offset voltage drift is specified by design and/or characterization and is not tested in production. Offset voltage drift is determined by dividing the change in VOS at temperature extremes into the total temperature change. (5) Positive current corresponds to current flowing into the device.
6.7 Electrical Characteristics: 12 V
Unless otherwise specified, all limits are specified for TJ = 25°C, V+ = 12 V, V− = 0 V, VCM = VO = V+/2, and RL = 100 kΩ to V+/2.(1) PARAMETER TEST CONDITIONS MIN(2) TYP (3) MAX (2) UNIT VOS Input offset voltage TJ = 25°C ±0.2 ±3 mV TJ = –40°C to 85°C ±3.8 TC VOS Input offset voltage drift(4) TJ = 25°C ±0.3 µV/°C TJ = –40°C to 85°C ±15 IB Input bias current(5) VCM = 0.5 V TJ = 25°C −1000 −320 pA TJ = –40°C to 85°C −1600 VCM = 11.5 V TJ = 25°C 110 800 TJ = –40°C to 85°C 1900 IOS Input offset current ±10 pA CMRR Common mode rejection ratio VCM Stepped from
0 V to 6 V
TJ = 25°C 75 115 dB TJ = –40°C to 85°C 70 VCM Stepped from
11.4 V to 12 V
TJ = 25°C 75 110 TJ = –40°C to 85°C 68 VCM Stepped from 0.5 V to 11.5 V TJ = 25°C 70 97 TJ = –40°C to 85°C 65
SNOSAG7D –AUGUST 2005–REVISED AUGUST 2016 www.ti.com Product Folder Links: LPV511 Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated Electrical Characteristics: 12 V (continued) Unless otherwise specified, all limits are specified for TJ = 25°C, V+ = 12 V, V− = 0 V, VCM = VO = V+/2, and RL = 100 kΩ to V+/2.(1) PARAMETER TEST CONDITIONS MIN(2) TYP (3) MAX (2) UNIT (6) The Short-Circuit Test is a momentary test. See Note 3 in Absolute Maximum Ratings. (7) Slew rate is the average of the rising and falling slew rates. PSRR Power supply rejection ratio V+ = 2.7 V to 5 V, VCM = 0.5 V TJ = 25°C 72 114 TJ = –40°C to 85°C 68 V+ = 3 V to 5 V, VCM = 0.5 V TJ = 25°C 76 115 TJ = –40°C to 85°C 72 V+ = 5 V to 12 V, VCM = 0.5 V TJ = 25°C 84 117 TJ = –40°C to 85°C 80 CMVR Input common-mode voltage CMRR ≥ 50 dB V TJ = –40°C to 85°C 0 12 AVOL Large signal voltage gain Sinking, VO = 0.5 V TJ = 25°C 89 110 dB TJ = –40°C to 85°C 84 Sourcing, VO = 11.5 V TJ = 25°C 89 110 TJ = –40°C to 85°C 84 VO Output swing high VID = 100 mV TJ = 25°C 11.8 11.85 V TJ = –40°C to 85°C 11.72 Output swing low VID = −100 mV TJ = 25°C 150 200 mV TJ = –40°C to 85°C 280 ISC Output short circuit current(6) Sourcing VID = 100 mV −650 −200 µA Sinking VID = −100 mV 200 1300 IS Supply current TJ = 25°C 1.2 1.75 µA TJ = –40°C to 85°C 2.5 SR Slew rate(7) AV = 1, VO ramped from 1 V to 11 V 5.25 7 V/ms 3.1 GBW Gain bandwidth product RL = 1 MΩ, CL= 50 pF 25 kHz Phase margin RL = 1 MΩ, CL= 50 pF 52 ° en Input-referred voltage noise f = 100 Hz 320 nV/√Hz in Input-referred current noise f = 10 Hz 0.02 pA/√Hz f = 1 kHz 0.01
6.8 Typical Characteristics
At TJ = 25°C, unless otherwise specified. Figure 1. Supply Current vs Supply Voltage Figure 2. Input Offset Voltage vs Input Common Mode Figure 3. Input Offset Voltage vs Input Common Mode Figure 4. Input Offset Voltage vs Input Common Mode Figure 5. Sourcing Current vs Output Voltage Figure 6. Sinking Current vs Output Voltage
200 Ps/DIV
At TJ = 25°C, unless otherwise specified. Figure 19. Frequency Response vs CL Figure 20. Frequency Response vs CL Figure 21. Frequency Response vs CL Figure 22. Voltage Noise vs Frequency Figure 23. Noninverting Small-Signal Pulse Response Figure 24. Noninverting Large-Signal Pulse Response
At TJ = 25°C, unless otherwise specified. Figure 25. Inverting Small-Signal Pulse Response Figure 26. Inverting Large-Signal Pulse Response
Copyright © 2016, Texas Instruments Incorporated LPV511 SNOSAG7D –AUGUST 2005–REVISED AUGUST 2016 www.ti.com Product Folder Links: LPV511 Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated
7 Detailed Description
7.1 Overview
The LPV511 is a micropower operational amplifier that operates from a voltage supply range as wide as 2.7 V to 12 V with ensured specifications at 3 V, 5 V, and 12 V. The LPV511 exhibits an excellent speed-to-power ratio, drawing only 880 nA of supply current with a bandwidth of 27 kHz.
7.2 Functional Block Diagram
7.3 Feature Description
The LPV511 has a rail-to-rail input which provides more flexibility for the system designer. As can be seen from Functional Block Diagram, rail-to-rail input is achieved by using in parallel, one PNP differential pair and one NPN differential pair. When the common mode input voltage (VCM) is near V+, the NPN pair is on and the PNP pair is off. When VCM is near V−, the NPN pair is off and the PNP pair is on. When VCM is between V+ and V−, internal logic decides how much current each differential pair will get. This special logic ensures stable and low distortion amplifier operation within the entire common mode voltage range.
7.4 Device Functional Modes
7.4.1 Input Stage
Because both input stages have their own offset voltage (VOS) characteristic, the offset voltage of the LPV511 becomes a function of VCM. VOS has a crossover point at 1 V below V+. See the VOS vs VCM curve in Typical Characteristics. Caution must be taken in situations where the input signal amplitude is comparable to the VOS value and/or the design requires high accuracy. In these situations, it is necessary for the input signal to avoid the crossover point. The input bias current, IB will change in value and polarity as the input crosses the transition region. In addition, parameters such as PSRR and CMRR which involve the input offset voltage will also be affected by changes in VCM across the differential pair transition region. Differential input voltage is the difference in voltage between the noninverting (+) input and the inverting input (−) of the op amp. Due to the three series diodes across the two inputs, the absolute maximum differential input voltage is ±2.1 V. This may not be a problem to most conventional op amp designs; however, designers must avoid using the LPV511 as a comparator.
7.4.2 Output Stage
dynamic range at the output. This is particularly important when operating on low supply voltages. The LPV511 maximum output voltage swing defines the maximum swing possible under a particular output load. The LPV511 output swings 110 mV from the rail at 5-V supply with an output load of 100 kΩ.
7.4.3 Driving Capacitive Load
The LPV511 is internally compensated for stable unity gain operation, with a 27-kHz typical gain bandwidth. than 100 pF, a small series resistor at the output of the amplifier improves the phase margin (see Figure 27). were a load resistor in Figure 27, the output voltage would be divided by RISO and the load resistor. Figure 27. Resistive Isolation of Capacitive Load
8 Application and Implementation
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LPV511 is fabricated with Texas Instrument's state-of-the-art VIP50C process.
8.2 Typical Applications
8.2.1 Battery Current Sensing
RSENSE is connected to the battery directly. Figure 28. High Side Current Sensing
8.2.1.1 Design Requirements
range extends up to the positive supply.
8.2.1.2 Detailed Design Procedure
proportional to the VSENSE voltage. amplifier is at essentially the same potential as the negative sense input. noninverting input. At this point, the voltage drop across R1 now matches VSENSE.
- G = R3 / R1 (3)
8.2.1.3 Application Curve
Figure 29 shows the results of the example current sense circuit. The error after 4 V where transistor Q1 runs out of headroom and saturates, limiting the upper output swing. Figure 29. Current Sense Amplifier Results
8.2.2 Summing Amplifier
Equation 4 shows the ratio of the sum and the output voltage is defined using feedback and input resistors. Figure 30. Summing Amplifier Circuit
8.3 Dos and Don'ts
Do properly bypass the power supplies. Do add series resistence to the output when driving capacitive loads, particularly cables, Muxes and ADC inputs. the supplies. Limit the current to 1 mA or less (1 kΩ per volt).
9 Power Supply Recommendations
presented in the Electrical Characteristics: 3 V. Supply voltages larger than 13.2 V can permanently damage the device. suggested that 100 nF capacitors be placed as close as possible to the operational amplifier power supply pins. between V+ and ground, and one capacitor between V– and ground. if kilohertz or above noise is expected on the power supply lines.
10 Layout
10.1 Layout Guidelines
- The V+ pin should be bypassed to ground with a low-ESR capacitor.
- The optimum placement is closest to the V+ and ground pins.
- Take care to minimize the loop area formed by the bypass capacitor connection between V+ and ground.
- The ground pin should be connected to the PCB ground plane at the pin of the device.
- The feedback components should be placed as close to the device as possible minimizing strays.
10.2 Layout Example
Figure 31. SOT-23 Layout Example
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
LPV511 PSPICE Model, http://www.ti.com/lit/zip/snom023 TINA-TI SPICE-Based Analog Simulation Program, http://www.ti.com/tool/tina-ti DIP Adapter Evaluation Module, http://www.ti.com/tool/dip-adapter-evm TI Universal Operational Amplifier Evaluation Module, http://www.ti.com/tool/opampevm TI Filterpro Software, http://www.ti.com/tool/filterpro
11.2 Documentation Support
11.2.1 Related Documentation
- Handbook of Operational Amplifier Applications (SBOA092)
- Compensate Transimpedance Amplifiers Intuitively (SBOA055)
- Circuit Board Layout Techniques (SLOA089)
- AN-1803 Design Considerations for a Transimpedance Amplifier (SNOA515)
11.3 Community Resource
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
www.ti.com 10-Nov-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) LPV511MG/NOPB Active Production SC70 (DCK) | 5 1000 | SMALL T&R Yes SN Level-1-260C-UNLIM -40 to 85 A91 LPV511MG/NOPB.A Active Production SC70 (DCK) | 5 1000 | SMALL T&R Yes SN Level-1-260C-UNLIM -40 to 85 A91 LPV511MGX/NOPB Active Production SC70 (DCK) | 5 3000 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 85 A91 LPV511MGX/NOPB.A Active Production SC70 (DCK) | 5 3000 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 85 A91 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1
PACKAGE MATERIALS INFORMATION www.ti.com 16-Jan-2026 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION www.ti.com 16-Jan-2026 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LPV511MG/NOPB SC70 DCK 5 1000 208.0 191.0 35.0 LPV511MGX/NOPB SC70 DCK 5 3000 208.0 191.0 35.0 Pack Materials-Page 2
www.ti.com PACKAGE OUTLINE C 0.22
0.08 TYP
0.15 2.4 1.8 2X 0.65 1.3
1.1 MAX
0.1
0.0 TYP
5X 0.33 0.15 NOTE 5
0.1 C A B
0.46
0.26 TYP
0 TYP
1.3 4X 0 -12 4X 4 -15 A 2.15 1.85 B1.4 1.1 (0.9) (0.15) (0.1) SOT - 1.1 max heightDCK0005A SMALL OUTLINE TRANSISTOR 4214834/G 11/2024 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-203. 4. Support pin may differ or may not be present. 5. Lead width does not comply with JEDEC. 6. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.25mm per side 0.1 C SCALE 5.600
www.ti.com EXAMPLE BOARD LAYOUT
0.07 MAX
0.07 MIN
5X (0.95) 5X (0.4) (2.2) (1.3) 2X (0.65) (R0.05) TYP 4214834/G 11/2024 SOT - 1.1 max heightDCK0005A SMALL OUTLINE TRANSISTOR NOTES: (continued) 7. Publication IPC-7351 may have alternate designs. 8. Solder mask tolerances between and around signal pads can vary based on board fabrication site. SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:18X PKG 3 4 SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL METALSOLDER MASK OPENING NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DETAILS EXPOSED METAL
www.ti.com EXAMPLE STENCIL DESIGN (2.2) (1.3) 2X(0.65) 5X (0.95) 5X (0.4) (R0.05) TYP SOT - 1.1 max heightDCK0005A SMALL OUTLINE TRANSISTOR 4214834/G 11/2024 NOTES: (continued) 9. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 10. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 THICK STENCIL SCALE:18X SYMM PKG 3 4
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