LP8720

One Step-Down DC/DC and Five Linear Regulators with I2C Compatible Interface datasheet (Rev. B)

Document overview

• Manufacturer or author: Texas Instruments, Incorporated [SNVS575,B]
• PDF pages: 26

Technical content

1 µF 1.2V-3.3V @300 mA VIN1 VIN2 1 µF 1.2V-3.3V @300 mA VDD 1.2V-3.3V @300 mA 1 µF LDO3 1 µF 0.8V-2.85V @300 mA LDO4 LDO5 1 µF 1.2V-3.3V @300 mA LDO2 A-type LDO1 D-type LDO3 A-type LDO4 LO-type LDO5 D-type VBATT VBATT 2.2 µF2.2 µF - + LP8720 Voltage Reference Thermal Shutdown 2.2 µF LDO2 @400mA Buck 10 µF 2.2 µH SW FB GNDB VINB 10 µF VBATT 10k1.5k1.5k VSI SDA IRQ_N SCL EN DVS Serial Interface and ControlVBATT DEFSEL VBATT IDSEL GND LP8720 www.ti.com SNVS575B –JULY 2008–REVISED MAY 2013 LP8720OneStep-DownDC-DCandFiveLinearRegulatorswithI2C-CompatibleInterface Check for Samples: LP8720 1FEATURES APPLICATIONS 2• 5 Low Noise LDO’s for up to 300 mA • Cellular Handsets

• One High-Efficiency Synchronous Magnetic • Portable Hand-Held Products Buck Regulator, IOUT 400 mA DESCRIPTION– High Efficiency PFM Mode @Low IOUT The LP8720 is a multi-function, programmable Power– Auto Mode PFM/PWM Switch Management Unit, optimized for sub block power– Low Inductance 2.2 µH @ 2 MHz Clock requirement solutions. This device integrates one – Dynamic Voltage Scale Control highly efficient 400 mA step-down DC-DC converter with Dynamic Voltage Scale (DVS), five low-noise low• I2C-Compatible Interface for the Controlling of dropout (LDO) voltage regulators, and a 400 KHz I2C-Internal Registers compatible interface to allow a host controller access• 20-Bump 2.5 x 2.0 mm DSBGA Package to the internal control registers of the LP8720. Additionally, the LP8720 features programmable KEY SPECIFICATIONS power-on sequencing.
• Programmable VOUT from 0.8V to 2.3V on DC- LDO regulators provide high PSRR and low noise DC ideally suited for supplying power to both analog and digital loads. The package will be the smallest 2.5• Automatic Soft Start on DC-DC mm x 2.0 mm 20-bump DSBGA package.• 200 mV Typ Dropout Voltage at 300 mA on LDO’s
• 2% (Typ) Output Voltage Accuracy on LDO’s Typical Application Diagram Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Copyright © 2008–2013, Texas Instruments IncorporatedProducts conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Figure 1. Package Number YZR002011A A4 VBATT P Battery Input for LDO1 and all internal circuitry. E4 VINB P Battery Input for Buck. A2 VIN1 P Battery Input for LDO2 and LDO3. D1 VIN2 P Battery Input for LDO4 and LDO5. D4 GNDB G Power Ground for Buck. needed, typ 1.5 kΩ. If not in use then hard wire to GND. in use then hard-wire to GND. B3 IRQ_N DO Interrupt output, active LOW. Open Drain output, external pull-up resistor is needed, typ 10 kΩ. If not in use then hard-wire to GND or leave floating. E2 EN DI Enable. EN=LO standby. EN=HI power on. Internal pull-down resistor 500 kΩ. If not in use then hard wire to VBATT. or GND or left floating (Hi-Z) for specific application. When DEFSEL= VBATT then setup 1 is used for default voltages and startup sequence. When DEFSEL= GND then setup 2 is used for default voltages and startup sequence. When DEFSEL= floating (Hi-Z) setup 3 is used for default voltages and startup sequence. GND or left floating (Hi-Z) for specific application. When IDSEL= VBATT then slave address is 7h’7F. When IDSEL= floating (Hi-Z) then slave address is 7h’7C. When IDSEL= GND then slave address is 7h’7D.

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www.ti.com SNVS575B –JULY 2008–REVISED MAY 2013 LP8720 PIN DESCRIPTIONS(1) (continued) Pin Number Name Type Description D3 DVS DI Dynamic Voltage Scaling. When DVS=HI then Buck voltage set BUCK_V1 is in use. When DVS=LO then Buck voltage set BUCK_V2 is in use. Buck voltage set BUCK_V1 should be higher than Buck voltage set BUCK_V2. If not in use then hard wire to VBATT or GND. Device Description Operation Modes POWER-ON-RESET: After VBATT gets above POR higher threshold, the DEFSEL pin and IDSEL pin are read. All internal registers of LP8720 then are reset to the default values; after that the LP8720 goes to STANDBY mode. This process duration max is 500 µs. STANDBY: In STANDBY mode only serial interface is working and all other PMU functions are disabled – PMU is in low-power condition. In STANDBY mode the LP8720 can be (re)configured via Serial Interface. STARTUP: STARTUP sequence is defined by registers contents. STARTUP sequence starts: 1) If rising edge on EN pin. 2) After cooling down from thermal shutdown event if EN = HI. It is not recommended to write to LP8720 registers during startup. If doing so then current startup sequence may become undefined. IDLE: PMU will enter into IDLE mode (normal operating mode) after end of startup sequence. In IDLE mode all LDO’s and BUCK can be enabled/disabled via Serial Interface. Also in IDLE mode LP8720 can be (re)configured via Serial Interface. SHUTDOWN: SHUTDOWN sequence is “reverse order of startup sequence,”and this is defined by registers contents. SHUTDOWN starts: 1) If falling edge on EN pin. 2) If temperature exceeds thermal shutdown threshold TSD +160°C. It is not recommended to write to LP8720 registers during SHUTDOWN. If doing so then current SHUTDOWN sequence may become undefined. Additional Functions SLEEP: If sum of all LDOs' load currents and BUCK load current is no higher than 5 mA , the user can put PMU to SLEEP. In SLEEP PMU GND current is minimized, and LDO’s and BUCK cannot be loaded with bigger current. There are 2 possibilities to use SLEEP: 1) Control via Serial Interface. 2) Control by DVS pin. Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: LP8720

1) Control via Serial Interface. tBON 150 µs – Reference and bias turn ON. Min 100 µs max 200 µs. tS 25 µs – time step. Time step accuracy is defined by OSC frequency accuracy. registers are not rewritten via Serial Interface. than 35 µs. For details please see LDO’s and BUCK Electrical Specifications. changed via Serial interface, then LDO5 and BUCK are disabled with no delay from falling edge on EN pin. (4) At this time point registers 0x09 and 0x0C are reset to POR default values. (5) At this time point registers 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07 and 0x08 are reset to POR default values. Figure 2. Startup Sequence if DEFSEL=VBATT or DEFSEL=Hi-Z

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tBON 150 µs – Reference and bias turn ON. Min 100 µs max 200 µs. tS 25 µs – time step. Time step accuracy is defined by OSC frequency accuracy. registers are not rewritten via Serial Interface. than 35 µs. For details please see LDO’s and BUCK Electrical Specifications. are disabled with no delay from falling edge on EN-pin. (4) At this time point registers 0x09 and 0x0C are reset to POR default values. (5) At this time point registers 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07 and 0x08 are reset to POR default values. Figure 3. Startup Sequence if DEFSEL=GND Table 1. Startup Sequence(1) VBATT LDO1, 2, 3, 4 enable same time. In reverse order of startup sequence. LDO5 and BUCK enable via Serial Interface. GND LDO3 enable. In reverse order of startup sequence. LDO1, 2, 4, 5 and BUCK enable via Serial Interface . Hi-Z LDO1, 2, 3, 4 enable same time. In reverse order of startup sequence. LDO5 and BUCK enable via Serial Interface. (1) When IDSEL= VBATT then slave address is 7h’7F. When IDSEL= floating (Hi-Z) then slave address is 7h’7C. When IDSEL= GND then slave address is 7h’7D.

Table 2. Default Output Voltages(1)(2) (1) BUCK voltage is 1.2V if DVS=LO and 1.3V if DVS=HI. Table 3. Control Register Map(1) (1) When IDSEL= VBATT then slave address is 7h’7F. When IDSEL= floating (Hi-Z) then slave address is 7h’7C. When IDSEL= GND then slave address is 7h’7D. (2) Registers STATUS_BITS 0x0A and INTERRUPT_BITS 0x0B are read only.

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Table 4. Register 0x00

• DVS = HI then BUCK_V1[4:0]
• DVS = LO then BUCK_V2[4:0] 0 – Serial interface control:
• DVS_V2/V1 = 1 then BUCK_V1[4:0]
• DVS_V2/V1 = 0 then BUCK_V2[4:0] EXT_SLEEP_CONTROL 1 – DVS-pin control:
• DVS = HI then normal
• DVS = LO then SLEEP 0 – Serial interface control:
• SLEEP_MODE = 0 then normal
• SLEEP_MODE = 1 then SLEEP SHORT_TIMESTEP 1 – time step tS = 25 µs 0 – time step tS= 50 µs By request time step 100 µs/200 µs is available.

Table 5. Registers 0x01 – 0x07 BUCK_V1[4:0] should be higher (or equal) than BUCK_V2[4:0]. LDO5_T[2:0] For proper startup operation “111 NO startup”should have corresponding bit in ENABLE_BITS registerBUCK_T[2:0] 0x08 set to 0 (disable). 0 – Buck works in automatic PFM/PWM selection mode.

Table 6. Register 0x08 LDO4_EN LDO5_EN BUCK_EN 1 – During next startup sequence will be enabled. effect. have corresponding enable bit 0 (disable). Table 7. Register 0x09 Thermal Shutdown after cooling down if EN-pin is High. 1 – No change to registers – registers content stays the same as before Thermal Shutdown. 0 – Reset registers to default values before startup from Thermal Shutdown. Table 8. Register 0x0A (Read Only) TSD 1 – device is in Thermal Shutdown. 0 – device is NOT in Thermal Shutdown . TSD_EW 1 – device temperature is higher than Thermal Shutdown Early Warning threshold. 0 – device temperature is lower than Thermal Shutdown Early Warning threshold. Table 9. Register 0x0B (Read Only) Table 10. Register 0x0C The LP8720 has an internal reference block creating all necessary references and biasing for all blocks. There is an internal oscillator giving clock to the bucks and to logic control.

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www.ti.com SNVS575B –JULY 2008–REVISED MAY 2013 Thermal Shutdown The Thermal Shutdown (TSD) function monitors the chip temperature to protect the chip from temperature damage caused eg. by excessive power dissipation. The temperature monitoring function has two threshold values, TSD and TSD_EW, that result in protective actions. When TSD_EW +125ºC is exceeded, IRQ_N is set to low, and “1” is written to the TSD_EW bit in both the STATUS register and in INTERRUPT register. If the temperature exceeds TSD +160ºC, then PMU initiates Emergency Shutdown. The POWER-UP operation after Thermal Shutdown can be initiated only after the chip has cooled down to the +115ºC threshold. Parameter Typ Unit TSD(1) 160 °C TSD_EW(1) 125 °C TSD_EW Hysteresis(1) 10 °C (1) Ensured by design. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Absolute Maximum Ratings(1)(2)(3) VBATT = VINB, VBATT -0.3V to +6V VIN1, VIN2 -0.3V to VBATT+0.15V, max 6V All other pins -0.3V to VBATT+0.3V, max 6V Junction Temperature (TJ-MAX) 150ºC Storage Temperature -40 to 150ºC Maximum Continuous Power Dissipation, PD-MAX (4) 1.75 W 2 kV HBM ESD(5) 200V MM (1) Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the device is specified. Operating Ratings do not imply ensured performance limits. For specified performance limits and associated test conditions, see the Electrical Characteristics tables. (2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications. (3) All voltages are with respect to the potential at the GND pin. (4) The Absolute Maximum power dissipation depends on the ambient temperature and can be calculated using the formula P = (TJ – TA)/θJA, (eq. 1) where TJ is the junction temperature, TA is the ambient temperature, and θJA is the junction-to-ambient thermal resistance. The 1.75-W rating appearing under Absolute Maximum Ratings results from substituting the Absolute Maximum junction temperature, 150ºC for TJ, 70ºC for TA, and 45°C/W for θJA. More power can be dissipated safely at ambient temperatures below 70°C. Less power can be dissipated safely at ambient temperatures above 70°C. The Absolute Maximum power dissipation can be increased by 22 mW for each degree below 70°C, and it must be de-rated by 22 mW for each degree above 70ºC. (5) The human-body model is 100 pF discharged through 1.5 kΩ. The machine model is a 200-pF capacitor discharged directly into each pin, MIL-STD-883 3015.7. Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: LP8720

SNVS575B –JULY 2008–REVISED MAY 2013 www.ti.com Operating Ratings(1)(2) VBATT = VINB, VBATT 2.7 to 4.5V VIN1, VIN2 2.5V to VBATT All input-only pins 0V to VBATT Junction Temperature (TJ) -40 to 125ºC Ambient Temperature (TA) -40 to 85ºC Maximum Power Dissipation (TA = 70ºC)(3) 1.2 W (1) Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the device is specified. Operating Ratings do not imply ensured performance limits. For specified performance limits and associated test conditions, see the Electrical Characteristics tables. (2) All voltages are with respect to the potential at the GND pin. (3) Like the Absolute Maximum power dissipation, the maximum power dissipation for operation depends on the ambient temperature. The 1.2W rating for DSBGA 20 appearing under Operating Ratings results from substituting the maximum junction temperature for operation, 125°C, for TJ, 70°C for TA, and 45°C/W for θJA into (eg. 1) above. More power can be dissipated at ambient temperatures below 70°C. Less power can be dissipated at ambient temperatures above 70°C. The maximum power dissipation for operation can be increased by 22mW for each degree below 70°C, and it must be de-rated by 22 mW for each degree above 70°C. Thermal Properties(1) Junction-to-Ambient Thermal Resistance (θJA) (Jedec Standard Thermal PCB) 45°C/W 20-bump DSBGA package (1) Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power dissipation exists, special care must be paid to thermal dissipation issues in board design. Current Consumption Unless otherwise noted, VVBATT = VVINB =VVIN1 = VVIN2 = 3.6V, GND = GNDB = 0V, CVBATT = CVIN1= CVIN2 = 2.2 µF, CVINB = 10 µF. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, TJ= -40 to +125°C(1) Limit Parameter Test Conditions Typ Units Min Max IQ(STANDBY) Battery Standby Current VBATT = 3.6V 0.7 5 µA IQ(SLEEP) Battery Current in SLEEP BUCK and all LDO’s enabled 190 270 µAMode @ 0 load IQ(SLEEP) Battery Current in SLEEP LDO1, LDO2, LDO3 and LDO4 enabled 170 µAMode @ 0 load IQ(SLEEP) Battery Current in SLEEP LDO3 enabled 100 150 µAMode @ 0 load IQ(SLEEP) Battery Current in SLEEP LDO1 and BUCK enabled 100 µAMode @ 0 load IQ Battery Current @ 0 load BUCK and all LDO’s enabled 270 400 µA IQ Battery Current @ 0 load LDO1, LDO2, LDO3 and LDO4 enabled 230 µA IQ Battery Current @ 0 load LDO3 enabled 120 200 µA IQ Battery Current @ 0 load LDO1 and BUCK enabled 120 µA (1) All limits are specified. All electrical characteristics having room-temperature limits are tested during production with TJ = 25°C. All hot and cold limits are ensured by correlating the electrical characteristics to process and temperature variations and applying statistical process control.

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www.ti.com SNVS575B –JULY 2008–REVISED MAY 2013 Power-On Reset(1) Unless otherwise noted, VVBATT = VVINB = VVIN1 =VVIN2 = 3.6V, GND = GNDB = 0V, CVBATT =CVIN1= CVIN2=2.2 µF, CVINB = 10 µF. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, TJ= -40 to +125°C. (1) Limit Parameter Test Conditions Typ Units Min Max VPOR_HI POR higher threshold VVBATT rising 2.2 2.0 2.4 V VPOR_LO POR lower threshold VVBATT falling(2) 1.4 V (1) All limits are specified. All electrical characteristics having room-temperature limits are tested during production with TJ = 25°C. All hot and cold limits are ensured by correlating the electrical characteristics to process and temperature variations and applying statistical process control. (2) Ensured by design. Logic and Control Unless otherwise noted, VVBATT = VVINB = VVIN1 = VVIN2 = 3.6V, GND=GNDB=0V, CVBATT =CVIN1= CVIN2 = 2.2 µF, CVINB = 10 µF. Typical values and limits appearing in normal type apply for TJ=25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, TJ= -40 to +125°C(1) Limit Parameter Test Conditions Typ Units Min Max Logic and Control Inputs VIL Input Low Level EN, SCL, SDA, DVS 0.4 V VIH Input High Level EN, SCL, SDA, DVS 1.2 V IIL Input Current All logic inputs -5 +5 µA RPD Pull-Down Resistance From EN to GND 550 300 900 kΩ Logic and Control Outputs VOL Output Low Level IRQ_N, SDA, IOUT = 2 mA 0.4 V VOH Output High Level IRQ_N, SDA are Open drain outputs. NA µA (1) All limits are specified. All electrical characteristics having room-temperature limits are tested during production with TJ = 25°C. All hot and cold limits are ensured by correlating the electrical characteristics to process and temperature variations and applying statistical process control. Buck Converter Unless otherwise noted, VVBATT = VVINB = VVIN1 = VVIN2 = 3.6V, GND = GNDB = 0V, CVBATT = CVIN1 = CVIN2 = 2.2 µF, CVINB = 10 µF. Typical values and limits appearing in normal type apply for TJ=25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, TJ= -40 to +125°C(1)(2) Limit Parameter Test Conditions Typ Units Min Max VVOUT,PFM Output Voltage regulation in See(3) PFM mode relative to 1.5% regulation in PWM mode VOUT Line Regulation 3.0V ≤ VIN ≤ 4.5V 0.14 %/VIOUT = 10 mA VOUT Load Regulation 100mA ≤ IOUT ≤ 300mA 0.09 %/mA ILIM_PWM Switch Peak Current Limit PWM Mode @ 400 mA 900 500 mA3.0V ≤ VIN ≤ 4.5V RDSON(P) P channel FET on resistance VIN = 3.6V, ID = 100 mA 310 500 mΩ RDSON(N) N channel FET on resistance 160 300 mΩ (1) All limits are specified. All electrical characteristics having room-temperature limits are tested during production with TJ = 25°C. All hot and cold limits are ensured by correlating the electrical characteristics to process and temperature variations and applying statistical process control. (2) Ensured for output voltages no less than 1.0V (3) Ensured by design. Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: LP8720

Table 11. Buck Output Voltage Programming in Register 0x06 and 0x07 Buck1 output voltage can be programmed via the selection of the external feedback resistor network.

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C1 = 1 (2 x /c53 x RFB1 x 45 x 103) VOUT = VFB x R FB1 R FB2 1+/ca9 /ca7 /ca9 /ca7 LP8720 www.ti.com SNVS575B –JULY 2008–REVISED MAY 2013 The formula for output voltage selection is

• VOUT – output voltage
• VFB – feedback voltage (0.5V) (1) For any out voltage greater than or equal to 0.8V a transfer function zero should be added by the addition of a capacitor C1. The formula for calculation of C1 is: (2) For recommended component values see the table below. VOUT [V] RFB1 [kΩ] RFB2 [kΩ] C1 [pF] L [µH] COUT [µF] 1.0 200 200 18 2.2 10 1.2 280 200 12 2.2 10 1.4 360 200 10 2.2 10 1.5 360 180 10 2.2 10 1.6 440 200 8.2 2.2 10 1.85 540 200 6.8 2.2 10 LDO’s There are, all together, 5 LDO’s in the LP8720 grouped as:
• A-type LDO’s (LDO2, 3)
• D-type LDO’s (LDO1, 5)
• LO-type LDO (LDO 4) The A-type LDO’s are optimized for supplying of analog loads and have ultra low noise (15 µVRMS) and excellent PSRR (70 dB) performance. The D-type LDO’s are optimized for good dynamic performance to supply different fast changing (digital) loads. The LO-type LDO is optimized for low output voltage and for good dynamic performance to supply different fast changing (digital) loads. All LDO’s can be programmed through serial interface for 32 different output voltage values, which are summarized in the Ouput Voltage Programming tables below. At the PMU power on, LDO’s start up according to the selected startup sequence, and the default voltages after startup sequence depend on startup setup. See section Power-On and Power-Off Sequences for details. For stability all LDO’s have to be connected to output an external capacitor COUT with recommended value of 1 µF. It is important to select the type of capacitor which capacitance will in no case (voltage, temperature, etc) be outside of limits specified in the LDO Electrical Characteristics. Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 13 Product Folder Links: LP8720

Table 12. LDO1, 2, 3 and 5 Output Voltage Programming Table 13. LDO4 Output Voltage Programming

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www.ti.com SNVS575B –JULY 2008–REVISED MAY 2013 A-Type LDO Electrical Characteristics Unless otherwise noted, VVBATT = VVINB = VVIN1 = VVIN2 = 3.6V, GND = GNDB = 0V, CVBATT = CVIN1 = CVIN2 = 2.2 µF, CVINB = 10 µF. Typical values and limits appearing in normal type apply for TJ=25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, TJ= -40 to +125°C(1) Limit Parameter Test Conditions LDO# Typ Units Min Max VOUT Output Voltage Accuracy IOUT = 1mA, VOUT = 2.85V -2% +2% 2,3 -3% +3% ISC Output Current Limit VOUT = 0V 2,3 600 mA VDO Dropout Voltage IOUT = IMAX(2) 2,3 200 400 mV ΔVOUT Line Regulation VOUT + 0.5V ≤ VIN ≤ 4.5V 2,3 1 mVIOUT = IMAX Load Regulation 1 mA ≤ IOUT ≤ IMAX 2,3 5 mV eN Output Noise Voltage 10Hz ≤ f ≤ 100kHz COUT = 1 µF(3) 2,3 15 µVRMS PSRR Power Supply Ripple f = 10 kHz, COUT = 1 µF, IOUT = 20 2,3 70 dBRejection Ratio mA(3) tstartup Startup Time from Shutdown COUT = 1 µF, IOUT = IMAX (3) 2,3 35 µs VTransient Startup Transient Overshoot COUT = 1 µF, IOUT = IMAX (3) 2,3 30 mV COUT External output capacitance 2,3 1.0 0.5 20 µFfor stability (1) All limits are specified. All electrical characteristics having room-temperature limits are tested during production with TJ = 25°C. All hot and cold limits are ensured by correlating the electrical characteristics to process and temperature variations and applying statistical process control. (2) Dropout voltage is the input-to-output voltage difference at which the output voltage is 100mV below its nominal value. This specification does not apply in cases it implies operation with an input voltage below the 2.5V minimum appearing under Operating Ratings. For example, this specification does not apply for devices having 1.5V outputs because the specification would imply operation with an input voltage at or about 1.5V. (3) Ensured by design. D-Type and LO-Type LDO Electrical Characteristics Unless otherwise noted, VVBATT = VVINB = VVIN1 = VVIN2 = 3.6V, GND = GNDB = 0V, CVBATT = CVIN1 = CVIN2 = 2.2 µF, CVINB = 10 µF. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, TJ= -40 to +125°C(1) Limit Parameter Test Conditions LDO# Typ Units Min Max VOUT Output Voltage Accuracy IOUT = 1mA, VOUT = 2.85V -2% +2% 1,5 -3% +3% IOUT = 1mA, VOUT = 1.20V -2% +2% -3% +3% IOUT = 1mA, VOUT = 2.60V -3% +3% -4% +4% ISC Output Current Limit VOUT = 0V 1,4,5 600 mA VDO Dropout Voltage IOUT = IMAX (2) 1,4,5 190 400 mV ΔVOUT Line Regulation VOUT + 0.5V ≤ VIN ≤ 4.5V 1,4,5 2 mVIOUT = IMAX Load Regulation 1mA ≤ IOUT ≤ IMAX 1,4,5 5 mV eN Output Noise Voltage 10Hz ≤ f ≤ 100kHz, COUT = 1 µF(3) 1,4,5 100 µVRMS (1) All limits are specified. All electrical characteristics having room-temperature limits are tested during production with TJ = 25°C. All hot and cold limits are ensured by correlating the electrical characteristics to process and temperature variations and applying statistical process control. (2) Dropout voltage is the input-to-output voltage difference at which the output voltage is 100mV below its nominal value. This specification does not apply in cases it implies operation with an input voltage below the 2.5V minimum appearing under Operating Ratings. For example, this specification does not apply for devices having 1.5V outputs because the specification would imply operation with an input voltage at or about 1.5V. (3) Ensured by design. Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 15 Product Folder Links: LP8720

SNVS575B –JULY 2008–REVISED MAY 2013 www.ti.com D-Type and LO-Type LDO Electrical Characteristics (continued) Unless otherwise noted, VVBATT = VVINB = VVIN1 = VVIN2 = 3.6V, GND = GNDB = 0V, CVBATT = CVIN1 = CVIN2 = 2.2 µF, CVINB = 10 µF. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, TJ= -40 to +125°C(1) Limit Parameter Test Conditions LDO# Typ Units Min Max PSRR Power Supply Ripple f =10 kHz, COUT = 1 µF, IOUT = 20 1,4,5 55 dBRejection Ratio mA(3) tstartup Startup Time from Shutdown COUT = 1 µF, IOUT = IMAX(3) 1,4,5 35 µs VTransient Startup Transient Overshoot COUT = 1µF, IOUT = IMAX(3) 1,4,5 30 mV COUT External output capacitance 1,4,5 1.0 0.5 20 µFfor stability Serial Interface Unless otherwise noted, VVBATT = VVINB = VVIN1 = VVIN2 = 3.6V, GND = GNDB = 0V, CVBATT = CVIN1 = CVIN2 = 2.2 µF, CVINB = 10 µF. Typical values and limits appearing in normal type apply for TJ= 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, TJ= -40 to +125°C(1)(2) Limit UnitParameter Test Conditions Typ sMin Max fCLK Clock Frequency 400 kHz tBF Bus-Free Time between START and STOP 1.3 µs tHOLD Hold Time Repeated START Condition 0.6 µs tCLK-LP CLK Low Period 1.3 µs tCLK-HP CLK High Period 0.6 µs tSU Set-Up Time Repeated START Condition 0.6 µs tDATA-HOLD Data Hold Time 50 ns tDATA-SU Data Set-Up Time 100 ns tSU Set-Up Time for STOP Condition 0.6 µs tTRANS Maximum Pulse Width of Spikes that Must Be Suppressed by 50 nsthe Input Filter of Both DATA and CLK Signals (1) All limits are specified. All electrical characteristics having room-temperature limits are tested during production with TJ = 25°C. All hot and cold limits are ensured by correlating the electrical characteristics to process and temperature variations and applying statistical process control. (2) Ensured by design.

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transferred, and the acknowledge signal sent by the receiving device. Figure 6. Bus Acknowledge Cycle signal after every byte received. There is one exception to the “acknowledge after every byte”rule. acknowledge clock pulse (generated by the master), but the SDA line is not pulled down.

• When IDSEL= VBATT then slave address is 7h’7F.
• When IDSEL= floating (Hi-Z) then slave address is 7h’7C.
• When IDSEL= GND then slave address is 7h’7D. Before any data is transmitted, the master transmits the address of the slave being addressed. The slave device should send an acknowledge signal on the SDA line, once it recognizes its address. The slave address is the first seven bits after a Start Condition. The direction of the data transfer (R/W) depends on the bit sent after the slave address — the eighth bit. When the slave address is sent, each device in the system compares this slave address with its own. If there is a match, the device considers itself addressed and sends an acknowledge signal. Depending upon the state of the R/W bit (1:read, 0:write), the device acts as a transmitter or a receiver. Control Register Write Cycle
• Master device generates start condition.
• Master device sends slave address (7 bits) and the data direction bit (r/w = '0').
• Slave device sends acknowledge signal if the slave address is correct.
• Master sends control register address (8 bits).
• Slave sends acknowledge signal.
• Master sends data byte to be written to the addressed register.

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• Slave sends acknowledge signal.
• If master will send further data bytes the control register address will be incremented by one after acknowledge signal.
• Write cycle ends when the master creates stop condition. Control Register Read Cycle
• Master device generates a start condition.
• Master device sends slave address (7 bits) and the data direction bit (r/w = '0').
• Slave device sends acknowledge signal if the slave address is correct.
• Master sends control register address (8 bits).
• Slave sends acknowledge signal.
• Master device generates repeated start condition.
• Master sends the slave address (7 bits) and the data direction bit (r/w = “1”).
• Slave sends acknowledge signal if the slave address is correct.
• Slave sends data byte from addressed register.
• If the master device sends acknowledge signal, the control register address will be incremented by one. Slave device sends data byte from addressed register.
• Read cycle ends when the master does not generate acknowledge signal after data byte and generates stop condition. Address Mode Data Read <Start Condition> <Slave Address><r/w = ‘0’>[Ack] <Register Addr.>[Ack] <Repeated Start Condition> <Slave Address><r/w = ‘1’>[Ack] [Register Data]<Ack or NAck> … additional reads from subsequent register address possible <Stop Condition> Data Write <Start Condition> <Slave Address><r/w = ‘0’>[Ack] <Register Addr.>[Ack] <Register Data>[Ack] … additional writes to subsequent register address possible <Stop Condition> < > Data from master [ ] Data from slave Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 19 Product Folder Links: LP8720

(7 bits) '0' A A Control Register Add. (7 bits) '0' A A A PControl Register Add. Figure 7. Register Write Format Figure 8. Register Read Format

20 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated

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REVISION HISTORY

Changes from Revision A (May 2013) to Revision B Page Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 21 Product Folder Links: LP8720

www.ti.com 11-Nov-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) LP8720TLE/NOPB Active Production DSBGA (YZR) | 20 250 | SMALL T&R Yes SNAGCU Level-1-260C-UNLIM -40 to 125 8720 LP8720TLE/NOPB.A Active Production DSBGA (YZR) | 20 250 | SMALL T&R Yes SNAGCU Level-1-260C-UNLIM -40 to 125 8720 LP8720TLX/NOPB Active Production DSBGA (YZR) | 20 3000 | LARGE T&R Yes SNAGCU Level-1-260C-UNLIM -40 to 125 8720 LP8720TLX/NOPB.A Active Production DSBGA (YZR) | 20 3000 | LARGE T&R Yes SNAGCU Level-1-260C-UNLIM -40 to 125 8720 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 9-Aug-2022 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 9-Aug-2022 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LP8720TLE/NOPB DSBGA YZR 20 250 208.0 191.0 35.0 LP8720TLX/NOPB DSBGA YZR 20 3000 208.0 191.0 35.0 Pack Materials-Page 2

www.ti.com TLA20XXX (Rev D) 0.600±0.075 D E A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994. B. This drawing is subject to change without notice. 4215053/A 12/12 NOTES: D: Max = E: Max = 2.49 mm, Min = 1.99 mm, Min = 2.43 mm 1.93 mm

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