LP211

LP211, LP311 datasheet (Rev. D)

Document overview

• Manufacturer or author: Texas Instruments, Incorporated [SLCS003,D]
• PDF pages: 14

Technical content

LP211, LP311 LOW-POWER DIFFERENTIAL COMPARATORS WITH STROBES SLCS003D − JUNE 1987 − REVISED SEPTEMBER 2003 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068Low Power Drain . . . 900 μW Typical With 5-V Supply /C0068Operates From ±15 V or From a Single Supply as Low as 3 V /C0068Output Drive Capability of 25 mA /C0068Emitter Output Can Swing Below Negative Supply /C0068Response Time . . . 1.2 μs Typ /C0068Low Input Currents: Offset Current ...2 n A T y p Bias Current . . . 15 nA Typ /C0068Wide Common-Mode Input Range: −14.5 V to 13.5 V Using ±15-V Supply /C0068Offset Balancing and Strobe Capability /C0068Same Pinout as LM211, LM311 /C0068Designed To Be Interchangeable With Industry-Standard LP311 description/ordering information The LP211 and LP311 devices are low-power versions of the industry-standard LM211 and LM311 devices. They take advantage of stable, high-value, ion-implanted resistors to perform the same function as the LM311 series, with a 30:1 reduction in power consumption, but only a 6:1 slowdown in response time. They are well suited for battery-powered applications and all other applications where fast response times are not needed. They operate over a wide range of supply voltages, from ±18 V down to a single 3-V supply with less than 300-μA current drain, but are still capable of driving a 25-mA load. The LP211 and LP311 are quite easy to apply free of oscillation if ordinary precautions are taken to minimize stray coupling from the output to either input or to the trim pins. In addition, offset balancing is available to minimize input offset voltage. Strobe capability also is provided to turn off the output (regardless of the inputs) by pulling the strobe pin low. The LP211 is characterized for operation from −25°C to 85°C. The LP311 is characterized for operation from 0°C to 70°C.

ORDERING INFORMATION

AT 25°C PACKAGE† ORDERABLE PART NUMBER TOP-SIDE MARKING PDIP (P) Tube of 50 LP311P LP311P 0°Ct o7 0°C 75m V SOIC (D) Tube of 75 LP311D LP311−0°C to 70°C 7.5 mV SOIC (D) Reel of 2500 LP311DR LP311 SOP (PS) Reel of 2000 LP311PSR L311 25°Ct o8 5°C 75m V SOIC (D) Tube of 75 LP211D LP211−25°C to 85°C 7.5 mV SOIC (D) Reel of 2500 LP211DR LP211 † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Copyright © 2003, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. EMIT OUT IN+ IN− VCC− VCC+ COL OUT BAL/STRB BALANCE LP211 ...D P ACKAGE LP311 . . . D, P, OR PS PACKAGE (TOP VIEW)

LP211, LP311 LOW-POWER DIFFERENTIAL COMPARATORS WITH STROBES SLCS003D − JUNE 1987 − REVISED SEPTEMBER 2003

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

IN− BAL/STRB BALANCE absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the recommended operating conditions section of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values, unless otherwise noted, are with respect to the midpoint between V CC+ and VCC−. 2. Differential input voltages are at IN+ with respect to IN−. 3. The magnitude of the input voltage must never exceed the magnitude of the supply voltage of ±15 V, whichever is less. 4. The output may be shorted to ground or to either power supply. 5. Maximum power dissipation is a function of T J(max), θJA, and TA. The maximum allowable power dissipation at any allowable ambient temperature is PD = (TJ(max) − TA)/θJA. Operating at the absolute maximum TJ of 150°C can affect reliability. 6. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions MIN MAX UNIT (|VCC±| ≤ 15 V) Input voltage VCC− + 0.5 VCC+ − 1.5 V VCC+ − VCC− Supply voltage 3.5 30 V

LP211, LP311 LOW-POWER DIFFERENTIAL COMPARATORS WITH STROBES SLCS003D − JUNE 1987 − REVISED SEPTEMBER 2003 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics at specified free-air temperature, VCC± = ±15 V (unless otherwise noted) PARAMETER TEST CONDITIONS TA MIN TYP† MAX UNIT V Input offset voltage RS 100 k Ω See Note 7 25°C 2 7.5 mVVID Input offset voltage RS < 100 k Ω, See Note 7 Full range 10 mV VID < −10 mV, IOL = 25 mA, 25°C 04 15VID < 10 mV, See Note 8 IOL = 25 mA, 25°C 0.4 1.5 VOL Low-level output voltage VCC = 4.5 V, V <1 0 m V VCC− = 0, I 16m A Full range 01 04 V VID < −10 mV, See Note 8 IOL = 1.6 mA, Full range 0.1 0.4 I Input offset current See Note 7 25°C 2 25 nAIIO Input offset current See Note 7 Full range 35 nA I Input bias current 25°C 15 100 nAIIB Input bias current Full range 150 nA Low level strobe current V(strobe) = 0.3 V, VID < −10 mV, 25°C 100 300 ALow-level strobe current V(strobe) = 0.3 V, See Note 9 VID < 10 mV, 25°C 100 300 μA IO(off) Output off-state current VID > 10 mV, VCE = 35 V 25°C 0.2 100 nA A Large-signal differential-voltage R 5k Ω 25°C 40 100 V/mVAVD Large signal differential voltage amplification RL = 5 kΩ 25°C 40 100 V/mV ICC+ Supply current from VCC+ VID = −50 mV, RL = ∞ Full range 150 300 μA ICC− Supply current from VCC− VID = 50 mV, RL = ∞ Full range − 80 − 180 μA † All typical values are at VCC± = ±15 V, TA = 25°C. NOTES: 7. The offset voltages and offset currents given are the maximum values required to drive the output within 1 V of either supply with a 1-mA load. Thus, these parameters define an error band and take into account the worst-case effects of voltage gain and input impedance. 8. Voltages are with respect to EMIT OUT and V CC− tied together. 9. The strobe should not be shorted to ground; it should be current driven at 100 μA to 300 μA. switching characteristics, VCC± = ±5 V, TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS TYP UNIT Response time See Note 10 1.2 μs NOTE 10: The response time is specified for a 100-mV input step with 5-mV overdrive.

4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

pins should be shorted together. Figure 1. Offset Balancing Figure 2. Strobing

www.ti.com 11-Nov-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) LP211D Active Production SOIC (D) | 8 75 | TUBE Yes NIPDAU Level-1-260C-UNLIM -25 to 85 LP211 LP211D.A Active Production SOIC (D) | 8 75 | TUBE Yes NIPDAU Level-1-260C-UNLIM -25 to 85 LP211 LP211DR Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -25 to 85 LP211 LP211DR.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -25 to 85 LP211 LP211DRG4 Active Production SOIC (D) | 8 2500 | LARGE T&R - Call TI Call TI -25 to 85 LP311D Active Production SOIC (D) | 8 75 | TUBE Yes NIPDAU Level-1-260C-UNLIM 0 to 70 LP311 LP311D.A Active Production SOIC (D) | 8 75 | TUBE Yes NIPDAU Level-1-260C-UNLIM 0 to 70 LP311 LP311DR Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 LP311 LP311DR.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 LP311 LP311P Active Production PDIP (P) | 8 50 | TUBE Yes NIPDAU N/A for Pkg Type 0 to 70 LP311P LP311P.A Active Production PDIP (P) | 8 50 | TUBE Yes NIPDAU N/A for Pkg Type 0 to 70 LP311P LP311PE4 Active Production PDIP (P) | 8 50 | TUBE - Call TI Call TI 0 to 70 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Addendum-Page 1

www.ti.com 11-Nov-2025 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 10-Aug-2026 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 10-Aug-2026 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LP211DR SOIC D 8 2500 353.0 353.0 32.0 LP311DR SOIC D 8 2500 353.0 353.0 32.0 Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 10-Aug-2026 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) LP211D D SOIC 8 75 507 8 3940 4.32 LP211D.A D SOIC 8 75 507 8 3940 4.32 LP311D D SOIC 8 75 507 8 3940 4.32 LP311D.A D SOIC 8 75 507 8 3940 4.32 LP311P P PDIP 8 50 506 13.97 11230 4.32 LP311P.A P PDIP 8 50 506 13.97 11230 4.32 Pack Materials-Page 3

www.ti.com PACKAGE OUTLINE C .228-.244 TYP [5.80-6.19] .069 MAX [1.75] 6X .050 [1.27] 8X .012-.020 [0.31-0.51] .150 [3.81] .005-.010 TYP [0.13-0.25] 0 - 8 .004-.010 [0.11-0.25] .010 [0.25].016-.050 [0.41-1.27] 4X (0 -15 ) A .189-.197 [4.81-5.00] NOTE 3 B .150-.157 [3.81-3.98] NOTE 4 4X (0 -15 ) (.041) [1.04] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. 1 8 .010 [0.25] C A B PIN 1 ID AREA SEATING PLANE .004 [0.1] C SEE DETAIL A DETAIL A TYPICAL SCALE 2.800

www.ti.com EXAMPLE BOARD LAYOUT .0028 MAX [0.07] ALL AROUND .0028 MIN [0.07] ALL AROUND (.213) [5.4] 6X (.050 ) [1.27] 8X (.061 ) [1.55] 8X (.024) [0.6] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METAL SOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS EXPOSED METAL OPENING SOLDER MASK METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SYMM 4 5 SEE DETAILS SYMM

www.ti.com EXAMPLE STENCIL DESIGN 8X (.061 ) [1.55] 8X (.024) [0.6] 6X (.050 ) [1.27] (.213) [5.4] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X SYMM SYMM 4 5

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