LMR61428 Low Input Voltage, Step-Up DC-DC Converter datasheet (Rev. A)
Document overview
- Manufacturer or author: Texas Instruments, Incorporated [SNVS815,A]
- PDF pages: 22
Technical content
EFFICIENCY (%) IOUT (A) Vin = 3.0V Vin = 3.2V Vin = 3.4V Vin = 3.6V Vin = 3.8V Vin = 4.0V EFFICIENCY (%) IOUT (A) Vin = 2.0V Vin = 2.2V Vin = 2.5V Vin = 2.80 LMR61428 www.ti.com SNVS815A –JUNE 2012–REVISED APRIL 2013 LMR61428SIMPLESWITCHER® 14Vout,2.85AStep-UpVoltageRegulatorinVSSOP Check forSamples: LMR61428 1FEATURES DESCRIPTION The LMR61428 is a step-up DC-DC switching 23• 1.2Vto14V InputVoltage regulatorforbattery-poweredand low inputvoltage• AdjustableOutput Voltageup to14V systems thatcan achieveefficienciesup to 90%. It
- Switch Currentup to2.85A has a wide inputvoltagerangefrom1.2V to14V and a possibleregulatedoutputvoltagerangeof1.24V to• Up to2 MHz SwitchingFrequency 14V. Ithas an internal0.17Ω N-Channel MOSFET• Low Shutdown Iq,<1µA power switch.
- Cycle-by-CycleCurrentLimiting The highswitchingfrequencyof up to 2MHz of the• VSSOP Packaging (3.0x 5.0x 1.09mm) LMR61428 allowsfortinysurfacemount inductors
- WEBENCH ® Enabled and capacitors.Because oftheuniqueconstant-duty- cyclegated oscillatortopologyveryhighefficiencies are realizedover a wide load range. The supplyPERFORMANCE BENEFITS currentisreduced to 80µA because of the BiCMOS• ExtremelyEasy toUse process technology.In the shutdown mode, the
- TinyOverallSolutionReduces System Cost supplycurrentislessthan2.5µA. The LMR61428 is availableina VSSOP-8 package.
APPLICATIONS
- Boost/SEPIC Conversions from 3.3V,5V,and 12V
- Space ConstrainedApplications
- LCD Displays
- LED Applications System Performance Efficiencyvs Load Current,VOUT = 5V Efficiencyvs Load Current,VOUT = 3.3V Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2SIMPLE SWITCHER, WEBENCH areregisteredtrademarksofTexas Instruments. 3Allothertrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2012–2013,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.
SNVS815A –JUNE 2012–REVISED APRIL 2013 www.ti.com TypicalApplicationCircuit Connection Diagram See Package Number DGK PIN DESCRIPTION Pin Name Function
1 PGND Power Ground
2 EN Active-LowShutdown Input
3 FREQ FrequencyAdjust.An externalresistorconnectedbetween thispinand Pin6 (VDD )setstheswitching frequencyoftheLMR61428.
4 FB OutputVoltageFeedback
5 SGND SignalGround
6 VDD Power SupplyforInternalCircuitry
7 BOOT BootstrapSupplyfortheGate DriveofInternalMOSFET Power Switch
8 SW DrainoftheInternalMOSFET Power Switch
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www.ti.com SNVS815A –JUNE 2012–REVISED APRIL 2013 These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates. AbsoluteMaximum Ratings(1)(2) SW PinVoltage −0.5V to14.5V BOOT, VDD ,EN and FB Pins −0.5Vto10V FREQ Pin 100µA θJA (3) 240°C/W TJmax (3) 150°C StorageTemperatureRange −65°C to+150°C Lead Temp. (Soldering,5 sec) 260°C Power Dissipation(TA=25°C)(3) 500mW ESD Rating(4) 2kV (1) Absolutemaximum ratingsindicatelimitsbeyond whichdamage tothedevicemay occur.Electricalspecificationsdo notapplywhen operatingthedeviceoutsideofitsratedoperatingconditions. (2) IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheTexas InstrumentsSalesOffice/Distributorsforavailabilityand specifications. (3) The maximum power dissipationmust be deratedatelevatedtemperaturesand isdictatedby Tjmax (maximum junctiontemperature), θJA (junctiontoambientthermalresistance),and TA (ambienttemperature).The maximum allowablepower dissipationatany temperatureisPdmax = (Tjmax -TA)/θJA orthenumber givenintheAbsoluteMaximum Ratings,whicheverislower. (4) The human body model isa 100 pF capacitordischargedthrougha 1.5kΩ resistorintoeach pin.ForPin8 (SW) theESD ratingis1.5 kV. OperatingConditions(1) VDD Pin 2.5Vto5V FB, EN Pins 0 toVDD BOOT Pin 0 to10V AmbientTemperature(TA) −40°C to+85°C (1) Absolutemaximum ratingsindicatelimitsbeyond whichdamage tothedevicemay occur.Electricalspecificationsdo notapplywhen operatingthedeviceoutsideofitsratedoperatingconditions. Copyright© 2012–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:LMR61428
SNVS815A –JUNE 2012–REVISED APRIL 2013 www.ti.com ElectricalCharacteristics LimitsinstandardtypefaceareforTJ = 25°C, and limitsinboldfacetypeapplyoverthefulloperatingtemperaturerangeof −40°C to+85°C. Unlessotherwisespecified:VDD = VOUT = 3.3V. Symbol Parameter Condition Min Typ Max Units VIN_ST Minimum Start-UpSupplyVoltage ILOAD = 0mA 1.1 1.2 V (1) VIN_OP Minimum OperatingSupply ILOAD = 0mA 0.65 V Voltage(oncestarted) VFB FB PinVoltage 1.2028 1.24 1.2772 V VOUT_MAX Maximum OutputVoltage 14 V VHYST HysteresisVoltage(2) AtFeedback Pin 30 45 mV η Efficiency VIN = 3.6V;VOUT = 5V;ILOAD = 0.5A 87 VIN = 2.5V;VOUT = 3.3V;ILOAD = 0.2A 87 D SwitchDutyCycle 60 70 80 % IDD OperatingQuiescentCurrent(3) FB Pin> 1.3V;EN PinatVDD 80 110 µA ISD Shutdown QuiescentCurrent(4) VDD ,BOOT and SW Pinsat5.0V; µA0.01 2.5EN Pin<200mV ICL SwitchPeak CurrentLimit 2.85 A R DS_ON MOSFET SwitchOn Resistance 0.17 Ω Enable Section VEN_LO EN PinVoltageLow (5) 0.15VDD V VEN_HI EN PinVoltageHigh(5) 0.7VDD V (1) Outputinregulation,VOUT = VOUT (NOMINAL) ± 5% (2) Thisisthehysteresisvalueoftheinternalcomparatorused forthegated-oscillatorcontrolscheme. (3) ThisisthecurrentintotheVDD pin. (4) ThisisthetotalcurrentintopinsVDD ,BOOT, SW and FREQ. (5) When theEN pinisbelowVEN_LO ,theregulatorisshutdown; when itisabove VEN_HI ,theregulatorisoperating.
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EFFICIENCY (%) IOUT (A) Vin = 3.0V Vin = 3.2V Vin = 3.4V Vin = 3.6V Vin = 3.8V Vin = 4.0V EFFICIENCY (%) IOUT (A) Vin = 2.0V Vin = 2.2V Vin = 2.5V Vin = 2.80 LMR61428 www.ti.com SNVS815A –JUNE 2012–REVISED APRIL 2013 TYPICAL PERFORMANCE CHARACTERISTICS AllcurvestakenatTA = 25°C, unlessspecifiedotherwise. Efficiencyvs Load Current Efficiencyvs Load Current VOUT = 5.0V VOUT = 3.3V Figure1. Figure2. VFB vs Temperature IOP vs Temperature Figure3. Figure4. ISD vs Temperature,VDD = 5V ISD vs VDD Figure5. Figure6. Copyright© 2012–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:LMR61428
VOUT = 5V 50 mV/Div
10 Ps/DIV
SNVS815A –JUNE 2012–REVISED APRIL 2013 www.ti.com IOP vs VDD VIN_ST vs Load Current VOUT = 3.3V Figure7. Figure8. SwitchingFrequency vs R FQ Peak InductorCurrentvs Load Current Figure9. Figure10. Minimum InputVoltagevs Load Current Steady StateOperation Figure11. Figure12.
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www.ti.com SNVS815A –JUNE 2012–REVISED APRIL 2013 SimplifiedBlock Diagram Figure13. Block Diagram Copyright© 2012–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:LMR61428
SNVS815A –JUNE 2012–REVISED APRIL 2013 www.ti.com DETAILED DESCRIPTION OPERATING PRINCIPLE The LMR61428 is designed to providestep-upDC-DC voltageregulationin battery-poweredand low-input voltagesystems.Itcombines a step-upswitchingregulator,N-channelpower MOSFET, built-incurrentlimit, thermallimit,and voltagereferenceina single8-pinVSSOP package.The switchingDC-DC regulatorboostsan inputvoltagebetween 1.2V and 14V toa regulatedoutputvoltagebetween 1.24V and 14V thatislimitedby a fixedmaximum dutycylcleof70%. The LMR61428 startsfroma low 1.1V inputand remainsoperationaldown to 0.65V. Thisdeviceisoptimizedforuse incellularphones and otherapplicationsrequiringa smallsize,low profile,as wellas low quiescentcurrentformaximum batterylifeduringstand-byand shutdown.A high-efficiencygated- oscillatortopologyoffersan outputofup to1A. Additionalfeaturesincludea built-inpeak switchcurrentlimit,and thermalprotectioncircuitry. GATED OSCILLATOR CONTROL SCHEME A uniquegated oscillatorcontrolscheme enablesthe LMR61428 to have an ultra-lowquiescentcurrentand providesa high efficiencyover a wide load range. The switchingfrequencyof the internaloscillatoris programmableusingan externalresistorand can be setbetween 300 kHz and 2 MHz. Thiscontrolscheme uses a hysteresiswindow toregulatetheoutputvoltage.When theoutputvoltageisbelow theupper thresholdofthewindow,theLMR61428 switchescontinuouslywitha fixeddutycycleof70% atthe switchingfrequencyselectedby the user.Duringthe firstpartof each switchingcycle,the internalN-channel MOSFET switchisturnedon.Thiscauses thecurrenttoramp up intheinductorand storeenergy.Duringthe second partofeach switchingcycle,theMOSFET isturnedoff.The voltageacrosstheinductorreversesand forcescurrentthroughthediodetotheoutputfiltercapacitorand theload.Thus when theLMR61428 switches continuously,the outputvoltagestartsto ramp up. When the outputvoltagehitsthe upper thresholdof the window,theLMR61428 stopsswitchingcompletely.Thiscauses theoutputvoltagetodroopbecause theenergy storedintheoutputcapacitorisdepletedby theload.When theoutputvoltagehitsthelowerthresholdofthe hysteresiswindow, the LMR61428 startsswitchingcontinuouslyagaincausingthe outputvoltageto ramp up towardstheupperthreshold.Figure14 shows theswitchvoltageand outputvoltagewaveforms. Because of thistypeof controlscheme, the quiescentcurrentisinherentlyverylow.At lightloadsthe gated oscillatorcontrolscheme offersa much higherefficiencycompared totheconventionalPWM controlscheme. Figure14. TypicalStep-Up RegulatorWaveforms
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www.ti.com SNVS815A –JUNE 2012–REVISED APRIL 2013 LOW VOLTAGE START-UP The LMR61428 can start-upfrominputvoltagesas low as 1.1V.On start-up,thecontrolcircuitryswitchestheN- channelMOSFET continuouslyat70% dutycycleuntiltheoutputvoltagereaches2.5V.Afterthisoutputvoltage isreached,the normal step-upregulatorfeedbackand gated oscillatorcontrolscheme take over.Once the deviceisinregulationitcan operatedown to a 0.65V input,sincethe internalpower forthe IC can be boot- strappedfromtheoutputusingtheVDD pin. SHUTDOWN The LMR61428 featuresa shutdown mode thatreducesthe quiescentcurrentto lessthan an ensured 2.5µA over temperature.This extendsthe lifeof the batteryin batterypowered applications.Duringshutdown,all feedbackand controlcircuitryisturnedoff.The regulator'soutputvoltagedrops to one diodedrop below the inputvoltage.Entryintotheshutdown mode iscontrolledby theactive-lowlogicinputpinEN (Pin2).When the logicinputto thispinpulledbelow 0.15VDD , the devicegoes intoshutdown mode. The logicinputto thispin shouldbe above 0.7VDD forthedevicetowork innormalstep-upmode. OUTPUT VOLTAGE RIPPLE FREQUENCY A major component of the outputvoltagerippleisdue to the hysteresisused in the gated oscillatorcontrol scheme. The frequencyofthisvoltagerippleisproportionaltotheloadcurrent.The frequencyofthisrippledoes notnecessitatetheuse oflargerinductorsand capacitors.The sizeofthesecomponents isdeterminedby the switchingfrequencyoftheoscillatorwhichcan be setupto2MHz usingan externalresistor. INTERNAL CURRENT LIMITAND THERMAL PROTECTION An internalcycle-by-cyclecurrentlimitservesas a protectionfeature.Thisissethighenough (2.85Atypical, approximately4A maximum) so as nottocome intoeffectduringnormaloperatingconditions.An internalthermal protectioncircuitrydisablestheMOSFET power switchwhen thejunctiontemperature(TJ)exceedsabout160°C. The switchisre-enabledwhen TJ dropsbelowapproximately135°C. Design Procedure SETTING THE OUTPUT VOLTAGE The outputvoltageof the step-upregulatorcan be set between 1.24V and 14V. But because of the gated oscillatorscheme, themaximum possibleinputtooutputboostratioisfixed.Fora boostregulator, VOUT /VIN = 1 /[1−D] (1) The LMR61428 has a fixeddutycycle,D, of70% typical.Therefore, VOUT /VIN = 1 /0.3 (2) Thissetsthemaximum possibleboostratioofVIN toVOUT toabout3 times.The usercan now estimatewhat the minimum designinputsshouldbe inorderto achievea desiredoutput,or what the outputwould be when a certainminimum inputisapplied.E.g.IfthedesiredVOUT was 14V, thentheleastVIN shouldbe higherthanVOUT /3.Iftheinputvoltagefellbelow thisthreshold,theoutputvoltagewould notbe regulatedbecause ofthefixed dutycycle.Iftheminimum VIN was ensuredat2V,themax possibleVOUT wouldbe VIN *3. The VOUT issetby connectinga feedbackresistivedividermade ofR F1 and R F2.The feedbackresistorvalues areselectedas follows: A valueof150kΩ issuggestedforR F1.Then, R F2 can be selectedusingtheabove equation.A 39pF capacitor (Cff)connectedacrossR F1 helpsinfeedingback most oftheAC rippleatVOUT totheFB pin.Thishelpsreduce thepeak-to-peakoutputvoltagerippleas wellas improvetheefficiencyofthestep-upregulator,because a set hysteresisof30mV attheFB pinisused forthegatedoscillatorcontrolscheme. Copyright© 2012–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:LMR61428
SNVS815A –JUNE 2012–REVISED APRIL 2013 www.ti.com BOOTSTRAPPING When the outputvoltage(VOUT ) is between 2.5V and 5.0V a bootstrappedoperationis suggested.This is achievedby connectingtheVDD pin(Pin6)toVOUT .However iftheVOUT isoutsidethisrange,theVDD pinshould be connectedtoa voltagesourcewhose rangeisbetween 2.5Vand 5V.Thiscan be theinputvoltage(VIN),VOUT steppeddown usinga linearregulator,ora differentvoltagesourceavailableinthesystem.Thisisreferredtoas non-bootstrappedoperation.The maximum acceptablevoltageattheBOOT pin(Pin7)is10V. SETTING THE SWITCHING FREQUENCY The switchingfrequencyoftheoscillatorisselectedby choosingan externalresistor(RFQ ) connectedbetween FREQ and VDD pins.See the followinggraph,Figure15, forchoosingthe R FQ valueto achievethe desired switchingfrequency.A high switchingfrequencyallowsthe use of very smallsurfacemount inductorsand capacitorsand resultsin a very smallsolutionsize.A switchingfrequencybetween 300kHz and 2MHz is recommended. Figure15. SwitchingFrequency vs R FQ INDUCTOR SELECTION The LMR61428's highswitchingfrequencyenablestheuse ofa smallsurfacemount inductor.A 6.8µH shielded inductorissuggestedfora typicalapplication.The inductorshouldhave a saturationcurrentratinghigherthan the peak currentitwillexperienceduringcircuitoperation(see the followinggraph,Peak Inductorvs Load Current).Less than100m Ω ESR issuggestedforhighefficiency. Figure16. Peak InductorCurrentvs Load Current Open-core inductorscause fluxlinkagewithcircuitcomponents and interferewiththe normal operationof the circuit.They shouldbe avoided.Forhighefficiency,choose an inductorwitha highfrequencycorematerial,such as ferrite,toreducethecorelosses.To minimizeradiatednoise,use a toroid,potcoreorshieldedcoreinductor. The inductorshouldbe connectedtotheSW pinas closetotheIC as possible.See ConnectionDiagram.
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www.ti.com SNVS815A –JUNE 2012–REVISED APRIL 2013 OUTPUT DIODE SELECTION A Schottkydiodeshouldbe used fortheoutputdiode.The forwardcurrentratingofthediodeshouldbe higher thantheloadcurrent,and thereversevoltageratingmust be higherthantheoutputvoltage.Do notuse ordinary rectifierdiodes,sinceslowswitchingspeeds and longrecoverytimescause theefficiencyand theloadregulation tosuffer. INPUT AND OUTPUT FILTER CAPACITORS SELECTION Whiletantalumchipcapacitorsarerecommended fortheinputand outputfiltercapacitors,ceramiccaps can also be used.A 22µF capacitorissuggestedfortheinputfiltercapacitor.Itshouldhave a DC workingvoltagerating higherthanthemaximum inputvoltage.A 68µF tantalumcapacitorissuggestedfortheoutputcapacitor.The DC workingvoltageratingshouldbe greaterthantheoutputvoltage.VeryhighESR values(>3Ω)shouldbe avoided. PC BOARD LAYOUT High switchingfrequenciesand highpeak currentsmake a properlayoutofthePC board an importantpartof design.Poor designcan cause excessiveEMI and ground-bounce,bothofwhichcan cause malfunctionand loss ofregulationby corruptingvoltagefeedbacksignaland injectingnoiseintothecontrolsection. Power components -such as theinductor,inputand outputfiltercapacitors,and outputdiode-shouldbe placed as closetotheregulatorIC as possible,and theirtracesshouldbe keptshort,directand wide.The groundpins oftheinputand outputfiltercapacitorsand thePGND and SGND pinsofLMR61428 shouldbe connectedusing short,directand wide traces.The voltagefeedbacknetwork(Rfbt,R fbb,and C ff)shouldbe keptveryclosetothe FB pin.Noisytraces,such as fromtheSW pin,shouldbe keptaway fromtheFB and VDD pins.The tracesthat runbetween Vout and theFB pinoftheIC shouldbe keptaway fromtheinductorflux.Always providesufficient copperareatodissipatetheheatdue topower lossinthecircuitryand preventthethermalprotectioncircuitryin the IC from shuttingthe IC down. Additionalground planes as intermediatelevelshelp withshieldingand improveEMI mitigation. Copyright© 2012–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:LMR61428
SNVS815A –JUNE 2012–REVISED APRIL 2013 www.ti.com ApplicationExamples Figure17. EXAMPLE 1.5V/0.5AStep-Up Regulator U1 Texas Instruments LMR61428XMM C1 Vishay/Sprague 595D226X06R3B2T, Tantalum C2 Vishay/Sprague 595D686X0010C2T, Tantalum D1 Motorola MBRS140T3 L Coilcraft DT1608C-682
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www.ti.com SNVS815A –JUNE 2012–REVISED APRIL 2013 Figure18. EXAMPLE 2.2mm Tall5V/0.2AStep-Up RegulatorforLow ProfileApplications U1 Texas Instruments LMR61428XMM C1 Vishay/Sprague 592D156X06R3B2T, Tantalum C2 Vishay/Sprague 592D336X06R3C2T, Tantalum D1 Motorola MBRS140T3 L Vishay/Dale ILS-3825-03 Copyright© 2012–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:LMR61428
SNVS815A –JUNE 2012–REVISED APRIL 2013 www.ti.com
REVISION HISTORY
Changes from Original(April2013)toRevisionA Page
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www.ti.com 11-Nov-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) LMR61428XMM/NOPB Active Production VSSOP (DGK) | 8 1000 | SMALL T&R Yes SN Level-1-260C-UNLIM -40 to 85 SN1B LMR61428XMM/NOPB.A Active Production VSSOP (DGK) | 8 1000 | SMALL T&R Yes SN Level-1-260C-UNLIM -40 to 85 SN1B LMR61428XMM/NOPB.B Active Production VSSOP (DGK) | 8 1000 | SMALL T&R Yes SN Level-1-260C-UNLIM -40 to 85 SN1B LMR61428XMMX/NOPB Active Production VSSOP (DGK) | 8 3500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 85 SN1B LMR61428XMMX/NOPB.A Active Production VSSOP (DGK) | 8 3500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 85 SN1B LMR61428XMMX/NOPB.B Active Production VSSOP (DGK) | 8 3500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 85 SN1B (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1
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PACKAGE MATERIALS INFORMATION www.ti.com 31-Jul-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION www.ti.com 31-Jul-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMR61428XMM/NOPB VSSOP DGK 8 1000 208.0 191.0 35.0 LMR61428XMMX/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0 Pack Materials-Page 2
www.ti.com PACKAGE OUTLINE C 6X 0.65 1.95 8X 0.38 0.25 5.05
4.75 TYP
0.15 0.05 0.25 GAGE PLANE 0 -8
1.1 MAX
0.23 0.13 B 3.1 2.9 NOTE 4 A 3.1 2.9 NOTE 3 0.7 0.4 VSSOP - 1.1 mm max heightDGK0008A SMALL OUTLINE PACKAGE 4214862/A 04/2023
0.13 C A B
0.1 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-187. PowerPAD is a trademark of Texas Instruments. A 20 DETAIL A TYPICAL SCALE 4.000
www.ti.com EXAMPLE BOARD LAYOUT
0.05 MAX
0.05 MIN
8X (1.4) 8X (0.45) 6X (0.65) (4.4) (R0.05) TYP VSSOP - 1.1 mm max heightDGK0008A SMALL OUTLINE PACKAGE 4214862/A 04/2023 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. 8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. 9. Size of metal pad may vary due to creepage requirement. TM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 15X SYMM SYMM SEE DETAILS 15.000 METALSOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METALEXPOSED METAL SOLDER MASK DETAILS NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED
www.ti.com EXAMPLE STENCIL DESIGN 8X (1.4) 8X (0.45) 6X (0.65) (4.4) (R0.05) TYP VSSOP - 1.1 mm max heightDGK0008A SMALL OUTLINE PACKAGE 4214862/A 04/2023 NOTES: (continued) 11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 12. Board assembly site may have different recommendations for stencil design. TM SOLDER PASTE EXAMPLE SCALE: 15X SYMM SYMM
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