LMR10530

LMR10530 5.5-V, 3-A, 1.5 or 3-MHz Step-Down Regulator in WSON Package datasheet (Rev. B)

Document overview

• Manufacturer or author: Texas Instruments, Incorporated [SNVS814,B]
• PDF pages: 34

Technical content

7,89,10 C3 4NC Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LMR10530 SNVS814B –JUNE 2012–REVISED JUNE 2019 LMR105305.5-V,3-A,1.5or3-MHzStep-DownRegulatorinWSONPackage

1 Features

1• Input Voltage Range of 3 V to 5.5 V

• Output Voltage Range of 0.6 V to 4.5 V
• 1.5-MHz (LMR10530X) and 3-MHz (LMR10530Y) Switching Frequencies
• 3-A Steady-State Output Current
• Low Shutdown IQ, 300 nA Typical
• 56-mΩ PMOS Switch
• Internal Soft Start
• Internally Compensated Peak Current-Mode Control
• Cycle-by-cycle Current Limit and Thermal Shutdown
• WSON (3 × 3 × 0.8 mm) Packaging
• Create a custom design using the LMR10530 with the WEBENCH® Power Designer

2 Applications

• Point-of-load Conversions from 3.3-V and 5-V Rails
• Space-Constrained Applications

3 Description

The LMR10530 regulator is a monolithic, high frequency, PWM step-down DC/DC converter available in a 10-pin WSON package. It contains all the active functions to provide local DC/DC conversion with fast transient response and accurate regulation in the smallest possible PCB area. With a minimum of external components, the LMR10530 is easy to use. The ability to drive 3-A loads with an internal 56-mΩ PMOS switch using state-of-the-art 0.5-µm BiCMOS technology results in the best power density available. The control circuitry allows on-times as low as 30 ns, thus supporting exceptionally high- frequency conversion over the entire 3-V to 5.5-V input operating range down to the minimum output voltage of 0.6 V. Switching frequency is internally set to 1.5 MHz or 3 MHz, allowing the use of extremely small surface mount inductors and capacitors. Even though the operating frequency is high, efficiencies up to 93% are easy to achieve. External shutdown is included, featuring an ultra-low stand-by current of 300 nA. The LMR10530 utilizes peak current-mode control and internal compensation to provide high- performance regulation over a wide range of operating conditions. Additional features include internal soft-start circuitry to reduce inrush current, cycle-by-cycle current limit, frequency foldback, thermal shutdown, and output overvoltage protection. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) LMR10530 WSON (10) 3.00 mm × 3.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Typical Application

SNVS814B –JUNE 2012–REVISED JUNE 2019 www.ti.com Product Folder Links: LMR10530 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated Table of Contents

10.2 Receiving Notification of Documentation Updates 27

11 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (April 2013) to Revision B Page Changes from Original (April 2013) to Revision A Page

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5 Pin Configuration and Functions

DESCRIPTION

NO. NAME 1 VINC Input supply for internal bias and control circuitry. Need to locally bypass this pin to GND. 2 EN Enable control input. Logic high enables operation. Do not allow this pin to float or subject to voltages greater than VIN + 0.3V. 3 SGND Signal (analog) ground. Place the bottom resistor of the feedback network as close as possible to this pin for good load regulation. 4 NC No user function, connect this pin to GND. 5 FB Feedback pin. Connect this pin to the external resistor divider to set output voltage. 6 PGND Power ground pin. Provides ground return path for the internal driver. 7, 8 SW Switch pins. Connect these pins to the inductor and catch diode. 9, 10 VIND Input supply voltage. Connect a bypass capacitor locally from these pins to PGND. DAP Die Attach Pad Connect to system ground for low thermal impedance, but it cannot be used as a primary GND connection.

SNVS814B –JUNE 2012–REVISED JUNE 2019 www.ti.com Product Folder Links: LMR10530 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated (1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the recommended Operating Ratings is not implied. The recommended Operating Ratings indicate conditions at which the device is functional and should not be operated beyond such conditions. (2) If Military/Aerospace specified devices are required, contact the Texas Instruments Sales Office/ Distributors for availability and specifications. (3) Human body model, 1.5 kΩ in series with 100 pF. (4) Thermal shutdown occurs if the junction temperature exceeds the maximum junction temperature of the device.

6 Specifications

6.1 Absolute Maximum Ratings

See notes(1)(2). VINC, VIND -0.5V to 7V FB Voltage -0.5V to 3V EN Voltage -0.5V to VIN+o.3V SW Voltage -0.5V to 7V ESD Susceptibility(3) 2kV Junction Temperature(4) 150°C Storage Temperature -65°C to +150°C Soldering Information Infrared/Convection Reflow (15 sec) 220°C

6.2 Recommended Operating Ratings

VINC, VIND 3V to 5.5V Junction Temperature -40°C to +125°C

www.ti.com SNVS814B –JUNE 2012–REVISED JUNE 2019 Product Folder Links: LMR10530 Submit Documentation FeedbackCopyright © 2012–2019, Texas Instruments Incorporated (1) Applies for packages soldered directly onto a 4”× 3”4-layer standard JEDEC board in still air. (2) Thermal shutdown occurs if the junction temperature exceeds the maximum junction temperature of the device.

6.3 Electrical Characteristics

Unless otherwise specified under the Conditions column, VIN = 5 V. Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of –40°C to +125°C. Minimum and Maximum limits are ensured through test, design, or statistical correlation. Typical values represent the most likely parametric norm, and are provided for reference purposes only. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VFB Feedback Voltage WSON-10 Package 0.588 0.600 0.612 V ΔVFB/(ΔVINxVFB) Feedback Voltage Line Regulation VIN = 3V to 5.5V 0.08 %/V IB Feedback Input Bias Current 0.1 100 nA UVLO Undervoltage Lockout VIN Rising 2.70 2.90 V VIN Falling 1.85 2.35 UVLO Hysteresis 0.35 V fSW Switching Frequency LMR10530X 1.1 1.5 1.95 MHz LMR10530Y 2.25 3.0 3.75 DMAX Maximum Duty Cycle LMR10530X 86% 95% LMR10530Y 80% 90% DMIN Minimum Duty Cycle LMR10530X 5% LMR10530Y 7% RDS(ON) Switch On Resistance 58 90 mΩ ICL Switch Current Limit 3.4 4.4 A VEN_TH Enable Threshold Voltage 1.8 V Shutdown Threshold Voltage 0.4 ISW Switch Leakage 100 nA IEN Enable Pin Current Sink/Source 100 nA IQ Quiescent Current (switching) LMR10530X, VFB = 0.55 3.2 5 mA LMR10530Y, VFB = 0.55 4.3 6.5 Quiescent Current (shutdown) All Options VEN = 0V 300 nA VFB_F FB Frequency Foldback Threshold All Options 0.32 V fFB Foldback Frequency LMR10530X, VFB = 0V 400 kHz LMR10530Y, VFB = 0V 800 θJA Junction to Ambient

0 LFPM Air Flow (1) 53 °C/W

θJC Junction to Case (1) 12 °C/W TSD Thermal Shutdown Threshold (2) Junction Temperature Rising 165 °C TSD_HYS Thermal Shutdown Hysteresis Junction Temperature Falling 15 °C

6.4 Typical Characteristics

Figure 1. Efficiency vs Load Current - Both Options Figure 2. Efficiency vs Load Current - LMR10530X Figure 3. Efficiency vs Load Current - LMR10530Y Figure 4. Oscillator Frequency vs Temperature - LMR10530X Figure 5. Oscillator Frequency vs Temperature - LMR10530Y Figure 6. Current Limit vs Temperature

Figure 19. Short-Circuit Release - LMR10530X

7 Detailed Description

7.1 Overview

Figure 20. Typical Waveforms

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7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 Frequency Foldback

Typical Characteristics section.

7.3.2 Load Step Response

less effect on the step response at lower output voltages. bandwidth as a result of CFF reduces the total output excursion by more than half. desired output voltages are close to the feedback voltage. Figure 21. Adding a CFF Capacitor

Figure 22. Loop Gain and Phase Without CFF Figure 23. Loop Gain and Phase With CFF Figure 24. Load Step Response Without CFF Figure 25. Load Step Response With CFF

7.3.3 Output Overvoltage Protection

7.3.4 Undervoltage Lockout

below 2.35 V (typical). Hysteresis prevents the part from turning off during power up if VIN is non-monotonic.

7.3.5 Current Limit

switch until the next switching cycle begins.

7.3.6 Soft Start/Shutdown

Figure 26. In applications where this output voltage overshoot is undesirable, one simple solution is to add a up output voltage smoothly as shown in Figure 28. smooth output voltage rise, at low programmed output voltage and high output load current.

Figure 26. Start-up Response to VIN Figure 27. Start-up Response to VIN With CFF Figure 28. Startup Response To VIN With 100-µs Rise Time Figure 29. Recovery From Thermal Shutdown -

7.3.7 Thermal Shutdown

until the junction temperature drops below approximately 150°C.

2.2 PF 22 PF 22 nF

8 Application and Implementation

validate and test their design implementation to confirm system functionality.

8.1 Application Information

efficiencies up to 93% are easy to achieve.

8.2 Typical Application

Figure 30. Typical Application Schematic

8.2.1 Detailed Design Procedure

8.2.1.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the LMR10530 device with the WEBENCH® Power Designer.

1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.

pricing and component availability.

• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues Get more information about WEBENCH tools at www.ti.com/WEBENCH.

L = VOUT + VD IOUT x r x fSW x (1-D) r = 'iL lOUT D = VOUT + VD VIN + VD - VSW D = VOUT VIN LMR10530 www.ti.com SNVS814B –JUNE 2012–REVISED JUNE 2019 Product Folder Links: LMR10530 Submit Documentation FeedbackCopyright © 2012–2019, Texas Instruments Incorporated Typical Application (continued)

8.2.1.2 Inductor Selection

The duty cycle (D) can be approximated quickly using the ratio of output voltage (VOUT) to input voltage (VIN): (3) The catch diode (D1) forward voltage drop and the voltage drop across the internal PMOS must be included to calculate a more accurate duty cycle. Calculate D by using the following formula: (4) VSW can be approximated by: VSW = IOUT x RDS(ON) where

• IOUT is output load current. (5) The diode forward drop (VD) can range from 0.3 V to 0.7 V depending on the quality of the diode. The lower the VD, the higher the operating efficiency of the converter. The inductor value determines the output ripple current (ΔiL, as defined in ). Lower inductor values decrease the size of the inductor, but increase the output ripple current. An increase in the inductor value decreases the output ripple current. In general, the ratio of ripple current to the output current is optimized when it is set between 0.2 and 0.4 for output currents above 2 A. This ratio r is defined as: (6) One must ensure that the minimum current limit (3.4 A) is not exceeded, so the peak current in the inductor must be calculated. The peak current (ILPK) in the inductor is calculated by: ILPK = IOUT + ΔiL/2 (7) When the designed maximum output current is reduced, the ratio r can be increased. At a current of 0.1 A, r can be made as high as 0.9. The ripple ratio can be increased at lighter loads because the net ripple is actually quite low, and if r remains constant the inductor value can be made quite large. An equation empirically developed for the maximum ripple ratio at any current below 2 A is: r = 0.387 x IOUT -0.3667 (8) Note that this is just a guideline, and it needs to be combined with two important factors for proper selection of inductance values at any operating condition. The first consideration is at output voltage above 2.5 V, one needs to ensure that the inductance given by the above guideline should not be less than 1 µH for the LMR10530X or 0.5 µH for the LMR10530Y. Because the LMR10530 has a fixed internal corrective ramp signal, a very low inductance value at high output voltage generates a very steep down slope of inductor current, which results in an insufficient slope compensation, and cause instability known as sub-harmonic oscillation. Another consideration is at low load current, one needs to ensure that the inductance value given by the guideline should not exceed 10 µH for the LMR10530X and 4.7 µH for the LMR10530Y, since too much inductance effectively flattens the down slope of the inductor current, and may significantly limit the system bandwidth and phase margin resulting in instability. The LMR10530 operates at frequencies allowing the use of ceramic output capacitors without compromising transient response. Ceramic capacitors allow higher inductor ripple without significantly increasing output ripple. See the Output Capacitor section for more details on calculating output voltage ripple. Now that the ripple current is determined, the inductance is calculated by: where
• fSW is the switching frequency. (9)

'VOUT = 'IL R ESR +8 x fSW x COUT IRMS-IN = IOUT x D x 1 - D IRMS-IN = IOUT x D x r2 121 - D + LMR10530 SNVS814B –JUNE 2012–REVISED JUNE 2019 www.ti.com Product Folder Links: LMR10530 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated Typical Application (continued) When selecting an inductor, make sure that it is capable of supporting the peak output current without saturating. Inductor saturation will result in a sudden reduction in inductance and prevent the regulator from operating properly. Because of the operating frequency of the LMR10530, ferrite based inductors are preferred to minimize core losses. This presents little restriction since the variety and availability of ferrite-based inductors is large. Lastly, inductors with lower series resistance (DCR) will provide better operating efficiency. For recommended inductor selection, refer to Other System Examples.

8.2.1.3 Input Capacitor

An input capacitor is necessary to ensure that VIN does not drop excessively during switching transients. The primary specifications of the input capacitor are capacitance, voltage rating, RMS current rating, and equivalent series inductance (ESL). The input voltage rating is specifically stated by the capacitor manufacturer. Make sure to check any recommended deratings and also verify if there is any significant change in capacitance at the operating input voltage and the operating temperature. The input capacitor maximum RMS input current rating (IRMS-IN) must be greater than: (10) Neglecting inductor ripple simplifies the above equation to: (11) It can be shown from the above equation that maximum RMS capacitor current occurs when D = 0.5. Always calculate the RMS at the point where the duty cycle D is closest to 0.5. The ESL of an input capacitor is usually determined by the effective cross sectional area of the current path. As a rule of thumb, a large leaded capacitor will have high ESL and a 1206 ceramic chip capacitor will have very low ESL. At the operating frequencies of the LMR10530, leaded capacitors may have an ESL so large that the resulting impedance (2 πfL) will be higher than that required to provide stable operation. TI strongly recommends usin ceramic capacitors due to their low ESR and low ESL. A 22-µF multilayer ceramic capacitor (MLCC) is a good choice for most applications. In cases where large capacitance is required, use surface mount capacitors such as Tantalum capacitors and place at least a 4.7-µF ceramic capacitor close to the VIN pin. For MLCCs TI recommends using X7R or X5R dielectrics. Consult capacitor manufacturer datasheet to see how rated capacitance varies over operating conditions.

8.2.1.4 Output Capacitor

The output capacitor is selected based upon the desired output ripple and transient response. The initial current of a load transient is provided mainly by the output capacitor. The output ripple of the converter is: (12) When using MLCCs, the ESR is typically so low that the capacitive ripple may dominate. When this occurs, the output ripple will be approximately sinusoidal and 90° phase shifted from the switching action. Given the availability and quality of MLCCs and the expected output voltage of designs using the LMR10530, there is really no need to review any other capacitor technologies. Another benefit of ceramic capacitors is their ability to bypass high frequency noise. A certain amount of switching edge noise will couple through parasitic capacitances in the inductor to the output. A ceramic capacitor will bypass this noise while a tantalum will not. Since the output capacitor is one of the two external components that control the stability of the regulator control loop, most applications will require a minimum of 22-µF output capacitance. In the case of low output voltage, a larger output capacitance is required to ensure sufficient phase margin. Capacitance can often, but not always, be increased significantly with little detriment to the regulator stability. Like the input capacitor, recommended multilayer ceramic capacitors are X7R or X5R types. Again, verify actual capacitance at the desired operating voltage and temperature. Check the RMS current rating of the capacitor. The maximum RMS current rating of the capacitor is: (13) One may select a 1206 size MLCC for output capacitor, since its current rating is typically above 1 A, more than enough for the requirement.

D = VOUT + VD + VDCR VIN + VD - VSW D = VOUT + VD VIN + VD - VSW K = POUT POUT + PLOSS K = POUT PIN x R2R1 = VREF VOUT - 1 LMR10530 www.ti.com SNVS814B –JUNE 2012–REVISED JUNE 2019 Product Folder Links: LMR10530 Submit Documentation FeedbackCopyright © 2012–2019, Texas Instruments Incorporated Typical Application (continued)

8.2.1.5 Catch Diode

The catch diode conducts during the switch off-time. TI recommends a Schottky diode for its fast switching time and low forward voltage drop. The catch diode should be chosen such that its current rating is greater than: ID = IOUT × (1-D) (14) The reverse breakdown rating of the diode must be at least the maximum input voltage plus appropriate margin. To improve efficiency, choose a Schottky diode with a low forward voltage drop.

8.2.1.6 Output Voltage

The output voltage is set using the following equation where R2 is connected between the FB pin and GND, and R1 is connected between VOUT and the FB pin. A good value for R2 is 2 kΩ. (15) VREF = 0.6 V (16)

8.2.1.7 Efficiency Estimation

The complete LMR10530 DC/DC converter efficiency can be calculated in the following manner: (17) or (18) Calculations for determining the most significant power losses are shown in the following examples. Other losses totaling less than 2% are not discussed. The main power loss (PLOSS) in the converter includes two basic types of losses: switching loss and conduction loss. In addition, there is loss associated with the power required for the internal circuitry of IC. Conduction losses usually dominate at higher output loads, whereas switching losses dominate at lower output loads. The first step in determining the losses is to calculate the duty cycle (D): (19) VSW is the voltage drop across the internal power switch when it is on, and is equal to: VSW = IOUT × RDS(ON) (20) VD is the forward voltage drop across the catch diode. It can be obtained from the diode manufactures Electrical Characteristics section. If the DC voltage drop across the inductor (VDCR) is accounted for, the equation becomes: (21) The conduction losses in the catch diode are calculated as follows: PDIODE = VD × IOUT × (1-D) (22) Often this is the single most significant power loss in the circuit. Take care to choose a Schottky diode with a low forward-voltage drop. Another significant external power loss is the conduction loss in the output inductor. The equation can be simplified to: PIND = IOUT 2 × RDCR (23) The LMR10530 conduction loss is mainly associated with the internal power switch:

this loss is to empirically measuring the rise and fall times (10% to 90%) of the switch at the switch node. Table 1. Power Loss Tabulation

8.2.2 Application Curve

Figure 31. Line Transient Response - "LMR10530X"

8.2.3 Other System Examples

8.2.3.1 LMR10530X Design Example 1

Figure 32. LMR10530X (1.5 MHz) Table 2. Bill Of Materials

8.2.3.2 LMR10530X Design Example 2

Figure 33. LMR10530X (1.5 MHz) Table 3. Bill Of Materials

8.2.3.3 LMR10530Y Design Example 3

Figure 34. LMR10530Y (3 MHz) Table 4. Bill Of Materials

8.2.3.4 LMR10530Y Design Example 4

Figure 35. LMR10530Y (3 MHz) Table 5. Bill Of Materials

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9 Layout

9.1 Layout Considerations

When planning layout there are a few things to consider to achieve a clean, regulated output. The most important consideration is the close coupling of the GND connections of the input capacitor Cin and the catch diode D1. These ground ends should be close to one another and be connected to the GND plane with at least two through-holes. Place these components as close to the IC as possible. The next consideration is the location of the GND connection of the output capacitor Co, which should be near the GND connections of C1 and D1. There must be a continuous ground plane on the bottom layer of a two-layer board except under the switching node island. Tie the signal ground SGND (pin 3) and power ground PGND (pin 6) together and connected to ground plane through vias. The FB pin is a high impedance node— take care to make the FB trace short to avoid noise pickup that causes inaccurate regulation. The feedback resistors must be placed as close as possible to the IC, with the GND of Rfbb placed as close as possible to the SGND of the IC. Route the VOUT trace to Rfb1 away from the inductor and any other traces that are switching. High AC currents flow through the VIN, SW, and VOUT traces, so they must be as short and wide as possible. Radiated noise can be decreased by choosing a shielded inductor. Place the remaining components as close as possible to the IC. See Application Note AN-2280 for further considerations and the LMR10530 demo board as an example of a four-layer layout.

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10 Device and Documentation Support

10.1 Device Support

10.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

10.1.2 Development Support

10.1.2.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the LMR10530 device with the WEBENCH® Power Designer. 1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements. 2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial. 3. Compare the generated design with other possible solutions from Texas Instruments. The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time pricing and component availability. In most cases, these actions are available:

• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues Get more information about WEBENCH tools at www.ti.com/WEBENCH.

10.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

10.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

10.4 Trademarks

E2E is a trademark of Texas Instruments. WEBENCH is a registered trademark of Texas Instruments. All other trademarks are the property of their respective owners.

10.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

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10.6 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 1-Nov-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) LMR10530XSD/NOPB Active Production WSON (DSC) | 10 1000 | SMALL T&R Yes SN Level-1-260C-UNLIM -40 to 125 L287B LMR10530XSD/NOPB.A Active Production WSON (DSC) | 10 1000 | SMALL T&R Yes SN Level-1-260C-UNLIM -40 to 125 L287B LMR10530XSDX/NOPB Active Production WSON (DSC) | 10 4500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 L287B LMR10530XSDX/NOPB.A Active Production WSON (DSC) | 10 4500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 L287B LMR10530XSDX/NOPB.B Active Production WSON (DSC) | 10 4500 | LARGE T&R - Call TI Call TI -40 to 125 LMR10530YSD/NOPB Active Production WSON (DSC) | 10 1000 | SMALL T&R Yes SN Level-1-260C-UNLIM -40 to 125 L286B LMR10530YSD/NOPB.A Active Production WSON (DSC) | 10 1000 | SMALL T&R Yes SN Level-1-260C-UNLIM -40 to 125 L286B LMR10530YSDX/NOPB Active Production WSON (DSC) | 10 4500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 L286B LMR10530YSDX/NOPB.A Active Production WSON (DSC) | 10 4500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 L286B (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative Addendum-Page 1

www.ti.com 1-Nov-2025 and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 31-Jul-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 31-Jul-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMR10530XSD/NOPB WSON DSC 10 1000 208.0 191.0 35.0 LMR10530XSDX/NOPB WSON DSC 10 4500 367.0 367.0 35.0 LMR10530YSD/NOPB WSON DSC 10 1000 208.0 191.0 35.0 LMR10530YSDX/NOPB WSON DSC 10 4500 367.0 367.0 35.0 Pack Materials-Page 2

www.ti.com SDA10A (Rev A)

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