LMQ644XX-Q1

LMQ644A2-Q1 TI

Document overview

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• PDF pages: 60

Technical content

LMQ644xx-Q1 3-V to 36-V, Low IQ, Dual 6/5/4-A Automotive Buck Converter Optimized for Power Density and Low EMI

1 Features

• AEC-Q100-qualified for automotive applications: – Device temperature grade 1: –40°C to +125°C ambient operating temperature – Operation up to 150°C junction temperature
• Functional Safety-Capable – Documentation available to aid functional safety system design
• Designed for Low EMI – Symmetrical input voltage pins with > 1 mm clearance to ground – Four 22-nF integrated VIN to GND bypass capacitors
• Two bypass capacitors placed in series between each VIN and GND for high reliability – Pin selectable spread spectrum option – Pin selectable FPWM or auto mode operation – Enhanced HotRod™ QFN (25) package with wettable flanks – Switching frequency from 100 kHz to 2.2 MHz – Meets CISPR 25 class 5 EMI requirements
• Single and dual-output features – Wide input voltage range of 3 V to 36 V – 1% accurate fixed 3.3 V, 5 V or adjustable outputs from 0.8 V to 20 V – Hiccup-mode overcurrent protection and thermal shutdown protection with hysteresis – Precision ENABLE and PGOOD functions – 50 ns tON(min) for high VIN / VOUT ratio – 80 ns tOFF(min) for low dropout
• Versatile dual-output operation – Shutdown mode current: 0.5-µA typical – No-load standby current: 9-µA typical – Built-in compensation and 3-ms soft start – Independent precision ENABLE and PGOOD
• Adaptable single-output operation – > 95% efficient for an 8-A load, single output, VIN =12 V, VOUT = 5 V – External compensation and adjustable soft start – PGOOD, SYNCIN, and SYNCOUT functions

2 Applications

• Automotive infotainment and cluster: head unit, media hub, USB charge, display
• Automotive ADAS and body electronics
• General-purpose dual buck converters

3 Description

The LMQ644xx-Q1 is a 36-V, synchronous, buck DC/DC converter for high-current single or dual outputs. The device uses an interleaved, stackable, current-mode control architecture for easy loop compensation, fast transient response, excellent load and line regulation, and accurate current sharing with an output clock supporting up to 6 phases for currents up to 36 A. A high-side switch minimum on-time of 50 ns gives large step-down ratios, enabling the direct conversion from 12 V, 24 V, or automotive inputs to low-voltage rails for reduced system complexity and design cost. The LMQ644xx-Q1 incorporates spread spectrum in an optimized enhanced HotRod QFN package, with wettable flanks, and four 22-nF high frequency integrated capacitors to minimize EMI. Dual Random Spread Spectrum (DRSS) frequency hopping is set to ±10% (typical), drastically reducing emissions through a combination of triangular and pseudo-random modulation. A bias pin allows the LMQ644xx-Q1 to save losses by powering the device from the output of the converter, achieving a 9- μA no-load quiescent current to extend the operating run-time in battery-powered systems. The LMQ644xx-Q1 can maintain high efficiency light-load operation even when stacking multiple devices for high efficiency over the full load range. Device Information PART NUMBER(3) PACKAGE(1) BODY SIZE (NOM) LMQ644A2-Q1 RXA (VQFN-FCRLF, 24) 4.0 mm × 5.0 mmLMQ644A0-Q1(2) LMQ64480-Q1(2) (1) For all available packages, see the orderable addendum at the end of the data sheet. (2) Preview information (not Production Data). (3) See the Device Comparison Table. CISPR 25 Conducted, VOUT = 3.3 V, 2.1 MHz, 12 A LMQ644A2-Q1 SNVSC42 – SEPTEMBER 2023 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.

10.2 Receiving Notification of Documentation Updates..55

11 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. DATE REVISION NOTES September 2023 * Initial release LMQ644A2-Q1 SNVSC42 – SEPTEMBER 2023 www.ti.com

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5 Device Comparison Table

CURRENT PACKAGE JUNCTION TEMPERATURE RANGE RELEASE STATUS LMQ644A2-Q1 LMQ644A2QRXARQ1 Dual 6 A/6 A, or stackable 12 A RXA (WQFN, 24) –40°C to 150°C Released LMQ644A0-Q1 LMQ644A0QRXARQ1 Dual 5 A/5 A, or stackable 10 A RXA (WQFN, 24) –40°C to 150°C Preview LMQ64480-Q1 LMQ64480QRXARQ1 Dual 4 A/4 A, or stackable 8 A RXA (WQFN, 24) –40°C to 150°C Preview www.ti.com LMQ644A2-Q1 SNVSC42 – SEPTEMBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: LMQ644A2-Q1

6 Pin Configuration and Functions

RXA package, 24-pin VQFN-FCRLF with Wettable Flanks 1 2 3 4 5 6 7 12131415161720 18 19 SERIES CAP2 SERIES CAP1 PG2 VIN2 CB2 SW2 PGND3 SW1 CB1 VIN1 PGND2 PGND1 PG2 CONFIG EN2 BIAS & VOSNS1 VOSNS2 FB2 RT VCC FB1 PG1 SYNC PGND EN1 AGND Figure 6-1. Dual Output (Top View) LMQ644A2-Q1 SNVSC42 – SEPTEMBER 2023 www.ti.com

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Table 6-1. Pin Functions PIN TYPE(1) DESCRIPTION NO. NAME DUAL OUTPUT SINGLE OUTPUT 1 VIN2 VIN2 I Input supply to the regulator. Connect a high quality bypass capacitors from this pin to PGND2. Low impedance connection must be provided to VIN1. 2 BOOT2 BOOT2 I/O Channel 2 high-side driver upper supply rail. Connect a 100-nF capacitor between SW2 and BOOT2. An internal diode charges the capacitor while SW2 is low.

3 SW2 SW2 P

Channel 2 Switching node that is internally connected to the source of the high-side NMOS buck switch and the drain of the low-side NMOS synchronous rectifier. Connect to the switching node of the power inductor. 4 PGND3 PGND3 G Power ground to internal low side MOSFET. Connect to system ground. Low impedance connection must be provided to PGND1, PGND2 and exposed pad.

5 SW1 SW1 P

Channel 1 Switching node that is internally connected to the source of the high-side NMOS buck switch and the drain of the low-side NMOS synchronous rectifier. Connect to the switching node of the power inductor. 6 BOOT1 BOOT1 I/O Channel 1 High-side driver upper supply rail. Connect a 100-nF capacitor between SW1 and BOOT1. An internal diode charges the capacitor while SW1 is low. 7 VIN1 VIN1 I Input supply to the regulator. Connect a high quality bypass capacitors from this pin to PGND1. Low impedance connection must be provided to VIN2.

8 SERIES

Pin is connected to mid-point of two series capacitors between pins VIN1 and PGND1. This pin can be left floating, or can be connected to the mid-point of additional bypass capacitors in series configuration if required for the end application.

9 PGND1 PGND1 G

Power ground to internal low side MOSFET. Connect to system ground. Low impedance connection must be provided to PGND2 and PGND3. Connect a high quality bypass capacitors from this pin to VIN1.

10 SYNC SYNC I

Multi-function pin. SYNC selects forced pulse width modulation (FPWM) or Diode Emulation mode. Connect SYNC to AGND to enable diode emulation mode. Connect SYNC to VCC to operate the LMQ644xx in FPWM mode with continuous conduction at light loads. SYNC can also be used as a synchronization input to synchronize the internal oscillator to an external clock. When used as a secondary device in single output configuration, the SYNC pin is connected to SYNC_OUT of the primary for clock timing.

11 PG1 MODE O

Dual function pin. An open drain output that transitions low if VOSNS1 is outside a specified regulation window in dual output and single output primary configuration. In single output secondary mode configuration, this behaves as a mode pin to select between forced PWM (FPWM) mode and Diode Emulation Mode (DEM). Connect MODE of single output secondary to SYNC pin of single output primary to place them in the same mode of operation. For FPWM, connect MODE to VCC through a 10 kOhm resistor. For DEM connect to ground.

12 EN1 EN1 I

An active high input LMQ644xx (VOH > 1.375 V) enables Output 1 in dual output operation. When in single output operation, an active high input enables all phases in the system. When disabled, the LMQ644xx is in shutdown mode. EN1 must never be floating.

13 BIAS &

BIAS & VOSNS1 I Output voltage sense and input to internal voltage regulator. Connect to non-switching side of the inductor. Connect an optional high quality 0.1-μF capacitor from this pin to AGND for best performance.

14 FB1 FB1 I

Feedback input to channel 1 of the LMQ644xx in dual output operation and feedback input to all channels in single output operation. Connect FB1 to VCC through a 10 kOhm resistor for a 5-V output or connect FB1 to AGND for a 3.3-V output. A resistive divider from the non-switching side of the inductor to FB1 sets the output voltage level between 0.8 V and 20 V. The regulation threshold at FB1 is 0.8 V. For lower output voltages use at least a 10 kOhm for the top of the resistor divider. 15 VCC VCC O Internal regulator output. Used as supply to internal control circuits. Do not connect to any external loads. Connect a high quality 1-μF capacitor from this pin to AGND. 16 AGND AGND G Analog ground connection. Ground return for the internal voltage reference and analog circuits. 17 RT RT I Frequency programming pin. A resistor from RT to AGND sets the oscillator frequency between 100 kHz and 2.2 MHz. LMQ644A2-Q1 SNVSC42 – SEPTEMBER 2023 www.ti.com

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Table 6-1. Pin Functions (continued) PIN TYPE(1) DESCRIPTION NO. NAME DUAL OUTPUT SINGLE OUTPUT

18 FB2 SS I

Dual function pin. When in dual output operation, the pin functions as FB2, feedback input to channel 2 of the LMQ644xx. Connect FB2 to VCC through a 10 kOhm resistor for a 5-V output or connect FB2 to AGND for a 3.3-V output. A resistive divider from the non-switching side of the inductor to FB2 sets the output voltage level between 0.8 V and 20 V. For lower output voltages use at least a 10 kOhm for the top of the resistor divider. When in single output mode, the pin functions as SS. An external capacitor must be placed from SS to AGND for external soft-start of the output. Connect the SS pins of primary and secondaries for fault communication between devices.

19 VOSNS2 COMP I

Dual function pin. In dual output operation, the pin functions as VOSNS2 for the fixed 3.3-V and 5-V and adjustable output conditions. In single output operation, the pin is the output of the internal error amplifier.

20 EN2 EN2 I

An active high input (VOH > 1.375 V) enables Output 2 in dual output operation. When in single output mode, EN2 of all LMQ644xx must be connected together. An active high input enables all secondary phases in the system. When disabled, only one channel in the primary LMQ644xx is active while all remaining phases are in shutdown mode. EN2 must never be floating. 21 CONFIG CONFIG I Single or Dual output selection. Connect specific resistor values to the pin (refer to table Table 8-3) to select number of phases, primary and secondary and dither options.

22 PG2 SYNC_

Dual function pin. In dual output operation, this pin behaves as PG2, an open drain output that transitions low if VOSNS2 is outside a specified regulation window. In single output mode, the pin functions as SYNC_OUT and provides clock information from primary to secondary.

23 PGND2 PGND2 G

Power ground to internal low side MOSFET. Connect to system ground. Low impedance connection must be provided to PGND1, PGND3 and PGND4. Connect a high quality bypass capacitors from this pin to VIN2.

24 SERIES

Pin is connected to mid-point of two series capacitors between pins VIN2 and PGND2.This pin can be left floating for better pin FMEA, or can be connected to the mid-point of a capacitive divider between VIN2 and PGND2 as per convenience. 25 PGND4 PGND4 G Power ground and heat sink connection. Solder directly to system ground plane. Low impedance connection must be provided to PGND1, PGND2 and PGND3. (1) I = input, O = output, P = power, G = ground

6.1 Wettable Flanks

100% automated visual inspection (AVI) post-assembly is typically required to meet requirements for high reliability and robustness. Optimized QFN packages do not have solderable or exposed pins and terminals that are easily viewed. It is therefore difficult to visually determine whether or not the package is successfully soldered onto the printed-circuit board (PCB). The wettable-flank process was developed to resolve the issue of side-lead wetting of leadless packaging. The LMQ644xx-Q1 is assembled using a 24-pin Enhanced HotRod QFN package with wettable flanks to provide a visual indicator of solderability, which reduces the inspection time and manufacturing costs. www.ti.com LMQ644A2-Q1 SNVSC42 – SEPTEMBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: LMQ644A2-Q1

7 Specifications

7.1 Absolute Maximum Ratings

Over operating junction temperature range (unless otherwise noted) (1) MIN MAX UNIT Pin voltage VIN1, VIN2 to PGND (transient) –0.3 42 V Pin voltage SW1, SW2 to PGND (less than 10ns transient) –6 42.3 V Pin voltage SW1, SW2 to PGND (transient) –0.3 42.3 V Pin voltage BOOT1 - SW1, BOOT2 - SW2 –0.3 5.5 V Pin voltage EN1, EN2 to AGND –0.3 42 V Pin voltage PG1, SYNC_OUT/PG2 to AGND –0.3 20 V Pin voltage SYNC/MODE, FB1, FB2/SS, CONFIG to AGND –0.3 5.5 V Pin voltage BIAS/VOSNS1, COMP/VOSNS2 to AGND –0.3 22 V Pin voltage RT, VCC to AGND –0.3 5.5 V Pin voltage PGND1/2/3 to AGND voltage differential –1 2 V Sink current PG1, PG2 10 mA TJ Operating junction temperature –40 150 °C Tstg Storage temperature –55 150 °C (1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

7.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per AEC Q100-002 (1) HBM ESD classification Level 2 ±2000 VCharged device model (CDM), per AEC Q100-011 CDM ESD clasiffication Level C5 Corner pins (VIN1, VIN2, EN1, and EN2) ±750 Other pins ±750 (1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

7.3 Recommended Operating Conditions

Over operating junction temperature range (unless otherwise noted) MIN NOM MAX UNIT VVOSNS1/2 Output Voltage range 0.8 20 V VIN1/2 Input supply voltage range VIN1, VIN2 3 36 V FSW Frequency Switching frequency range 100 2200 kHz IOUT1/2 Output current range LMQ644A2 0 6 A TJ Operating junction temperature –40 150 °C

7.4 Thermal Information

THERMAL METRIC(1) DEVICE UNITRXA (JEDEC board 51-7) RXA (LMQ644A2 EVM)

24 PINS 24 PINS

RθJA Junction-to-ambient thermal resistance 34.2 17 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 6 (3) °C/W RθJC(top) Junction-to-case (top) thermal resistance 9.6 (2) °C/W RθJB Junction-to-board thermal resistance 7.3 (2) °C/W ψJT Junction-to-top characterization parameter 0.6 1 °C/W ψJB Junction-to-board characterization parameter 7.2 8.9 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. LMQ644A2-Q1 SNVSC42 – SEPTEMBER 2023 www.ti.com

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(2) Not applicable to an EVM.

7.5 Electrical Characteristics

TJ = –40°C to +150°C. Typical values are at TJ = 25°C and VIN = 13.5 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY IQ(VIN-DT3p3) VIN quiescent current, dual output mode, BIAS = 3.3V Non-switching, VEN = 2 V, VBIAS = VVOSNS1 = 3.3V + 10%, VVOSNS2 = 5 V + 10% 7 30 µA IQ(VIN-ST5p0) VIN quiescent current, single output mode Non-switching, VEN = 2 V, VBIAS = VVOSNS1 = 5V + 10% 29 45 µA IQ(VIN-ST3p3) VIN quiescent current, single output mode Non-switching, VEN = 2 V, VBIAS = VVOSNS1 = 3.3V + 10% 18 35 µA ISD(VIN) VIN shutdown supply current VEN = 0 V 0.5 8 µA UVLO VINUVLO(R) VIN UVLO rising threshold VIN rising 3.5 3.80 V VINUVLO(F) VIN UVLO falling threshold VIN falling 2.5 3 V VINUVLO(H) VIN UVLO hysteresis 0.75 1 1.25 V ENABLE VEN(R) EN1/2 voltage rising threshold EN1/2 rising, enable switching 1.125 1.25 1.375 V VEN(F) EN1/2 voltage falling threshold EN1/2 falling, disable switching 0.8 0.9 1.0 V VEN(H) EN1/2 voltage hysteresis 0.25 0.325 0.55 V VEN(W) EN1/2 voltage wake-up threshold 0.4 V IEN EN1/2 pin sourcing current post EN rising threshold VEN1/2 = VIN = 13.5 V 0.6 400 nA INTERNAL LDO VVCC Internal LDO output voltage VBIAS ≥ 3.4 V, IVCC ≤ 100 mA 2.7 3.1 3.7 V IVCC Internal LDO short-circuit current limit VIN = 13.5 V 100 360 880 mA VVCC(UVLO-R) VCC UVLO rising threshold for Startup 3.3 3.5 3.75 V VVCC(UVLO-F) VCC UVLO falling threshold for Shutdown 2.3 2.5 2.7 V REFERENCE VOLTAGE VFB1/2 Dual Output FB voltages in adjustable output configuration 788 800 812 mV VFB1_so Single Output mode FB voltage in adjustable output configuration 788 800 812 mV IFB1/2(LKG) FB input leakage current in dual output configuration VFB1/2 = 0.8 V 10 250 nA IFB1_so(LKG) FB input leakage current in single output configuration VFB = 0.8 V 10 250 nA FBSel-5v0 Voltage threshold for fixed 5.0V setting VCC-0.5 V FBSel-3v0 Resistor for fixed 3.3V setting 300 Ω FBSel-ext Minimum Thevenin Equivalent resistance of external FB divider option to select adjustable output voltage. 4 kΩ ERROR AMPLIFIER gm-S1 EA transconductance - single output mode VFB1 = VCOMP 625 1000 1300 µS ICOMP(src) EA source current - single output mode VCOMP = 1 V, VFB1 = 0.4 V 100 200 400 µA ICOMP(sink) EA sink current - single output mode VCOMP = 1 V, VFB1 = 0.8 V 100 200 500 µA SWITCHING FREQUENCY fSW1(FPWM) Switching frequency, FCCM operation RRT = 7.15 kΩ to AGND 1.9 2.1 2.3 MHz fSW2(FPWM) Switching frequency, FCCM operation RRT = 39.2 kΩ to AGND 360 410 450 kHz fADJ(FCCM) Adjustable switching frequency range RRT resistor from 6.81 kΩ to 158 kΩ to AGND 0.1 2.2 MHz fSS(int) Spread Spectrum switching frequency range RRT = 7.15 kΩ, RCONFIG= 73.2k Ω +-10% SYNCHRONIZATION VIH(sync) SYNCIN High-Level Threshold 1.35 1.6 V www.ti.com LMQ644A2-Q1 SNVSC42 – SEPTEMBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: LMQ644A2-Q1

7.5 Electrical Characteristics (continued)

TJ = –40°C to +150°C. Typical values are at TJ = 25°C and VIN = 13.5 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIL(sync) SYNCIN Low-Level Threshold 0.65 0.95 V VOH(sync) Sync output high voltage min 10 mA load 1.6 2.6 V VOL(sync) Sync output low voltage max 10 mA load 0.35 0.68 V fSYNC-0p4 Frequency sync range around 400kHz RRT = 39.2 kΩ to AGND 320 400 480 kHz tSYNC(min) Pulse width of external synchronization signal above VIH(sync) 100 ns tSYNC(max) Pulse width of low external synchronization signal below VIL(sync) 100 ns tSYNC-SW(delay) Delay from SYNC rising edge to SW rising edge - single output mode - secondary 115 ns STARTUP tSS(R) Internal fixed soft-start time - dual output mode From VVOSNS1/2= 0% (first SW pulse) to VVOSNS1/2 = 90% 2.7 4.5 7 ms tSS_Lockout(R) Time from first SW1/2 pulse to enable FPWM mode if output not in regulation - dual output mode 7 13 32 ms ISS(R) Soft-start charge current - single output mode VSS = 0 V 15 20 25 µA RSS(F) Soft-start discharge resistance - single output mode 10 27 Ω tEN EN1 (Single output mode) or EN1/EN2 (whichever first in dual output mode) HIGH to start of switching delay 600 900 µs POWER STAGE RDSON(HS) High-side MOSFET on-resistance VBOOT-SW = 3.3 V, IOUT = 1 A 37 75 mΩ RDSON(LS) Low-side MOSFET on-resistance VVCC = 3.3 V, IOUT = 1 A 23.9 50 mΩ tON(min) Minimum ON pulse width VIN = 20 V, IOUT = 2 A 50 65 ns tON(max) Maximum ON pulse width (dual output, single output primary) RRT = 7.15 kΩ 5 8 12 µs tON(max) Maximum ON pulse width (single output secondary) RRT = 7.15 kΩ 16 25 µs tOFF(min) Minimum OFF pulse width VIN = 4 V 80 110 ns BOOT CIRCUIT OVERCURRENT PROTECTION IHS(OC3) High-side peak current limit LMQ644A2-Q1 Peak current limit on HS FET when Duty Cycle approaches 0% 9 11 13.9 A ILS(OC3) Low-side valley current limit LMQ644A2-Q1 Valley current limit on LS FET 6.2 7.7 9 A ILS3(NOC) Low-side negative current limit LMQ644A2- Q1 Sinking current limit on LS FET 5 A ILPEAK3(min-0) Min peak inductor current at minimum duty cycle LMQ644A2-Q1 VVCC = 3.3 V, tpulse ≤ 100 ns 1 1.5 2.0 A ILPEAK3(min-100) Min peak inductor current at maximum duty cycle LMQ644A2-Q1 VVCC = 3.3 V, tpulse ≥ 1 µs 0.3 0.7 1.8 A VHiccup-FB Hiccup threshold on FB pin - dual output mode, adjustable output option LS FET On-time > 165 ns .25 0.3 0.35 V tHiccup-1 Wait time before entering Hiccup - single and dual output mode 126 128 130 Curent Limit cycles tHiccup-2 Hiccup time before re-start 50 88 ms POWER GOOD VPGTH-1 Power Good threshold (PG1/2) PGOOD low, VVOSNS1/2 rising 93% 95% 97% VPGTH-2 Power Good threshold (PG1/2) PGOOD high, VVOSNS1/2 falling 92% 94% 96% VPGTH-3 Power Good threshold (PG1/2) PGOOD high, VVOSNS1/2 rising 105% 107% 110% VPGTH-4 Power Good threshold (PG1/2) PGOOD low, VVOSNS1/2 falling 104% 106% 109% LMQ644A2-Q1 SNVSC42 – SEPTEMBER 2023 www.ti.com

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TJ = –40°C to +150°C. Typical values are at TJ = 25°C and VIN = 13.5 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tPGOOD(R) PG1/2 delay from VVOSNS1/2 valid to PGOOD high during startup VVOSNS1/2 = 3.3V 1.5 2.3 3 ms tPGOOD(F) PG1/2 delay from VVOSNS1/2 invalid to PGOOD low VVOSNS1/2 = 3.3V 25 45 70 µs IPG(LKG) PG1/2 pin Leakage current when open drain output is high VPG = 3.3 V 0.075 µA VPG-D(LOW) PG pin output low-level voltage for both channels IPG = 1 mA, VEN = 0 V. 400 mV RPG-1 Pull Down MOSFET Resistance IPG = 1 mA, VEN = 3.3 V. 30 90 Ω VIN(PG_VALID) Min VIN for valid PG output Pull up resistance on PG - RPG = 10 kΩ, Voltage Pull up on PG - VPULLUP_PG=3V, VPG-D (LOW)=0.4V 0.45 1.2 V THERMAL SHUTDOWN TJ(SD) Thermal shutdown threshold Temperature rising 168 °C TJ(HYS) Thermal shutdown hysteresis 10 °C www.ti.com LMQ644A2-Q1 SNVSC42 – SEPTEMBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: LMQ644A2-Q1

7.6 Typical Characteristics

Unless otherwise specified, VIN = 13.5 V. Temperature (°C) FB Voltage (V) -50 -25 0 25 50 75 100 125 150 0.796 0.797 0.798 0.799 0.8 0.801 0.802 0.803 0.804 Figure 7-1. Feedback Voltage Temperature (°C) Current (µ A) -50 -25 0 25 50 75 100 125 150 0.25 0.5 0.75 1.25 1.5 EN = 0 V Figure 7-2. Shutdown Supply Current Temperature (°C) RDS-ON (m) -50 -25 0 25 50 75 100 125 150 HS Switch LS Switch Figure 7-3. High-side and Low-side Switches RDS_ON Temperature (°C) Current Limit (A) -50 -25 0 25 50 75 100 125 150 Peak Valley Figure 7-4. High-side and Low-side Current Limits LMQ644A2 LMQ644A2-Q1 SNVSC42 – SEPTEMBER 2023 www.ti.com

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8 Detailed Description

8.1 Overview

The LMQ644xx is a wide-input, synchronous, buck DC/DC converter for high-current single or dual outputs. The device uses an interleaved, stackable, current-mode control architecture for easy loop compensation, fast transient response, excellent load and line regulation, and accurate current sharing stackable up to six phases for higher output currents up to 36 A. A high-side switch minimum on-time of 55 ns allows large step-down ratios, enabling the direct conversion from 12-V, 24-V, or automotive inputs to low-voltage rails for reduced system complexity and design cost. The LMQ644xx supports input voltage dips as low as 3 V, at nearly 100% duty cycle. If the minimum on-time or minimum off-time does not support the desired conversion ratio, the frequency is reduced. This action automatically allows regulation to be maintained during load dump and with very low dropout during cranking. Power the bias of LMQ644xx from the output of the converter for lower input quiescent current and power loss. Achieving 9- μA no-load quiescent current in dual output configuration to extend operating run-time in battery-powered systems. The LMQ644xx has been designed for low EMI. The device includes the following:

• Reduction of noise at the fundamental switching frequency through interleaving – To reduce input capacitor ripple current and EMI filter size, the device can be configured to operate in a stack of either two, four or six phases with corresponding phase shift interleave operation based on the number of phases. For example, in a 4 phase setup, a 90° out-of-phase clock output setup works well for cascaded, multi-channel, or multi-phase power stages. Phase relationship is maintained in light load operation for low output voltage ripple.
• Pin-enabled dual random spread spectrum (DRSS) – Dual Random Spread Spectrum (DRSS) frequency hopping is set to ±10% (typical), drastically reducing peak emissions through a combination of triangular and pseudorandom modulation.
• Symmetrical VIN pinout for low input inductance
• Operation over a frequency range above and below AM radio band – Resistor-adjustable switching frequency adjustable from 100 kHz to 2.2 MHz can be synchronized to an external clock source to eliminate beat frequencies in noise-sensitive applications.
• Internal input capacitors for EMI reduction – Each phase has two 22-nF input bypass capacitors configured in series for improved system reliability. Together, these features can eliminate shielding and other expensive EMI mitigation measures. The device also includes the following features:
• Internal fixed soft start or adjustable soft start using an external capacitor with monotonic start-up into prebiased loads
• Open-drain Power-Good flags with built-in delayed release for fault reporting and output monitoring
• Independent enable inputs
• Integrated VCC bias supply regulator
• Hiccup-mode overload protection
• Thermal shutdown protection with automatic recovery The LMQ644xx comes in a 5-mm × 4-mm Enhanced HotRod QFN 24-pin package with enlarged corner terminals for improved BLR and wettable flanks, allowing for optical inspection and allowing use in reliability- conscious environments www.ti.com LMQ644A2-Q1 SNVSC42 – SEPTEMBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: LMQ644A2-Q1

8.2 Functional Block Diagram

VREF 0.8V VREF SLOPE COMP RAMP 1/2 PWM1/2 STANDBY DRIVER CLK1/2 PFM/FPWM PG2 DEGLITCH 45ms PGUV PGOV CHANNEL 1/2 0.856 V 0.752 V FB2 DECODER FIXED or ADJ FAULT LOGIC 3.3 V 5 V COMP1/2 HICCUP FB2 150 mV Q Q R S DECODER DUAL or SINGLE CB1/2 CONFIG SYNCOUT on PG2 SYNC RT VIN1/2 SW1/2 PG2 / SYNCOUT VOSNS2 / COMP EN1/2 AGND VCC BIAS VIN1 Dither PFM / FPWM 2 / 4 / 6 phase 1 V SLOPE COMP RAMP 1/2 PLL and OSCILLATORS PGDN1/2 SERIESCAP 1/2 LS CURRENT SENSE HS CURRENT SENSE HS CURRENT SENSE 1/2 GND DUAL or SINGLE EXT_SS 20 mA FB2 / SS LS CURRENT SENSE 1/2 LS CURRENT LIMIT VALLEY FOLDBACK LS CURRENT LIMIT VALLEY FOLDBACK MUX FB2 COMP2 MUX SS DECODER FAULT LOGIC INT SS TIMER INTERNAL COMPENSATION LIMIT CURRENT MUX DUAL or SINGLE COMP1 DUAL or SINGLE VREF FB1 DECODER FIXED or ADJ FAULT LOGIC 3.3 V 5 V FB1 INTERNAL COMPENSATION LIMIT CURRENT FB1 VOSNS1 / BIAS SS DUAL or SINGLE COMP1 SS FB2 PG1 DEGLITCH 45ms PGUV PGOV 0.856 V 0.752 V GND FB1 PG1 EXT SS LMQ644A2-Q1 SNVSC42 – SEPTEMBER 2023 www.ti.com

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8.3 Feature Description

8.3.1 Input Voltage Range (VIN)

The LMQ644xx can start up from 3.5 V to 36 V, after start-up the input voltage range can extend down to 3 V. The device is intended for step-down conversions from 12-V automotive and 24-V industrial supply rails. The application circuit shows all the necessary components to implement an LMQ644xx based wide-V IN dual-output step-down regulator using a single supply. The LMQ644xx uses an internal LDO subregulator to provide a VCC bias rail for the gate drive and control circuits. VIN1 VIN2 PGND1 PGND2 BOOT1 BOOT2 SW1 SW2 BIAS / VOSNS1 VOSNS2 FB1 FB2 SYNC PG2 EN1 EN2 AGND RT VCC PG1 CONFIG L1 L2 VCC VIN1/2 = 6 V...36 V VOUT1 = 3.3 V IOUT = 6 A FSW = 2.1 MHz VOUT2 = 5.0 V IOUT = 6 A FSW = 2.1 MHz Figure 8-1. Dual-Output Regulator Schematic Diagram With Input Voltage Operating Range of 6 V to 36 V In high input voltage applications, take extra care to make sure the VIN and SW pins do not exceed their absolute maximum voltage rating of 42 V during line or load transient events. Voltage excursions that exceed the maximum ratings can damage the IC. Proceed carefully during PCB board layout and use high-quality input bypass capacitors to minimize voltage overshoot and ringing.

8.3.2 Enable EN Pin and Use as VIN UVLO

Apply a voltage less than 0.25 V to the EN1 pin to put the LMQ644xx into shutdown mode. In shutdown mode, the quiescent current drops to 0.5 µA (typical). Above this voltage but below the lower EN threshold, VCC is active but switching on SW1 and SW2 remains inactive. After EN1 is above V EN, the SW1 becomes active. EN2 controls switching on the second output SW2. In dual output configuration EN2 can be used to independantly turn off the second output voltage, but does not control entering shutdown mode. In single-output multi-phase configuration EN1 on primaries and secondaries must be tied together. In single output configuration EN1 must not be used to disable the secondary devices for phase shedding. EN2 of the primary and secondaries must be tied together and can be used to shutdown the secondary phases. The very high efficiency of the device in PFM operation eliminates the need to phase shed in most designs as phase of the secondaries is controlled even under PFM operation. The EN terminals cannot be left floating. The simplest way to enable the operation is to connect the EN pins to VIN. This action allows the self-start-up of the device when VIN drives the internal VCC above its UVLO level. www.ti.com LMQ644A2-Q1 SNVSC42 – SEPTEMBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: LMQ644A2-Q1

However, many applications benefit from employing an enable divider string, which establishes a precision input undervoltage lockout (UVLO). The precision UVLO can be used for the following:

• Sequencing
• Preventing the device from retriggering when used with long input cables
• Reducing the occurrence of deep discharge of a battery power source Note that EN thresholds are accurate. The rising enable threshold has 10% tolerance. Hysteresis is enough to prevent retriggering upon shutdown of the load (approximately 38%). The external logic output of another IC can also be used to drive the EN terminals, allowing system power sequencing. RENT RENB EN AGND VIN Figure 8-2. VIN UVLO Using the EN Pin Resistor values can be calculated using the equation below: R ENB = R ENT × V EN R V IN on − V EN R (1) V OFF = V IN on × 1 − V EN H (2) where
• VON = VIN turn-on voltage
• VOFF = VIN turn-off voltage

8.3.3 Output Voltage Selection and Soft Start

A voltage divider between the output voltage and the FB1 pin is used to create an adjustable output voltage from 0.8 to 20 V for the first buck converter. The thevenin impedance of the divider must be larger than 4 kohms, to correctly enter adjustable output voltage configuration. For lower output voltages a minimum of 10 kohms is recommended for RFBT to meet this requirement. For a fixed 5-V output connect FB1 to VCC through a 10 kohm resistor. For a fixed 3.3 V connect FB1 to AGND. For fixed output voltage configurations the first channel output voltage is sensed on pin 13 BIAS/VOSNS1. For dual-output voltage configuration, R CONFIG = 0 (spread spectrum disabled) or 121 kΩ (spread spectrum enabled). FB2 is configured in the same manner as FB1. A voltage divider between output voltage and the FB2 pin is used to create an adjustable output voltage from 0.8 to 20 V for the second buck converter. The thevenin impedance of the divider must be larger than 4 kohms, to correctly enter adjustable output voltage configuration. For lower output voltages a value of 10 kohms is recommended for R FBT to meet this requirement. For a fixed 5-V output, connect FB2 to VCC through a 10 kohm resistor. For a fixed 3.3 V connect FB2 to AGND. For fixed output voltage configurations, the second channel output voltage is sensed on pin 19. that is, VOSNS2. Current sharing between multiple buck channels can increase the current. For one device, single-output multi- phase operation can double the single buck current and provide up to 12 A. Using three devices allows six times the current up to 36 A. When the device is configured to single-output multi-phase operation (9.53 k Ω < RCONFIG < 93.1k Ω) , FB2 is re-configured to provide an adjustable soft start (SS). An external capacitor can be placed from this pin to ground to extend the internal soft-start time. The time can be calculated using the LMQ644A2-Q1 SNVSC42 – SEPTEMBER 2023 www.ti.com

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soft-start current of 20 µA (typical) charging the external capacitor to the reference voltage of 0.8 V (typical). As an example, a 220-nF capacitor provides a soft start of 8 ms after the initialization of the device. The pin must also be tied to FB2/SS of all other LMQ stacked devices for fault communication between primary and secondary devices. Faults, such as thermal shutdown, are communicated by pulling the pin low and stops switching for all devices. RFBT RFBB FB AGND VOUT Figure 8-3. Setting Output Voltage of Adjustable Versions The LMQ644xx uses a 0.8-V reference. The following equation can be used to determine R FBB for a desired output voltage and a given RFBT. Usually, RFBT is limited to a maximum value of 100 kΩ to prevent drifting due to PCB leakage under harsh conditions. To improve light load efficiency, a larger resistance of up to 1 M Ω can be used in cleaner environments, or the fixed output voltage options can be used under harsher conditions. R FBB k Ω = 0.8 × R FBT k Ω V O UT − 0.8 (3) In addition, a feedforward capacitor C FF can be used to optimize the transient response. Typical values are provided in the applications section and were selected based upon the top feedback resistor to place a zero slightly above the cross-over frequency.

8.3.4 SYNC Allows Clock Synchronization and Mode Selection

The SYNC pin can be used to select forced pulse width modulation (FPWM) or pulse frequency modulation (PFM). In FPWM the switching frequency remains constant at lighter output currents. In PFM the low-side FET is turned off when the inductor current goes negative and the frequency is reduced to improve efficiency under light-load conditions. Connect SYNC to AGND to enable PFM. Connect SYNC to VCC to operate the LMQ644xx in FPWM mode with continuous conduction at light loads. The SYNC pin can also be used to synchronize the internal oscillator to an external clock. When synchronized to an external clock the LMQ644xx operates in FPWM. The internal oscillator can be synchronized to a positive edge into the SYNC pin. The coupled edge voltage at the SYNC pin must exceed the SYNC amplitude threshold of V SYNCDH to trip the internal synchronization pulse detector. The minimum SYNC rising pulse and falling pulse durations must be longer than t PULSE_H and tPULSE_L respectively. The LMQ644xx switching action can be synchronized to an external clock from 200 kHz to 2.2 MHz. When synchronizing to an external clock, the R T pin must be used to set the internal frequency to a value close to that of the external clock. This action prevents large frequency changes in the event of loss of synchronization. It is also used to set the slope compensation for secondary devices. In single-output two-phase operation, the PG2/SYNC-OUT terminal of the primary can be left floating as clock information is shared internally. In single-output four-phase operation, the PG2/SYNC-OUT terminal of the primary must be connected to the SYNC pin of the secondary to clock all four phases 90 degrees out of phase. www.ti.com LMQ644A2-Q1 SNVSC42 – SEPTEMBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: LMQ644A2-Q1

In single-output six-phase operation, the PG2/SYNC-OUT terminal of the primary must be connected to the SYNC pin of the secondary device. The PG2/SYNC-OUT terminal of the secondary must be connected to the SYNC pin of the tertiary device. In this way, the devices operate all six phases 60 degrees out of phase. SYNC/MODEClock Range AGND Figure 8-4. Typical Implementation Allowing Synchronization Using the SYNC/MODE Pin VSYNCDH tPULSE_L tPULSE_H t VSYNCDL This image shows the conditions needed for detection of a synchronization signal. Figure 8-5. Typical SYNC/MODE Waveform

8.3.5 Clock Locking

After a valid synchronization signal is detected on the primary or dual output converter, a clock locking procedure is initiated. After approximately 32 pulses, the clock frequency abruptly changes to the frequency of the synchronization signal. While the frequency adjusts suddenly, phase is maintained so the clock cycle lying between operation at the default and synchronization frequencies is of intermediate length. There are no very long or very short pulses. After frequency is adjusted, phase is adjusted over a few tens of cycles so that rising synchronization edges correspond to rising the SW node pulses.

8.3.6 Adjustable Switching Frequency

The frequency is set using a resistor on the RT pin. A resistor to AGND is used to set the adjustable operating frequency. See below for resistor values. Note that if a resistor value falls outside of the recommended range, it can cause the device to stop switching. Do not apply a pulsed signal to this pin to force synchronization. If synchronization is needed, see the SYNC pin. R T k Ω = 16.4 F SW MHz − 0.633 (4) choice. Table 8-1. Typical RT values RT (kΩ) Frequency (kHz) 6.81 2206 7.15 2106 15.4 1005 LMQ644A2-Q1 SNVSC42 – SEPTEMBER 2023 www.ti.com

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Table 8-1. Typical RT values (continued) RT (kΩ) Frequency (kHz) 31.6 497.4 39.2 402 158 101 Figure 8-6. Setting Clock Frequency

8.3.7 Power-Good Output Voltage Monitoring

While the PG1/PG2 of the LMQ644xx resembles a standard power-good function, the functionality is designed to replace a discrete reset IC, reducing BOM cost. There are three major differences between the PG function and the normal power-good function seen in most regulators:

• A delay has been added for release of reset. See Table 8-2.
• PG output signals a fault (pulls its output to ground) while the part is disabled.
• PG continues to operate with input voltage as low as 1.2 V. Below this input voltage, PG output can be high impedance. For dual output configuration (R CONFIG = 0 or 121 k Ω), The PG1 is an open-drain and must be tied through a resistor to an external voltage, and pulls low if the monitors on FB1 or VOSNS1 trip. The PG2 flag is configured in the same manner as PG1 and monitors the second output at either FB2 or VOSNS2. For single-output multi-phase operation (9.53 k Ω < RCONFIG < 93.1 kΩ) , PG2 is re-configured as SYNC-OUT to provide a phase shifted clock to the secondary devices. In this configuration, the PG2/SYNC-OUT terminal of the primary device can be left floating for dual phase operation or tied to the SYNC pin of the secondary device for more than four-phases. For six-phase operation the PG2/SYNC-OUT pin of the secondary device is connected to the SYNC pin of the tertiary device. www.ti.com LMQ644A2-Q1 SNVSC42 – SEPTEMBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: LMQ644A2-Q1

High = Power Good Low = Fault VRESET-OV VRESET-UV VRESET-HYS-FALLING VRESET-HYS-RISING RESET Figure 8-7. PG Static Voltage Thresholds LMQ644A2-Q1 SNVSC42 – SEPTEMBER 2023 www.ti.com

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Glitches do not cause false operation nor reset timer < tdg trise-delay tdg VRESET-UV t t trise-delay VIN t VRESET-VALID VRESET-HYS-RISING VCC_UVLO VCC_UVLO_HYS < 20 V RESET RESET Figure 8-8. PG Timing Diagram (Excludes OV Events) www.ti.com LMQ644A2-Q1 SNVSC42 – SEPTEMBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: LMQ644A2-Q1

Table 8-2. Conditions that Cause PG to Signal a Fault (Pull Low) FAULT CONDITION INITIATED FAULT CONDITION ENDS (AFTER WHICH tRESET_ACT MUST PASS BEFORE RESET OUTPUT IS RELEASED) FB below VRESET_UV for longer than tRESET_FILTER FB above VRESET_UV + VRESET_HYST for longer than tRESET_FILTER FB above VRESET_OV for longer than tRESET_FILTER FB below VRESET_OV – VRESET_HYST for longer than tRESET_FILTER Junction temperature exceeds TSD_R Junction temperature falls below TSD_F (1) EN low tEN passes after EN becomes high(1) VIN falls low enough so that VCC falls below VCC_UVLO - VCC_UVLO_HYST. This value is called VIN_OPERATE. Voltage on VIN is high enough so that VCC pin exceed VCC_UVLO (1) (1) As an additional operational check, PG remains low during soft start. It is defined as until the lesser of either full output voltage reached or tSS2 has passed since initiation. This is true even if all other conditions in this table are met and tRESET_ACT has passed. Lockout during soft start does not require tRESET_ACT to pass before PG is released. The threshold voltage for the PG function is specified to take advantage of the availability of the internal feedback threshold to the PG circuit. This allows a maximum threshold of 96.5% of selected output voltage to be specified at the same time as 96% of actual operating point. The net result is a more accurate reset function while expanding the system allowance for transient response. See the output voltage error stack-up comparison in Figure 8-9. In addition to signaling a fault upon overvoltage detection (FB above V RESET_OV), the switch node is shut down and a small, approximately 1-mA pulldown is applied to the SW node. 112% 95% Typical SMPS upper specification Typical SMPS lower specification Selected output voltage 92% -1% -5.5% VGAURD is available margin for ripple and step loads 1.5% -1.5% VFB accuracy -4% 100% 96.5% Lowest VRESET_UV 94% 93% 98.5% 98% 101.5% -5.5% Lowest VOUT Lowest VFB Highest VFB -1% Highest VRESET_UV Lowest VOUT - VGAURD Typical VFB - VRESET_UV Low VFB case High VFB case VGAURD Typical VFB - VRESET_UV Figure 8-9. Reset Threshold Voltage Stack-Up

8.3.8 Internal LDO, VCC UVLO, and BIAS Input

The LMQ644xx uses VCC as its internal power supply. VCC is, in turn, powered from VIN or VOSNS1/BIAS. After the device is active power comes from VIN, if BIAS is less than approximately 3.1 V. Power comes from BIAS, if BIAS is more than 3.1 V. VCC is typically 3 V to 3.3 V under most conditions, but can be lower if VIN is very low. To prevent unsafe operation, VCC has a UVLO that prevents switching if the internal voltage is too low. See VCC_UVLO and VCC_UVLO_HYST . During start-up, VCC momentarily exceeds its normal operating voltage until VCC_UVLO is exceeded, then drops to its normal operating voltage. These UVLO values, when combined with the dropout of the LDO when powering the LMQ644xx, are used to derive minimum input operating voltage.

8.3.9 Bootstrap Voltage and VCBOOT-UVLO (CB1 and CB2 Pin)

The driver of the power switch (HS switch) requires bias higher than VIN when the HS switch is ON. The capacitors connected between CB1 and SW1 and CB2 and SW2 work as charge pumps to boost voltage on the CB terminals to (SW + VCC). The boot diode is integrated on the LMQ644xx die to minimize the physical design LMQ644A2-Q1 SNVSC42 – SEPTEMBER 2023 www.ti.com

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size. TI recommends a 100-nF capacitor rated for 10 V with X7R or better dielectric for the CBOOT capacitors. The boot (CB1 and CB2) rails have UVLO to protect the chip from operation with too little bias. This UVLO has a threshold of V BOOT_UVLO and is typically 2.1 V. If the CBOOT capacitor voltage drops below V BOOT_UVLO, then the device initiates a charging sequence using the low-side FET before attempting to turn on the high-side device.

8.3.10 CONFIG Device Configuration Pin

Several features are included to simplify compliance with CISPR 25 and automotive EMI requirements. To reduce input capacitor ripple current and EMI filter size, the device can be configured to operate in a stack of either two, four, or six phases with corresponding phase shift interleave operation based on the number of phases. For example, in a 4-phase setup, a 90° out-of-phase clock output setup works well for cascaded, multi-channel, or multi-phase power stages. Resistor-adjustable switching frequency as high as 2.2 MHz can be synchronized to an external clock source to eliminate beat frequencies in noise-sensitive applications. Optional spread spectrum modulation further improves the EMI signature. The CONFIG terminal is used to set up the device for either dual output or single output multi-phase operation. The spread spectrum can also be turned on and off with different resistor values. Table 8-3. RCONFIG Resistor Selection RCONFIG (kΩ) Mode Spread Spectrum

0 Dual output No

9.53 2 phase primary No 19.1 4 phase primary No 29.4 6 phase primary No

41.2 Secondary N/A

56.2 2 phase primary Yes 73.2 4 phase primary Yes 93.1 6 phase primary Yes

121 Dual output Yes

When configured in single output multi-phase operation, the VOSNS2 pin becomes the output of the error amplifier (COMP) and a resistor and capacitor are needed at this pin to compensate the control loop. R C = 11 kOhms, C C = 2.2 nF can be used in initial evaluation for many designs. Increasing the resistance results in higher loop gain and tends to require proportionately larger output capacitors. Decreasing the capacitance increases the loop response of the device, resulting in faster transients but can lower phase margin at the cross-over frequency and can require adjustments to the output capacitance. The table below has several settings for different output configurations. Table 8-4. Typical Bill of Materials MODE VOUT1 VOUT2 FREQUENCY COUT EACH PHASE CIN + CHF EACH PHASE L1, L2 RC CC DUAL 3.3 V 5 V 400 kHz 47 + 22 µF 2 × 10 µF + 1 × 100 nF 3.3 µH INTERNAL INTERNAL DUAL 3.3 V 5 V 2200 kHz 47 + 22 µF 1 × 10 µF + 1 × 100 nF 0.68 µH INTERNAL INTERNAL SINGLE 3.3 V 3.3 V 400 kHz 47 + 22 µF 2 × 10 µF + 1 × 100 nF 3.3 µH 11 kΩ 2.2 nF SINGLE 5 V 5 V 2200 kHz 47 + 22 µF 1 × 10 µF + 1 × 100 nF 1 µH 11 kΩ 2.2 nF www.ti.com LMQ644A2-Q1 SNVSC42 – SEPTEMBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: LMQ644A2-Q1

SYNC SYNC_OUT EN1 EN2 AGND RT VCC PG1 L1 L2 VIN1/2 = 3 V...36 V PGND3 CONFIG VOUT = 3.3 V IOUT = 8 A FSW = 2.2MHz High-Efficiency, Single Output 2-Phase Step-Down Converter VIN1 VIN2 PGND1 PGND2 BOOT1 BOOT2 SW1 SW2 FB1 EN1 EN2 VCC MODE L3 L4 Secondary VIN1/2 = 3 V...36 V VIN1 VIN2 PGND1 PGND2 BOOT1 BOOT2 SW1 SW2 BIAS / VOSNS1 COMP FB1 SS SYNC SYNC_OUT EN1 EN2 AGND RT VCC PG1 L1 L2 Primary VOUT = 3.3 V IOUT = 16 A VIN1/2 = 3 V...36 V COMP SS AGND RTPGND3 CONFIG PGND3 CONFIG SYNC SYNC_OUT BIAS / VOSNS1 FSW = 2.2 MHz High-Efficiency, Single Output 4-Phase Step-Down Converter LMQ644A2-Q1 SNVSC42 – SEPTEMBER 2023 www.ti.com

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VIN1/2 = 3 V...36 V VIN1 VIN2 PGND1 PGND2 BOOT1 BOOT2 SW1 SW2 BIAS / VOSNS1 COMP FB1 SS SYNC SYNC_OUT EN1 EN2 AGND RT VCC PG1 L1 L2 Primary VOUT = 3.3 V IOUT = 24 A VIN1/2 = 3 V...36 V COMP SS AGND RTPGND3 CONFIG PGND3 CONFIG SYNC SYNC_OUT BIAS / VOSNS1 FSW = 2.2 MHz VIN1 VIN2 PGND1 PGND2 BOOT1 BOOT2 SW1 SW2 FB1 EN1 EN2 VCC MODE L3 L4 Secondary VIN1/2 = 3 V...36 V COMP SS AGND RT PGND3 CONFIG SYNC SYNC_OUT BIAS / VOSNS1 High-Efficiency, Single Output 6-Phase Step-Down Converter

8.3.11 Spread Spectrum

Spread spectrum is configurable using the CONFIG pin. Spread spectrum eliminates peak emissions at specific frequencies by spreading these peaks across a wider range of frequencies than a part with fixed-frequency operation. The LMQ644xx implements a modulation pattern designed to reduce low frequency-conducted emissions from the first few harmonics of the switching frequency. The pattern can also help reduce the higher harmonics that are more difficult to filter, which can fall in the FM band. These harmonics often couple to the environment through electric fields around the switch node and inductor. The LMQ644xx uses a ±10% (typical) spread of frequencies which can spread energy smoothly across the FM and TV bands. The device implements Dual Random Spread Spectrum (DRSS). DRSS is a combination of a triangular frequency spreading pattern and pseudorandom frequency hopping. The combination allows the spread spectrum to be very effective at spreading the energy at the following:

• Fundamental switching harmonic with slow triangular pattern
• High frequency harmonics with additional psuedorandom jumps at the switching frequency The advantage of DRSS is its equivalent harmonic attenuation in the upper frequencies with a smaller fundamental frequency deviation. This reduces the amount of input current and output voltage ripple that is introduced at the modulating frequency. The spread spectrum is only available while the clocks of the The LMQ644xx are free running at their natural frequency. Any of the following conditions overrides the clock and can interfere with spread spectrum:
• The clock is slowed due to operation at low input voltage. This is operation in dropout.
• The clock is slowed under light load in auto mode. Note that if the device is operating in FPWM mode, spread spectrum is active, even if there is no load.
• The clock is slowed due to high input-to-output voltage ratio. This mode of operation is expected if on-time reaches minimum on-time. See the Electrical Characteristics.
• The clock is synchronized with an external clock.

8.3.12 Soft Start and Recovery From Dropout

When designing with the The LMQ644xx, slowed rise in output voltage due to recovery from dropout and soft start must be considered separate phenomena. Soft start is triggered by any of the following conditions:

• EN is used to turn on the device.
• Recovery from a hiccup waiting period; see Section 8.3.14.
• Recovery from shutdown due to overtemperature protection
• Power is applied to the VIN of the IC or the VCC UVLO is released. After soft start is triggered, the IC takes the following actions:
• The reference used by the IC to regulate output voltage is slowly ramped from zero. The net result is that output voltage, if previously 0 V, takes tSS to reach 90% of its desired value. www.ti.com LMQ644A2-Q1 SNVSC42 – SEPTEMBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: LMQ644A2-Q1

• Operating mode is set to auto, activating diode emulation. This allows start-up without pulling output low if there is a voltage already present on the output.
• Hiccup is disabled for the duration of soft start; see Section 8.3.14. All of these actions together provide start-up with limited inrush currents. They also allow the use of output capacitors and loading conditions that cause current to border on current limit during start-up without triggering hiccup. In addition, if output voltage is already present, output is not pulled down. See Figure 8-10. VEN VOUT Set Point EN and Output Voltages Time t VOUT V 90% of VOUT Set Point 0 V tSS2 tSS Triggering event If selected, FPWM is enabled after regulation but no later than tSS2tEN VEN VOUT Set Point EN and Output Voltages Time t VOUT V 90% of VOUT Set Point 0 V tSS2 tSS Triggering event If selected, FPWM is enabled after regulation but no later than tSS2tEN The left curves show soft start from 0 V. The right curves show soft starting behavior from a pre-biased or non-zero voltage. In either case, the output voltage reaches within 10% of the desired setpoint tSS time after soft start is initiated. During soft start, FPWM and hiccup are disabled. Both hiccup and FPWM are enabled after output reaches regulation or tSS2, whichever happens first. Figure 8-10. Soft-Start Operation Any time output voltage is more than a few percent low for any reason, output voltage ramps up slowly. This condition, called recovery from dropout, differs from soft start in three important ways:
• Hiccup is allowed only if output voltage is less than 0.4 times its set point. Note that during dropout regulation itself, hiccup is inhibited. See Section 8.3.14.
• FPWM mode is allowed during recovery from dropout. If output voltage were to suddenly be pulled up by an external supply, the The LMQ644xx can pull down on the output. Note that all the protections that are present during normal operation are in place, protecting the device if output is shorted to a high voltage or ground.
• The reference voltage is set to approximately 1% above that needed to achieve the current output voltage. It is not started from zero. Despite the name, recovery from dropout is active whenever output voltage is more than a few percent lower than the setpoint for long enough that:
• Duty factor is controlled by maximum on-time or
• When the part is operating in current limit. This primarily occurs under the following conditions:
• Dropout: When there is insufficient input voltage for the desired output voltage to be generated. See Section 8.4.3.5.
• Overcurrent that is not severe enough to trigger hiccup or if the duration is too short to trigger hiccup. See Section 8.3.14. LMQ644A2-Q1 SNVSC42 – SEPTEMBER 2023 www.ti.com

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V Whether output voltage falls due to high load or low input voltage, after the condition that causes output to fall below its setpoint is removed, output climbs at the same speed as during start-up. Even though hiccup does not trigger due to dropout, it can, in principal, be triggered during recovery if output voltage is below 0.4 times output the setpoint for more than 128 clock cycles during recovery. Figure 8-11. Recovery From Dropout

8.3.13 Overcurrent and Short-Circuit Protection

The LMQ644xx is protected from overcurrent conditions by cycle-by-cycle current limiting on both the high-side and the low-side MOSFETs. High-side MOSFET overcurrent protection is implemented by the nature of the peak current mode control. The HS switch current is sensed when the HS is turned on after a short blanking time. The HS switch current is compared to the output of the voltage regulation loop minus slope compensation, every switching cycle. Because the voltage loop has a maximum value and slope compensation increases with duty cycle, the HS current limit decreases with increased duty cycle such that it is reduced by 35% for high output to input voltage duty ratios. See Figure 8-12. Duty Cycle Command Current (A) Dual Vout HS Maximum Current Rated Maximum Current Figure 8-12. Maximum Current Allowed Through the HS FET - Function of Duty Cycle for LMQ644xx When the LS switch is turned on, the current going through it is also sensed and monitored. Like the high-side device, the low-side device turn-off is commanded by the voltage control loop. For a low-side device, turn-off is www.ti.com LMQ644A2-Q1 SNVSC42 – SEPTEMBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 27 Product Folder Links: LMQ644A2-Q1

prevented if current exceeds this value, even if the oscillator normally starts a new switching cycle. See Section called the low-side current limit; see the Electrical Characteristics for values. If the LS current limit is exceeded, the LS MOSFET stays on and the HS switch is not turned on. The LS switch is turned off after the LS current falls below its limit. The HS switch is turned on again as long as at least one clock period has passed since the last time the HS device has turned on. iL VSW IL-LS Inductor Current t t SW Voltage VIN Typically, tSW > Clock setting tON < tON_MAX IL-HS IOUT Figure 8-13. Current Limit Waveforms The net effect of the operation of high-side and low-side current limit is that the IC operates in hysteretic control. Because the current waveform assumes values between I L-HS and I L-LS, output current is close to the average of these two values unless duty cycle is very high. After operating in current limit, hysteretic control is used and current does not increase as output voltage approaches zero. If duty cycle is very high, current ripple must be very low to prevent instability; see Section 9.2.2.3. Because current ripple is low, the part is able to deliver full current unless dropout across device is less than 0.5V. The current delivered is very close to IL-LS. If overloaded, after the overload is removed, the device recovers as though in soft start; see Section 8.3.12. Note that hiccup can be triggered if output voltage drops below approximately 0.4 times the intended output voltage.

8.3.14 Hiccup

The LMQ644xx employs hiccup overcurrent protection to prevent overheating in the presence of a short circuit condition. In dual output mode the part enters Hiccup when all of the following conditions are met for 128 consecutive switching cycles:

• A time greater than tSS2 has passed since soft start has started; see Section 8.3.12.
• Output voltage is below approximately 0.4 times output setpoint.
• The part is not operating in dropout defined as having minimum off-time controlled by duty factor. In single output mode the part enters Hiccup when all of the following conditions are met for 128 consecutive switching cycles:
• COMP pin is at max of 1.1V
• The part is not operating in dropout defined as having minimum off-time controlled by duty factor. In hiccup mode, the device shuts itself down and attempts to soft start after t W. Hiccup mode helps reduce the device power dissipation under severe overcurrent conditions and short circuits. LMQ644A2-Q1 SNVSC42 – SEPTEMBER 2023 www.ti.com

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Figure 8-14. Inductor Current Bursts During Hiccup Figure 8-15. Short-Circuit Transient and Recovery

8.3.15 Thermal Shutdown

Thermal shutdown is a safety mechanism for the device that limits total power dissipation by turning off the internal switches when the a temperature sensor on the IC exceeds 168°C (typical). After thermal shutdown occurs, hysteresis prevents the device from switching until the temperature sensor temperature drops to approximately 159°C (typical). When the sensor temperature falls below 159°C (typical), the LMQ644xx attempts to soft start. While the sensor is close to the power FETs, it must not be used to determine maximum junction temperature of the device under load as there can be temperature gradients across the device. Instead thermal couples and other methods must be used to characterize thermal design in application. While the LMQ644xx is shut down due to high junction temperature, power continues to be provided to VCC. To prevent overheating from a short circuit applied to VCC, the LDO providing power to VCC has reduced current limit while the part is disabled due to high junction temperature. The LDO only provides a few milliamperes during thermal shutdown.

8.4 Device Functional Modes

8.4.1 Shutdown Mode

The EN pin provides electrical on and off control of the device. When the EN pin voltage is below 0.4 V, both the regulator and the internal LDO have no output voltage and the part is in shutdown mode. In shutdown mode, the quiescent current drops to typically 0.66 µA.

8.4.2 Standby Mode

The internal LDO has a lower EN threshold than the output of the regulator. The internal LDO regulates the VCC voltage at 3.3 V, typically when:

• The EN pin voltage is above 1.1 V (maximum) and
• The EN pin voltage is below the precision enable threshold for the output voltage. The precision enable circuitry is ON after VCC is above its UVLO. The internal power MOSFETs of the SW node remain off unless the voltage on the EN terminal goes above its precision enable threshold. The LMQ644xx also employs UVLO protection. If the VCC voltage is below its UVLO level, the output of the regulator is turned off.

8.4.3 Active Mode

The device is in active mode when the following occurs:

• The EN pin is above VEN.
• VIN is above VEN.
• VIN is high enough to satisfy the VIN minimum operating input voltage.
• No other fault conditions are present. See Section 8.3 for protection features. The simplest way to enable the operation is to connect EN to VIN, allowing self-start-up when the applied input voltage exceeds the minimum VIN_OPERATE. www.ti.com LMQ644A2-Q1 SNVSC42 – SEPTEMBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 29 Product Folder Links: LMQ644A2-Q1

In active mode, depending on the load current, input voltage, and output voltage, the LMQ644xx is in one of six sub-modes:

• Continuous conduction mode (CCM) with fixed switching frequency and peak current mode operation
• Discontinuous conduction mode (DCM) while in auto mode when the load current is lower than half of the inductor current ripple. If current continues to reduce, the device enters Pulse Frequency Modulation (PFM) which reduces the switch frequency to maintain regulation while reducing switching losses to achieve higher efficiency at light load.
• Minimum on-time operation while the on-time of the device needed for full-frequency operation at the requested low-duty cycle is not supported by TON_MIN
• Forced pulse width modulation (FPWM) similar to CCM with fixed-switching frequency, but extends the fixed frequency range of operation from full to no load
• Dropout mode when switching frequency is reduced to minimize dropout
• Recovery from dropout similar to other modes of operation except the output voltage setpoint is gradually moved up until the programmed setpoint is reached.

8.4.3.1 Peak Current Mode Operation

The following operating description of the LMQ644xx refers to Functional Block Diagram and the waveforms in Figure 8-16. Both supply a regulated output voltage by turning on the internal high-side (HS) and low-side (LS) NMOS switches with varying duty cycle (D). During the HS switch on-time, the SW terminal voltage, V SW, swings up to approximately V IN, and the inductor current, i L, increases with a linear slope. The HS switch is turned off by the control logic. During the HS switch off-time, t OFF, the LS switch is turned on. Inductor current discharges through the LS switch, forcing V SW to swing below ground by the voltage drop across the LS switch. The regulator loop adjusts the duty cycle to maintain a constant output voltage. D is defined by the on-time of the HS switch over the switching period: D = TON / (TON + TOFF). In an ideal buck converter where losses are ignored, D is proportional to the output voltage and inversely proportional to the input voltage: D = VOUT / VIN. iL VSW ILPK IOUT Iripple Inductor Current - IOUTÂ5DSLS D = t t SW Voltage tON tSWVIN tSW tON tOFF VOUT VIN Figure 8-16. SW Voltage and Inductor Current Waveforms in Continuous Conduction Mode (CCM) To get accurate DC load regulation, a voltage feedback loop is used. Peak and valley inductor currents are sensed for peak current mode control and current protection. The regulator operates with continuous conduction mode with constant switching frequency when load level is above one half of the minimum peak inductor current. The internally-compensated regulation network achieves fast and stable operation with small external components and low-ESR capacitors.

8.4.3.2 Auto Mode Operation

The LMQ644xx can have two behaviors while lightly loaded. One behavior, called auto mode operation, allows a seamless transition between normal current mode operation while heavily loaded and in highly-efficient light-load operation. The other behavior, called FPWM mode, maintains full frequency even when unloaded. Which mode LMQ644A2-Q1 SNVSC42 – SEPTEMBER 2023 www.ti.com

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the LMQ644xx operates in depends on the SYNC/MODE pin. When SYNC/MODE is high, the part is in FPWM. When SYNC/MODE is low, the part is in PFM. In auto mode, light-load operation is employed in the LMQ644xx at load lower than approximately 1/10th of the rated maximum output current. Light-load operation employs two techniques to improve efficiency:

• Diode emulation, which allows DCM operation
• Frequency reduction Note that while these two features operate together to create excellent light load behavior, they operate independently of each other.

8.4.3.2.1 Diode Emulation

Diode emulation prevents reverse current though the inductor, which requires a lower frequency needed to regulate given a fixed peak inductor current. Diode emulation also limits ripple current as frequency is reduced. Frequency is reduced when peak inductor current goes below I PEAK-MIN. With a fixed peak current, as output current is reduced to zero, frequency must be reduced to near zero to maintain regulation. iL VSW ILPK IOUT Inductor Current D = t t SW Voltage tON tSW VIN tSW tON tOFF tHIGHZ VOUT VIN In auto mode, the low-side device is turned off after inductor current is near zero. As a result, after output current is less than half of inductor ripple in CCM, the part operates in DCM. This is equivalent to saying that diode emulation is active. Figure 8-17. PFM Operation The LMQ644xx has a minimum peak inductor current setting in auto mode. That being said, when current is reduced to a low value with fixed input voltage, on-time is constant. Regulation is then achieved by adjusting frequency . This mode of operation is called PFM mode regulation.

8.4.3.3 FPWM Mode Operation

Like auto mode operation, FPWM mode operation during light-load operation is selected using the SYNC/MODE pin. In FPWM Mode, frequency is maintained while lightly loaded. To maintain frequency, a limited reverse current is allowed to flow through the inductor. Reverse current is limited by reverse current limit circuitry. See the Electrical Characteristics for reverse current limit values. www.ti.com LMQ644A2-Q1 SNVSC42 – SEPTEMBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 31 Product Folder Links: LMQ644A2-Q1

D = t t SW Voltage tON tSW VIN tSW tON tOFF VOUT VIN FPWM mode Continuous Conduction (CCM) is possible even if IOUT is less than half of Iripple. Figure 8-18. FPWM Mode Operation In FPWM mode, frequency reduction is still available if output voltage is high enough to command minimum on-time, even while lightly loaded. This allows good behavior during faults which involves the output being pulled up.

8.4.3.4 Minimum On-time (High Input Voltage) Operation

The LMQ644xx continues to regulate output voltage. This is true even if the input-to-output voltage ratio requires an on-time less than the minimum on-time of the chip with a given clock setting. This is accomplished using valley current control. At all times, the compensation circuit dictates both a maximum peak inductor current and a maximum valley inductor current. If, for any reason, valley current is exceeded, the clock cycle is extended until valley current falls below that determined by the compensation circuit. If it is not operating in current limit, the maximum valley current is set above the peak inductor current. This prevents valley control from being used unless there is a failure to regulate using peak current only. If the input-voltage to output-voltage ratio is too high, even though current exceeds the peak value dictated by compensation, the high-side device cannot be turned off quickly enough to regulate output voltage. See t ON_MIN in the Electrical Characteristics. As a result, the compensation circuit reduces both peak and valley current. After a low enough current is selected by the compensation circuit, valley current matches that being commanded by the compensation circuit. Under these conditions, the low-side device is kept on and the next clock cycle is prevented from starting until inductor current drops below the desired valley current. Because on-time is fixed at its minimum value, this type of operation resembles that of a device using a COT control scheme. See Figure 8-19. LMQ644A2-Q1 SNVSC42 – SEPTEMBER 2023 www.ti.com

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• IOUTÂ5DSLS D = t t SW Voltage tON tSWVIN tSW > Clock setting tON = tON_MIN tOFF VOUT VIN In valley control mode, the minimum inductor current is regulated, not peak inductor current. Figure 8-19. Valley Current Mode Operation

8.4.3.5 Dropout

Dropout operation is defined as any input-to-output voltage ratio that requires frequency to drop to achieve the needed duty factor. At a given clock frequency, duty factor is limited by minimum off-time. After this limit is reached, if clock frequency is maintained, output voltage falls. Instead of allowing the output voltage to drop, the LMQ644xx extends on-time past the end of the clock cycle until the required peak inductor current is achieved. The clock can start a new cycle after peak inductor current is achieved or after a pre-determined maximum on-time, tON-MAX, of approximately 9 µs passes. As a result, after the needed duty factor cannot be achieved at the selected clock frequency due to the existence of a minimum off-time, frequency drops to maintain regulation. If input voltage is low enough that the output voltage cannot be regulated even with an on-time of tON_MAX, output voltage drops to slightly below input voltage. iL VSW IOUT Iripple Inductor Current - IOUTÂ5DSLS D = t t SW Voltage tON tSWVIN tSW > Clock setting tOFF = tOFF_MIN tON < tON_MAX VOUT VIN ILPK This image shows the switching waveforms while in dropout. Inductor current takes longer than a normal clock to reach the desired peak value. As a result, frequency drops. This frequency drop is limited by tON_MAX. Figure 8-20. Dropout Waveforms

8.4.3.6 Recovery from Dropout

In some applications, input voltage can drop below the desired output voltage then recover to a higher value suddenly. With most regulators, the sudden increase in input voltage results in output voltage rising at a rate limited only by current limit until regulation is achieved. As input voltage reaches the desired output voltage, there is overshoot due to wind up in the control loop. This overshoot can be large in applications that have small www.ti.com LMQ644A2-Q1 SNVSC42 – SEPTEMBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 33 Product Folder Links: LMQ644A2-Q1

output capacitors and light loads. Also, large inrush currents can cause large fluctuations on the input line after the regulator starts regulating the output voltage. This typically requires less current than during this initial inrush. The LMQ644xx greatly reduces inrush current and overshoot. This is done by engaging the soft-start circuit whenever the input voltage suddenly rises, after dipping low enough to cause the output voltage to droop. To prevent this feature from accidentally engaging, output voltage must fall more than 1% to engage this feature. Also, this feature engages only if operating in dropout or current limit, preventing interference with normal transient response but allowing several percent overshoot while engaging. If output voltage is very close to its desired level, overshoot is reduced by inductor current not having time to rise to a high level before regulation starts. VIN VOUT Set Point Input and Output Voltage Slope the same as during soft start Time t VOUT V Figure 8-21. When Output Voltage Falls, It Recovers Slowly Preventing Overshoot and Large Inrush Currents

8.4.3.7 Other Fault Modes

Fault modes and their description can be found in Section 8.3 of this data sheet. LMQ644A2-Q1 SNVSC42 – SEPTEMBER 2023 www.ti.com

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9 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

9.1 Application Information

The LMQ644xx step-down DC-to-DC converter is typically used to convert a higher DC voltage to a lower DC voltage with a maximum output current up to 12 A per device. Maximum load current is dependent on the thermal environment of the design. The thermal performance curves for the EVM can be used as a starting point for determining load capability at different ambient temperatures. The following design procedure can be used to select components for the LMQ644xx.

9.2 Typical Application

Figure 9-1 and Figure 9-2 show typical application circuits for the LMQ644xx. The following design procedure can be used to select components for the LMQ644xx. This device is designed to function over a wide range of external components and system parameters. However, the internal compensation is optimized for a certain range of external inductance and output capacitance. As a quick start guide, Table 9-2 provides typical component values for some of the most common configurations. The values given in the table are typical. Other values can be used to enhance certain performance criterion as required by the application. Note that for this eQFN package, the input capacitors are split and placed on either side of the package. See Section 9.2.2.5 for more details. VIN1 VIN2 PGND1 PGND2 BOOT1 BOOT2 SW1 SW2 BIAS / VOSNS1 COMP FB1 SS SYNC SYNC_OUT EN1 EN2 AGND RT VCC PG1 L1 L2 PGND3 CONFIG VOUT = 3.3 V IOUT = 12 A FSW = 400 kHz Figure 9-1. Example Application Circuit - 400-kHz Single Adjustable Output www.ti.com LMQ644A2-Q1 SNVSC42 – SEPTEMBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 35 Product Folder Links: LMQ644A2-Q1

VIN1/2 = 6 V...36 V VOUT1 = 3.3 V IOUT = 6 A FSW = 2.1 MHz VOUT2 = 5.0 V IOUT = 6 A FSW = 2.1 MHz Figure 9-2. Example Application Circuit - 2.1-MHz Dual Fixed Output

9.2.1 Design Requirements

Table 9-1 provides the parameters for our detailed design procedure example for Figure 9-2: Table 9-1. Detailed Design Parameters DESIGN PARAMETER EXAMPLE VALUE Input voltage 13.5 V (6 V to 36 V) Output voltage 3.3 and 5 V fixed

9.2.2 Detailed Design Procedure

The following design procedure refers to Figure 9-2, and Table 9-1.

9.2.2.1 Choosing the Switching Frequency

The choice of switching frequency is a compromise between conversion efficiency and overall design size. Lower switching frequency implies reduced switching losses, usually resulting in less power dissipated in the IC. Lower power dissipated in the IC results in higher system efficiency and a lower IC temperature. However, higher switching frequency allows the use of smaller inductors and output capacitors, hence, a more compact design. Many applications require that the AM band be avoided. These applications tend to operate at around 400 kHz (below the AM band), or 2.1 MHz (above the AM band). For 400 kHz, a 39.2k 1% resistor can be used. For this 2100 kHz example, a 7.15k 1% resistor is selected.

9.2.2.2 Setting the Output Voltage

The output regulation target can be programmed to a fixed 3.3 V by connecting FB to AGND, or a fixed 5.0-V output by connecting FB to VCC through a 10-kΩ resistor. Also, the output voltage of the LMQ644xx is externally adjustable using a resistor divider network. The divider network is comprised of the top and bottom feedback resistors, R FBT and R FBB, and closes the loop between the output voltage and the converter. The converter regulates the output voltage by holding the voltage at the internal error amplifier input equal to the internal LMQ644A2-Q1 SNVSC42 – SEPTEMBER 2023 www.ti.com

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reference voltage, V FB = 0.8 V. The total resistance of the divider is a compromise between excessive noise pickup and excessive loading of the output. Lower resistance values reduce noise sensitivity but also reduce the light-load efficiency. The recommended value for RFBT is around 100 kΩ with a maximum value of 1 MΩ.

9.2.2.3 Inductor Selection

The main parameters for selecting the inductor are the inductance and saturation current. The inductance is based on the desired peak-to-peak ripple current. The inductance is normally chosen to be in the range of 20% to 50% of the maximum output current. Experience shows that a good value for inductor ripple current is 30% of the maximum load current for systems with a fixed input voltage. This example uses VIN = 13.5 V, which is closer to the nominal voltage of a 12-V car battery. When selecting the ripple current for applications with much smaller maximum load than the maximum available from the device, the maximum device current must be used for this calculation. Equation 5 can be used to determine the value of the inductance. The constant K is the percentage of peak-to-peak inductor current ripple to rated output current. For this 6-A, 2100-kHz, 3.3-V example, K = 0.25 is chosen and the closest standard value of 1 μH was selected. L = V OUT V IN × V I N − V O U T f SW × K × I OUT _ MAX (5) Ideally, the saturation current rating of the inductor must be at least as large as the high-side switch current limit, IHS. This rating makes sure that the inductor does not saturate, even during a soft-short condition on the output. A hard short causes the LMQ644xx to enter hiccup mode (see Section 8.3.14). A soft short can hold the output current near the current limit without triggering hiccup. When the inductor core material saturates, the inductance can fall to a very low value, causing the inductor current to rise very rapidly. Although the valley current limit, I LS, is designed to reduce the risk of current runaway, a saturated inductor can cause the current to rise to high values very rapidly. This event can lead to component damage, so the inductor not saturating is crucial. Inductors with a ferrite core material have very hard saturation characteristics, but usually have lower core losses than powdered iron cores. Powered iron cores exhibit a soft saturation, allowing some relaxation in the saturation current rating of the inductor. However, they have more core losses at frequencies typically above 1 MHz. To avoid subharmonic oscillation, the inductance value must not be less than that given in Equation 6. The maximum inductance is limited by the minimum current ripple required for the current mode control to perform correctly. As a rule-of-thumb, the minimum inductor ripple current must be no less than about 10% of the device maximum rated current under nominal conditions. L > V OUT f SW × I RATED (6)

9.2.2.4 Output Capacitor Selection

The output capacitor value and ESR determine the output voltage ripple and load transient performance. The output capacitor is usually limited by the load transient requirements rather than the output voltage ripple. Table 9-2 can be used to find capacitor values for COUT and CFF for a few common applications. Note that 4.99-kΩ RFF can be used in series with C FF to limit high frequency noise into the FB pin. In this example, 3.3 V OUT and 2.1 MHz, good transient performance is desired. From the table select 3 × 22-µF ceramic as the output capacitor and 10 pF as C FF. For other voltage a frequency combinations Cout can be estimated using the desired crossover frequency (fx) and output voltage. Crossover is usually limited by the sampling pole created from the switching frequency. Thus, the crossover is usually a percentage such as 1/10th the switching frequency. Table 9-2. Selected Output Capacitor and CFF Values FREQUENCY IOUT TRANSIENT PERFORMANCE 3.3-V OUTPUT 5-V OUTPUT COUT (per phase) CFF COUT CFF 400 kHz 6 A Minimum 3 × 47-µF ceramic 2 × 47-µF ceramic 400 kHz 6 A Better Transient 4 × 47-µF ceramic 10 pF 3 × 47-µF ceramic 10 pF

2.1 MHz 6 A Minimum 3 × 22-µF ceramic 2 × 22-µF ceramic

2.1 MHz 6 A Better Transient 4 × 22-µF ceramic 10 pF 3 × 22-µF ceramic 10 pF

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9.2.2.5 Input Capacitor Selection

The ceramic input capacitors provide a low impedance source to the regulator in addition to supplying the ripple current and isolating switching noise from other circuits. A minimum of 10- μF ceramic capacitance is required at each input/ground pin pair of the LMQ644xx. Use 2 x 10- μF ceramic capacitance or more for better EMI performance. This must be rated for at least the maximum input voltage that the application requires. It is preferable to have twice the maximum input voltage to reduce DC bias derating. This capacitance can be increased to help reduce input voltage ripple and maintain the input voltage during load transients. In addition, a small case size (0603 or 0402) ceramic capacitor can be used at each input/ground pin pair, VIN1/PGND1 and VIN2/PGND2. The capacitor must also have an X7R or better dielectric. Choose the highest capacitor value with these parameters. This provides a high frequency bypass to reduce switch-node ring and electromagnetic interference emissions. The LMQ644xx-Q1 also has two sets of internal capacitors to further improve bypassing. Each capacitor set is configured in series, so that in the unlikely scenario of a capacitor failure as a short, the second series capacitor can withstand the full input voltage and maintain operation. The eQFN (RXA) package provides two input voltage pins and two power ground pins on opposite sides of the package. This allows the input capacitors to be split and placed optimally with respect to the internal power MOSFETs, thus improving the effectiveness of the input bypassing. This example places two 10- μF, 50-V, 1206, X7R ceramic capacitors and two 0.1-μF, 50-V, 0402, X7R ceramic capacitors at each VIN/PGND pin pair. Often, using an electrolytic capacitor on the input in parallel with the ceramics is desirable. This action is especially true if long leads/traces are used to connect the input supply to the regulator. The moderate ESR of this capacitor can help dampen ringing on the input supply caused by the inductance of the long power leads. The use of this additional capacitor also helps with momentary voltage dips caused by input supplies with unusually high impedance. Most of the input switching current passes through the ceramic input capacitors. The approximate worst case RMS value of this current can be calculated with Equation 7 . This value must be checked against the manufacturers' maximum ratings. I RM S ≅ I OUT × V OUT V IN (7)

9.2.2.6 BOOT Capacitor

The LMQ644xx requires a bootstrap capacitor connected between the CBOOT pin and the SW pin. This capacitor stores energy which is used to supply the gate drivers for the power MOSFETs. TI recommends a high-quality, 100-nF ceramic capacitor with a rating of at least 10 V.

9.2.2.7 VCC

The VCC pin is the output of the internal LDO used as a supply to the internal control circuits of the regulator. This output requires a 1- μF, 10-V, X7R or similar, 0603 or similar ceramic capacitor connected from VCC to AGND for proper operation. Generally avoid loading this output with any external circuitry. However, this output can be used to supply the pullup for the PG pin (see Section 8.3.7) as well as configuring the FB pin for fixed output voltages. A pullup resistor with value of 100 k Ω is a good choice in this case. The nominal output voltage on VCC is 3.3 V.

9.2.2.8 CFF and RFF Selection

A feedforward capacitor, C FF, on the order of tens of picofarads and no bigger than 15 nF, can be used to improve phase margin and transient response of circuits which have output capacitors with low ESR and tight voltage margin requirements. Because this CFF capacitor can conduct noise from the output of the circuit directly to the FB node of the IC, a 4.99-k Ω resistor, R FF, can be placed in series with C FF to lower high frequency susceptibility when it is used. If the ESR zero of the output capacitor is below 200 kHz, no C FF must be used. In general the Cff capacitor can be sized to add phase boost slightly above the desired crossover frequency. C FF = 1 2 × π × R FBT × f X × 1.5 (8) LMQ644A2-Q1 SNVSC42 – SEPTEMBER 2023 www.ti.com

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If output voltage is less than 2.5 V, CFF has little effect, so it can be omitted. If output voltage is greater than 14 V, CFF must be used cautiously because it can easily introduce too much gain at higher frequencies. If 1 MΩ is selected for R FBT, then a feedforward capacitor C FF is usually required to offset parasitic capacitance in PCB construction.

9.2.2.9 SYNCHRONIZATION AND MODE

The SYNC pin allows you to synchronize the converter to an external clock voltage (SYNC). The pin also allows the selection between two modes. The following are the selectable modes:

• Forced pulse width modulation (FPWM) operation, which operates at a fixed frequency at all loads in typical operation
• Auto mode which automatically switches to pulse-frequency modulation (PFM) at light loads to improve light-load efficiency Connect the SYNC pin to VCC through a 10 kOhm resistor for FPWM. Connect to ground for PFM. You can also apply a clock signal to synchronize the switching frequency to an external clock. See Section 8.3.4 for more information.

9.2.2.10 External UVLO

In some cases, the user can need an input undervoltage lockout (UVLO) level different than that provided internal to the device. This can be accomplished by using the circuit shown in Figure 8-2. The input voltage at which the device turns on is designated V ON while the turn-off voltage is V OFF. First, a value for R ENB is chosen in the range of 10 kΩ to 100 kΩ, then Equation 1 is used to calculate RENT and VOFF.

9.2.2.11 Typical Thermal Performance

As with any power conversion device, the LMQ644xx dissipates internal power while operating. The effect of this power dissipation is to raise the internal temperature of the converter above ambient temperature. The internal die temperature (TJ) is a function of the following:

• Ambient temperature
• Power loss
• Effective thermal resistance, RθJA of the device
• PCB layout The maximum internal die temperature for the LMQ644xx must be limited to 150°C. This establishes a limit on the maximum device power dissipation and, therefore, the load current. Equation 9 shows the relationships between the important parameters. Larger ambient temperatures (T A) and larger values of R θJA reduce the maximum available output current. For low ambient temperature designs the converter efficiency can be estimated by using the curves provided in the Application Curves section. If the desired operating conditions cannot be found in one of the curves, then the junction temperature can be roughly estimated using the EVM thermal performance as a starting point. Alternatively, the EVM can be adjusted to match the desired application requirements and the efficiency can be measured directly. The correct value of R θJA is more difficult to estimate. As stated in the Semiconductor and IC Package Thermal Metrics application report , the JEDEC value of R θJA given in the electrical characteristics table is not always valid for design purposes and must not be used to estimate the thermal performance of the device in a real application. The values reported in the electrical characteristics table were measured under a specific set of conditions that are rarely obtained in an actual application. I O UT _ MAX = T J − T A R θJ A × η 1 − η × 1 V OUT (9) where
• η = efficiency
• TA = ambient temperature
• TJ = junction temperature
• RθJA = the effective thermal resistance of the IC junction to the air, mainly through the PCB www.ti.com LMQ644A2-Q1 SNVSC42 – SEPTEMBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 39 Product Folder Links: LMQ644A2-Q1

The effective RθJA is a critical parameter and depends on many factors (just to mention a few of the most critical parameters:

• Power dissipation
• Air temperature
• Airflow
• PCB area
• Copper heat-sink area
• Number of thermal vias under or near the package
• Adjacent component placement A typical curve of maximum output current versus ambient temperature is shown in Figure 9-3 and Figure 9-4 for a good thermal layout. This data is for the LMQ644A2 evaluation board . It must be remembered that the data given in these graphs are for illustration purposes only, and the actual performance in any given application depends on all of the previously mentioned factors. AMBIENT TEMPERATURE (C) IOUT2(A) 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 0.5 1.5 2.5 3.5 4.5 5.5 6.5 LMQ644A2 EVM VIN= 12 V, FSW= 400 kHz VOUT1= 3.3 V, VOUT2= 5 V No Airflow IOUT2@ IOUT1= 6A IOUT2@ IOUT1= 4A IOUT2@ IOUT1= 1A Figure 9-3. Typical Output Current versus Ambient Temperature, VIN = 12 V FSW = 400 kHz, Dual Output AMBIENT TEMPERATURE (C) IOUT2(A) 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 0.5 1.5 2.5 3.5 4.5 5.5 6.5 LMQ644A2 EVM VIN= 24 V, FSW= 400 kHz VOUT1= 3.3 V, VOUT2= 5 V No Airflow IOUT2@ IOUT1= 6A IOUT2@ IOUT1= 4A IOUT2@ IOUT1= 1A Figure 9-4. Typical Output Current versus Ambient Temperature, VIN = 24 V FSW = 400 kHz, Dual Output LMQ644A2-Q1 SNVSC42 – SEPTEMBER 2023 www.ti.com

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9.2.3 Application Curves

Unless otherwise specified, the following conditions apply: Device: LMQ644A2, VIN = 13.5 V, TA = 25°C. The circuit is shown in Figure 9-1, and Figure 9-2 with the appropriate BOM from Table 9-3. Output Current [A] Efficiency [%] V OUT =5V F SW =400kHz AUTO 4040 100 V IN =8V V IN =12V V IN =16V V IN =24V V IN =36V VOUT = 5 V FSW = 400 kHz Auto mode Single Output Figure 9-9. Efficiency Output Current [A] Efficiency [%] V OUT =5V F SW =400kHz AUTO 0 1 2 3 4 5 6 7 8 9 10 11 12 100 V IN =8V V IN =12V V IN =16V V IN =24V V IN =36V VOUT = 5 V FSW = 400 kHz Auto mode Single Output Figure 9-10. Efficiency Output Current [A] Efficiency [%] V OUT =5V F SW =400kHz FPWM 0 1 2 3 4 5 6 7 8 9 10 11 12 100 V IN =8V V IN =12V V IN =16V V IN =24V V IN =36V VOUT = 5 V FSW = 400 kHz FPWM mode Single Output Figure 9-11. Efficiency VOUT = 3.3 V FSW = 400 kHz Auto mode Single Output Figure 9-12. Efficiency Output Current [A] Efficiency [%] V OUT =3.3V F SW =400kHz AUTO 0 1 2 3 4 5 6 7 8 9 10 11 12 100 V IN =8V V IN =12V V IN =16V V IN =24V V IN =36V VOUT = 3.3 V FSW = 400 kHz Auto mode Single Output Figure 9-13. Efficiency Output Current [A] Efficiency [%] V OUT =3.3V F SW =400kHz FPWM 0 1 2 3 4 5 6 7 8 9 10 11 12 100 V IN =8V V IN =12V V IN =16V V IN =24V V IN =36V VOUT = 3.3 V FSW = 400 kHz FPWM mode Single Output Figure 9-14. Efficiency LMQ644A2-Q1 SNVSC42 – SEPTEMBER 2023 www.ti.com

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9.2.3 Application Curves (continued)

Unless otherwise specified, the following conditions apply: Device: LMQ644A2, VIN = 13.5 V, TA = 25°C. The circuit is shown in Figure 9-1, and Figure 9-2 with the appropriate BOM from Table 9-3. Output Current [A] Efficiency [%] V OUT =5V F SW =2.1MHz AUTO 4040 100 V IN =8V V IN =12V V IN =16V V IN =24V V IN =36V VOUT = 5 V FSW = 2.1 MHz Auto mode Single Output Figure 9-15. Efficiency Output Current [A] Efficiency [%] V OUT =5V F SW =2.1MHz AUTO 0 1 2 3 4 5 6 7 8 9 10 11 12 100 V IN =8V V IN =12V V IN =16V V IN =24V V IN =36V VOUT = 5 V FSW = 2.1 MHz Auto mode Single Output Figure 9-16. Efficiency Output Current [A] Efficiency [%] V OUT =5V F SW =2.1MHz FPWM 0 1 2 3 4 5 6 7 8 9 10 11 12 100 V IN =8V V IN =12V V IN =16V V IN =24V V IN =36V VOUT = 5 V FSW = 2.1 MHz FPWM mode Single Output Figure 9-17. Efficiency Output Current [A] Efficiency [%] V OUT =3.3V F SW =2.1MHz AUTO 4040 100 V IN =8V V IN =12V V IN =16V V IN =24V V IN =36V VOUT = 3.3 V FSW = 2.1 MHz Auto mode Single Output Figure 9-18. Efficiency Output Current [A] Efficiency [%] V OUT =3.3V F SW =2.1MHz AUTO 0 1 2 3 4 5 6 7 8 9 10 11 12 100 V IN =8V V IN =12V V IN =16V V IN =24V V IN =36V VOUT = 3.3 V FSW = 2.1 MHz Auto mode Single Output Figure 9-19. Efficiency Output Current [A] Efficiency [%] V OUT =3.3V F SW =2.1MHz FPWM 0 1 2 3 4 5 6 7 8 9 10 11 12 100 V IN =8V V IN =12V V IN =16V V IN =24V V IN =36V VOUT = 3.3 V FSW = 2.1 MHz FPWM mode Single Output Figure 9-20. Efficiency www.ti.com LMQ644A2-Q1 SNVSC42 – SEPTEMBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 43 Product Folder Links: LMQ644A2-Q1

Unless otherwise specified, the following conditions apply: Device: LMQ644A2, VIN = 13.5 V, TA = 25°C. The circuit is shown in Figure 9-1, and Figure 9-2 with the appropriate BOM from Table 9-3. Output Current [A] Efficiency [%] V OUT =5V F SW =2.1MHz AUTO 4040 100 V IN =8V V IN =12V V IN =16V V IN =24V V IN =36V VOUT = 5 V FSW = 2.1 MHz Auto mode Dual Output Figure 9-21. Efficiency Output Current [A] Efficiency [%] V OUT =5V F SW =2.1MHz AUTO 0 1 2 3 4 5 6 100 V IN =8V V IN =12V V IN =16V V IN =24V V IN =36V VOUT = 5 V FSW = 2.1 MHz Auto mode Dual Output Figure 9-22. Efficiency Output Current [A] Efficiency [%] V OUT =5V F SW =2.1MHz FPWM 0 1 2 3 4 5 6 100 V IN =8V V IN =12V V IN =16V V IN =24V V IN =36V VOUT = 5 V FSW = 2.1 MHz FPWM mode Dual Output Figure 9-23. Efficiency Output Current [A] Efficiency [%] V OUT =3.3V F SW =2.1MHz AUTO 4040 100 V IN =8V V IN =12V V IN =16V V IN =24V V IN =36V VOUT = 3.3 V FSW = 2.1 MHz Auto mode Dual Output Figure 9-24. Efficiency Output Current [A] Efficiency [%] V OUT =3.3V F SW =2.1MHz AUTO 0 1 2 3 4 5 6 100 V IN =8V V IN =12V V IN =16V V IN =24V V IN =36V VOUT = 3.3 V FSW = 2.1 MHz Auto mode Dual Output Figure 9-25. Efficiency Output Current [A] Efficiency [%] V OUT =3.3V F SW =2.1MHz FPWM 0 1 2 3 4 5 6 100 V IN =8V V IN =12V V IN =16V V IN =24V V IN =36V VOUT = 3.3 V FSW = 2.1 MHz FPWM mode Dual Output Figure 9-26. Efficiency LMQ644A2-Q1 SNVSC42 – SEPTEMBER 2023 www.ti.com

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Unless otherwise specified, the following conditions apply: Device: LMQ644A2, VIN = 13.5 V, TA = 25°C. The circuit is shown in Figure 9-1, and Figure 9-2 with the appropriate BOM from Table 9-3. VOUT = 3.3 V FSW = 2.1 MHz FPWM mode Single Output Figure 9-27. Load and Line Regulation Output Current [A] Output Voltage [V] V OUT =3.3V F SW =2.1MHz AUTO 3.25 3.3 3.35 V IN =8V V IN =12V V IN =24V VOUT = 3.3 V FSW = 2.1 MHz Auto mode Single Output Figure 9-28. Load and Line Regulation Output Current [A] Output Voltage [V] V OUT =3.3V F SW =2.1MHz FPWM 0 1 2 3 4 5 6 3.25 3.3 3.35 V IN =8V V IN =12V V IN =24V VOUT = 3.3 V FSW = 2.1 MHz FPWM mode Dual Output Figure 9-29. Load and Line Regulation Output Current [A] Output Voltage [V] V OUT =3.3V F SW =2.1MHz AUTO 3.25 3.3 3.35 V IN =8V V IN =12V V IN =24V VOUT = 3.3 V FSW = 2.1 MHz Auto mode Dual Output Figure 9-30. Load and Line Regulation Output Current [A] Output Voltage [V] V OUT =5V F SW =2.1MHz FPWM 0 1 2 3 4 5 6 4.95 5.05 V IN =8V V IN =12V V IN =24V VOUT = 5 V FSW = 2.1 MHz FPWM mode Dual Output Figure 9-31. Load and Line Regulation Output Current [A] Output Voltage [V] V OUT =5V F SW =2.1MHz AUTO 4.9 4.95 5.05 5.1 V IN =8V V IN =12V V IN =24V VOUT = 5 V FSW = 2.1 MHz Auto mode Dual Output Figure 9-32. Load and Line Regulation www.ti.com LMQ644A2-Q1 SNVSC42 – SEPTEMBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 45 Product Folder Links: LMQ644A2-Q1

Unless otherwise specified, the following conditions apply: Device: LMQ644A2, VIN = 13.5 V, TA = 25°C. The circuit is shown in Figure 9-1, and Figure 9-2 with the appropriate BOM from Table 9-3. Input Voltage [V] Switching Frequency [kHz] V OUT =5V F SW =400kHz FPWM 4.5 5 5.5 6 6.5 7 7.5 100 150 200 250 300 350 400 450 500 IOUT =10mA IOUT =6A IOUT =12A VOUT = 5 V FSW = 400 kHz FPWM mode Single Output Figure 9-33. Dropout Input Voltage [V] Switching Frequency [MHz] V OUT =5V F SW =2.1MHz FPWM 4.5 5 5.5 6 6.5 7 7.5 0.2 0.4 0.6 0.8 1.2 1.4 1.6 1.8 2.2 2.4 2.6 IOUT =10mA IOUT =6A IOUT =12A VOUT = 5 V FSW = 2.1 MHz FPWM mode Single Output Figure 9-34. Dropout Input Voltage [V] Switching Frequency [kHz] V OUT =3.3V F SW =400kHz FPWM 3 3.5 4 4.5 5 5.5 100 150 200 250 300 350 400 450 500 IOUT =10mA IOUT =6A IOUT =12A VOUT = 3.3 V FSW = 400 kHz FPWM mode Single Output Figure 9-35. Dropout Input Voltage [V] Switching Frequency [MHz] V OUT =3.3V F SW =2.1MHz FPWM 3 3.5 4 4.5 5 5.5 0.2 0.4 0.6 0.8 1.2 1.4 1.6 1.8 2.2 2.4 2.6 IOUT =10mA IOUT =6A IOUT =12A VOUT = 3.3 V FSW = 2.1 MHz FPWM mode Single Output Figure 9-36. Dropout VIN 2V / DIV ILOUT1 2A / DIV VOUT 2V / DIV SW1 5V / DIV VOUT = 5 V FSW = 400 kHz Auto mode IOUT = 3 A VIN = 5 to 7 V Single Output Figure 9-37. Dropout Recovery VOUT 5V / DIV ILOUT 5A / DIV EN 2V / DIV VOUT = 5 V FSW = 400 kHz FPWM mode IOUT = 100 mA VIN = 13.5 V Dual Output Figure 9-38. Start-Up With 100-mA Load LMQ644A2-Q1 SNVSC42 – SEPTEMBER 2023 www.ti.com

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Unless otherwise specified, the following conditions apply: Device: LMQ644A2, VIN = 13.5 V, TA = 25°C. The circuit is shown in Figure 9-1, and Figure 9-2 with the appropriate BOM from Table 9-3. VOUT 5V / DIV ILOUT 5A / DIV EN 2V / DIV VOUT = 3.3 V FSW = 400 kHz FPWM mode IOUT = 100 mA VIN = 13.5 V Dual Output Figure 9-39. Start-Up With 100-mA Load VOUT 2V / DIV ILOUT1 2A / DIV ILOUT2 2A / DIV EN1&EN2 5V / DIV VOUT = 3.3 V FSW = 400 kHz FPWM mode IOUT = 12 A VIN = 13.5 V Single Output Figure 9-40. Start-Up With 12-A Load VOUT 2V / DIV ILOUT1 5A / DIV ILOUT2 5A / DIV SS 2V / DIV VOUT = 3.3 V FSW = 400 kHz Auto mode IOUT = 0 A to Short Circuit VIN = 13.5 V Single Output Figure 9-41. Short-Circuit Protection VOUT 2V / DIV ILOUT 5A / DIV VOUT1 = 3.3 V FSW = 400 kHz Auto mode IOUT = 0 A to Short Circuit VIN = 13.5 V Dual Output Figure 9-42. Short-Circuit Protection VOUT 2V / DIV ILOUT1 5A / DIV ILOUT2 5A / DIV SS 2V / DIV VOUT = 3.3 V FSW = 400 kHz Auto mode IOUT = Short Circuit to 0 A VIN = 13.5 V Single Output Figure 9-43. Short-Circuit Hiccup VOUT 2V / DIV ILOUT 5A / DIV VOUT = 3.3 V FSW = 400 kHz Auto mode IOUT = Short Circuit to 0 A VIN = 13.5 V Dual Output Figure 9-44. Short-Circuit Hiccup www.ti.com LMQ644A2-Q1 SNVSC42 – SEPTEMBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 47 Product Folder Links: LMQ644A2-Q1

Unless otherwise specified, the following conditions apply: Device: LMQ644A2, VIN = 13.5 V, TA = 25°C. The circuit is shown in Figure 9-1, and Figure 9-2 with the appropriate BOM from Table 9-3. IOUT 5A / DIV VOUT 0.1V / DIV VOUT = 5 V FSW = 2.1 MHz FPWM mode IOUT = 100 mA to 6 A to 100 mA VIN = 13.5 V Dual Output Figure 9-45. Load Transient IOUT 5A / DIV VOUT 0.2V / DIV VOUT = 5 V FSW = 400 kHz FPWM mode IOUT = 100 mA to 6 A to 100 mA VIN = 13.5 V Dual Output Figure 9-46. Load Transient IOUT 5A / DIV VOUT 0.2V / DIV VOUT = 5 V FSW = 400 kHz Auto mode IOUT = 100 mA to 6 A to 100 mA VIN = 13.5 V Dual Output Figure 9-47. Load Transient IOUT 5A / DIV VOUT 0.1V / DIV VOUT = 5 V FSW = 400 kHz FPWM mode IOUT = 3 A to 6 A to 3 A VIN = 13.5 V Dual Output Figure 9-48. Load Transient IOUT 5A / DIV VOUT 0.1V / DIV VOUT = 3.3 V FSW = 2.1 MHz FPWM mode IOUT = 100 mA to 6 A to 100 mA VIN = 13.5 V Dual Output Figure 9-49. Load Transient IOUT 5A / DIV VOUT 0.2V / DIV VOUT = 3.3 V FSW = 2.1 MHz Auto mode IOUT = 100 mA to 6 A to 100 mA VIN = 13.5 V Dual Output Figure 9-50. Load Transient LMQ644A2-Q1 SNVSC42 – SEPTEMBER 2023 www.ti.com

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Unless otherwise specified, the following conditions apply: Device: LMQ644A2, VIN = 13.5 V, TA = 25°C. The circuit is shown in Figure 9-1, and Figure 9-2 with the appropriate BOM from Table 9-3. IOUT 5A / DIV VOUT 0.1V / DIV VOUT = 3.3 V FSW = 2.1 MHz FPWM mode IOUT = 3 A to 6 A to 3 A VIN = 13.5 V Dual Output Figure 9-51. Load Transient IOUT 5A / DIV VOUT 0.2V / DIV VOUT = 3.3 V FSW = 400 kHz FPWM mode IOUT = 100 mA to 6 A to 100 mA VIN = 13.5 V Dual Output Figure 9-52. Load Transient IOUT 5A / DIV VOUT 0.2V / DIV VOUT = 3.3 V FSW = 400 kHz Auto mode IOUT = 100 mA to 6 A to 100 mA VIN = 13.5 V Dual Output Figure 9-53. Load Transient IOUT 5A / DIV VOUT 0.1V / DIV VOUT = 3.3 V FSW = 400 kHz FPWM mode IOUT = 3 A to 6 A to 3 A VIN = 13.5 V Dual Output Figure 9-54. Load Transient IOUT 5A / DIV VOUT 0.2V / DIV VOUT = 3.3 V FSW = 400 kHz FPWM mode IOUT = 4 A to 12 A to 4 A VIN = 13.5 V Single Output Figure 9-55. Load Transient IOUT 5A / DIV VOUT 0.2V / DIV VOUT = 3.3 V FSW = 400 kHz FPWM mode IOUT = 6 A to 12 A to 4 A VIN = 13.5 V Single Output Figure 9-56. Load Transient www.ti.com LMQ644A2-Q1 SNVSC42 – SEPTEMBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 49 Product Folder Links: LMQ644A2-Q1

Unless otherwise specified, the following conditions apply: Device: LMQ644A2, VIN = 13.5 V, TA = 25°C. The circuit is shown in Figure 9-1, and Figure 9-2 with the appropriate BOM from Table 9-3. VOUT = 3.3 V FSW = 2100 kHz IOUT = 12 A Frequency Tested: 150 kHz to 30 MHz Figure 9-57. Single Output Monopole Radiated Emissions versus CISPR25 Class 5 Limits (Orange: Peak Signal, Red: Average Signal, Green: Quasi-Peak Signal) VOUT = 3.3 V FSW = 2100 kHz IOUT = 12 A Frequency Tested: 30 MHz to 200 MHz Figure 9-58. Single Output Bicon Radiated Emissions versus CISPR25 Class 5 Limits (Orange: Peak Signal, Red: Average Signal, Green: Quasi-Peak Signal) VOUT = 3.3 V FSW = 2100 kHz IOUT = 12 A Frequency Tested: 200 MHz to 1000 MHz Figure 9-59. Single Output Log Radiated Emissions versus CISPR25 Class 5 Limits (Orange: Peak Signal, Red: Average Signal, Green: Quasi-Peak Signal) VOUT = 3.3 V FSW = 2100 kHz IOUT = 12 A Frequency Tested: 1000 MHz to 2500 MHz Figure 9-60. Single Output Horn Radiated Emissions versus CISPR25 Class 5 Limits (Orange: Peak Signal, Red: Average Signal, Green: Quasi-Peak Signal) VOUT = 3.3 V FSW = 2100 kHz IOUT = 12 A Frequency Tested: 150 kHz to 30 MHz Figure 9-61. Single Output Conducted Emissions versus CISPR25 Class 5 Limits (Orange: Peak Signal, Red: Average Signal, Green: Quasi-Peak Signal) VOUT = 3.3 V FSW = 2100 kHz IOUT = 12 A Frequency Tested: 30 MHz to 108 MHz Figure 9-62. Single Output Conducted Emissions versus CISPR25 Class 5 Limits (Orange: Peak Signal, Red: Average Signal, Green: Quasi-Peak Signal) LMQ644A2-Q1 SNVSC42 – SEPTEMBER 2023 www.ti.com

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Unless otherwise specified, the following conditions apply: Device: LMQ644A2, VIN = 13.5 V, TA = 25°C. The circuit is shown in Figure 9-1, and Figure 9-2 with the appropriate BOM from Table 9-3. VOUT = 3.3 V FSW = 2100 kHz IOUT = 12 A Frequency Tested: 150 kHz to 30 MHz Figure 9-63. Dual Output Monopole Radiated Emissions versus CISPR25 Class 5 Limits (Orange: Peak Signal, Red: Average Signal, Green: Quasi-Peak Signal) VOUT = 3.3 V FSW = 2100 kHz IOUT = 12 A Frequency Tested: 30 MHz to 200 MHz Figure 9-64. Dual Output Bicon Radiated Emissions versus CISPR25 Class 5 Limits (Orange: Peak Signal, Red: Average Signal, Green: Quasi-Peak Signal) VOUT = 3.3 V FSW = 2100 kHz IOUT = 12 A Frequency Tested: 200 MHz to 1000 MHz Figure 9-65. Dual Output Log Radiated Emissions versus CISPR25 Class 5 Limits (Orange: Peak Signal, Red: Average Signal, Green: Quasi-Peak Signal) VOUT = 3.3 V FSW = 2100 kHz IOUT = 12 A Frequency Tested: 1000 MHz to 2500 MHz Figure 9-66. Dual Output Horn Radiated Emissions versus CISPR25 Class 5 Limits (Orange: Peak Signal, Red: Average Signal, Green: Quasi-Peak Signal) VOUT = 3.3 V FSW = 2100 kHz IOUT = 12 A Frequency Tested: 150 kHz to 30 MHz Figure 9-67. Dual Output Conducted Emissions versus CISPR25 Class 5 Limits (Orange: Peak Signal, Red: Average Signal, Green: Quasi-Peak Signal) VOUT = 3.3 V FSW = 2100 kHz IOUT = 12 A Frequency Tested: 30 MHz to 108 MHz Figure 9-68. Dual Output Conducted Emissions versus CISPR25 Class 5 Limits (Orange: Peak Signal, Red: Average Signal, Green: Quasi-Peak Signal) www.ti.com LMQ644A2-Q1 SNVSC42 – SEPTEMBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 51 Product Folder Links: LMQ644A2-Q1

Unless otherwise specified, the following conditions apply: Device: LMQ644A2, VIN = 13.5 V, TA = 25°C. The circuit is shown in Figure 9-1, and Figure 9-2 with the appropriate BOM from Table 9-3. 22 nF IN+ IN- 22 nF 2.2 μF 2.2 μF 2.2 μF 2.2 μF VIN GND

78279225101 XEL5030-102MEB

47 μF+ Figure 9-69. Recommended Input EMI Filter Table 9-3. BOM for Typical Application Curves VOUT FREQUENCY RFBB COUT EACH PHASE CIN + CHF EACH PHASE L CFFFOR ADJUSTABLE OUTPUT 3.3 V 400 kHz 32.4 kΩ 47 + 22 µF 2 × 10 µF + 1 × 100 nF 2.8 µH 10 pF 3.3 V 2200 kHz 32.4 kΩ 47 + 22 µF 2 × 10 µF + 1 × 100 nF 1 µH 10 pF 5 V 400 kHz 19.1 kΩ 47 + 22 µF 2 × 10 µF + 1 × 100 nF 2.8 µH 10 pF 5 V 2200 kHz 19.1 kΩ 47 + 22 µF 2 × 10 µF + 1 × 100 nF 1 µH 10 pF

9.3 Power Supply Recommendations

The characteristics of the input supply must be capable of delivering the required input current to the loaded regulator. The average input current can be estimated with Equation 10. I IN ≅ I OUT η × V OUT V IN (10) where

• η is the efficiency If the regulator is connected to the input supply through long wires or PCB traces, special care is required to achieve good performance. The parasitic inductance and resistance of the input cables can have an adverse effect on the operation of the regulator. The parasitic inductance, in combination with the low-ESR ceramic input capacitors, can form an underdamped resonant circuit. This can result in overvoltage transients at the input to the regulator or tripping UVLO. Consider that the supply voltage can dip when a load transient is applied to the output depending on the parasitic resistance and inductance of the harness and characteristics of the supply. If the application is operating close to the minimum input voltage, this dip can cause the regulator to momentarily shut down and reset. The best way to solve these kinds of issues is to reduce the distance from the input supply to the regulator. Additionally, use an aluminum input capacitor in parallel with the ceramics. The moderate ESR of this type of capacitor helps damp the input resonant circuit and reduce any overshoots or undershoots. A value in the range of 20 µF to 100 µF is usually sufficient to provide input damping and help hold the input voltage steady during large load transients. In some cases, a transient voltage suppressor (TVS) is used on the input of regulators. One class of this device has a snap-back characteristic (thyristor type). TI does not recommend to use a device with this type of characteristic. When the TVS fires, the clamping voltage falls to a very low value. If this voltage is less than the output voltage of the regulator, the output capacitors discharge through the device back to the input. This uncontrolled current flow can damage the device. The input voltage must not be allowed to fall below the output voltage. In this scenario, such as a shorted input test, the output capacitors discharge through the internal parasitic diode found between the VIN and SW pins of the device. During this condition, the current can become uncontrolled, possibly causing damage to the device. If this scenario is considered likely, then use a Schottky diode between the input supply and the output. LMQ644A2-Q1 SNVSC42 – SEPTEMBER 2023 www.ti.com

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9.4 Layout

9.4.1 Layout Guidelines

The PCB layout of any DC/DC converter is critical to the optimal performance of the design. Bad PCB layout can disrupt the operation of an otherwise good schematic design. Even if the converter regulates correctly, bad PCB layout can mean the difference between a robust design and one that cannot be mass produced. Furthermore, the EMI performance of the regulator is dependent on the PCB layout to a great extent. In a buck converter, the most EMI-critical PCB feature is the loop formed by the input capacitor or capacitors and power ground. This loop is shown in Figure 9-70 . This loop carries large transient currents that can cause large transient voltages when reacting with the trace inductance. Excessive transient voltages can disrupt the proper operation of the converter. Because of this, the traces in this loop must be wide and short while keeping the loop area as small as possible to reduce the parasitic inductance. Figure 9-71 shows a recommended layout for the critical components of the LMQ644xx circuit.

• Place the input capacitor or capacitors as close as possible to the input pin pairs: VIN1 to PGND1 and VIN2 to PGND2. Place the small capacitors closest. Each pair of pins are adjacent, simplifying the input capacitor placement. With the QFN package, there are two VIN/PGND pairs on either side of the package. This provides a symmetrical layout and helps minimize switching noise and EMI generation. Use a wide VIN plane on a mid-layer to connect both of the VIN pairs together to the input supply. Route symmetrically from the supply to each VIN pin to best use the benefits of the symmetric pinout.
• Place the bypass capacitor for VCC close to the VCC pin and AGND pin: This capacitor must be routed with short, wide traces to the VCC and AGND pins.
• Place the CBOOT capacitors as close as possible to the device with short, wide traces to the CBOOT and SW pins: Make sure to route the SW connection with a short wide trace to handle the current, but not longer than necessary to avoid generating common mode noise.
• Place the feedback divider as close as possible to the FB pin of the device: Place RFBB, RFBT, CFF if used, and RFF if used, physically close to the device. The connections to FB and AGND through RFBB must be short and close to those pins on the device. The connection to VOUT can be somewhat longer. However, this latter trace must not be routed near any noise source (such as the SW node) that can capacitively couple into the feedback path of the regulator.
• Make layer 2 of the PCB a ground plane: This plane acts as a noise shield and as a heat dissipation path. Using layer 2 reduces the enclosed area in the input circulating current in the input loop, reducing inductance.
• Provide wide paths for VIN, VOUT, and GND: These paths must be as wide and direct as possible to reduce any voltage drops on the input or output paths of the converter to maximize efficiency.
• Provide enough PCB area for proper heat sinking: Enough copper area must be used to make sure a low RθJA, considering maximum load current and ambient temperature. Make the top and bottom PCB layers with two-ounce copper and no less than one ounce. If the PCB design uses multiple copper layers (recommended), thermal vias can also be connected to the inner layer heat-spreading ground planes. Note that the package of this device dissipates heat through all pins. Wide traces can be used for all pins except where noise considerations dictate minimization of area.
• Keep the switch area small: Keep the copper area connecting the SW pin to the inductor as short and wide as possible. At the same time, the total area of this node must be minimized to help reduce radiated EMI. CIN_HF1 HS FET LS FET SW VIN1 PGND1 Figure 9-70. Input Current Loop www.ti.com LMQ644A2-Q1 SNVSC42 – SEPTEMBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 53 Product Folder Links: LMQ644A2-Q1

9.4.1.1 Ground and Thermal Considerations

As mentioned above, TI recommends using one of the middle layers as a solid ground plane. A ground plane provides shielding for sensitive circuits and traces. It also provides a quiet reference potential for the control circuitry. The AGND and PGND pins must be connected to the ground planes using vias next to the bypass capacitors. PGND pins connect directly to the grounds of the input and output capacitors. The PGND net contains noise at the switching frequency and can bounce due to load variations. The PGND trace, as well as the VIN and SW traces, must be constrained to one side of the ground plane. The other side of the ground plane contains much less noise and can be used for sensitive traces. TI recommends providing adequate device heat sinking by using vias near PGND and VIN pins to connect to the system ground plane or V IN strap, both of which dissipate heat. Use as much copper as possible for the system ground plane on the top and bottom layers and avoid plane cuts and bottlenecks for the heat flow for the best heat dissipation. Use a four-layer board with the copper thickness for the four layers, starting from the top as: 2 oz / 1 oz / 1 oz / 2 oz. A four-layer board with enough copper thickness and proper layout provides low current conduction impedance, proper shielding, and low thermal resistance.

9.4.2 Layout Example

Output capacitors Output capacitors Inductor Inductor GND PGND1PGND1 PGND3AGND CVIN1_HF1 CVIN2_HF1 CVIN2_HF2 CVIN1_HF2 CBOOT2CBOOT1 CVCC RFB1B RRT RFB2B CFVOSNS1 CFVOSNS2 Legend Top layer Layer-2 ground Top solder Keep the switch node copper area small Connect AGND, PGND1, PGND2, PGND3 directly to the DAP/EP on the top layer Place CVIN-HF1 close to the IC Place CVIN-HF2 next to the CVIN-HF1 Place RFBB, RRT, CVCC, CVOSNS close to the IC Place output capacitors adjacent to the inductor Place CBOOT close to the IC Use multiple vias around the positive and negative connections of the input capacitors Use multiple vias around the positive and negative connections of the output capacitors Use multiple vias around the positive and negative connections of the input capacitors Use multiple vias To PGND1 To PGND3 To PGND2 Figure 9-71. Layout Example LMQ644A2-Q1 SNVSC42 – SEPTEMBER 2023 www.ti.com

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10 Device and Documentation Support

10.1 Device Support

10.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

10.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

10.3 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

10.4 Trademarks

HotRod™ and TI E2E™ are trademarks of Texas Instruments. All trademarks are the property of their respective owners.

10.5 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

10.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. www.ti.com LMQ644A2-Q1 SNVSC42 – SEPTEMBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 55 Product Folder Links: LMQ644A2-Q1

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. LMQ644A2-Q1 SNVSC42 – SEPTEMBER 2023 www.ti.com

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www.ti.com 1-Oct-2023 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples LMQ644A2QRXARQ1 ACTIVE VQFN-FCRLF RXA 24 3000 RoHS (In Work) & Green (In Work) NIPDAU Level-2-260C-1 YEAR -40 to 150 LMQ644 A2B Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 2-Oct-2023 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant LMQ644A2QRXARQ1 VQFN- FCRLF Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 2-Oct-2023 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMQ644A2QRXARQ1 VQFN-FCRLF RXA 24 3000 346.0 346.0 33.0 Pack Materials-Page 2

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