LMP2021

LMP202x Zero-Drift, Low-Noise, EMI-Hardened Amplifiers datasheet (Rev. G)

Document overview

• Manufacturer or author: Texas Instruments, Incorporated [SNOSAY9,G]
• PDF pages: 42

Technical content

+ 1/2 LMP2022 0.1 PF LMP2022 0.1 PF 5.1 k: 0.1% 5.1 k: 0.1% 200: 200: 280: VA VA VA LMP2021 ADC161S626 VR = 1/2 VA 1 k: 1 k: R 3 R 4R 1 R 2 VA EMI 180: 470 pF VA = 5V Product Folder Sample & Buy T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LMP2021,LMP2022 SNOSAY9G –SEPTEMBER 2008–REVISED FEBRUARY 2016 LMP202xZero-Drift,Low-Noise,EMI-HardenedAmplifiers

1 Features

1(Typical Values, TA = 25°C, VS = 5 V)

• Input Offset Voltage (Typical) −0.4 µV
• Input Offset Voltage (Max) ±5 µV
• Input Offset Voltage Drift (Typical) –0.004 µV/°C
• Input Offset Voltage Drift (Max) ±0.02 µV/°C
• Input Voltage Noise, AV = 1000 11 nV/√Hz
• Open Loop Gain 160 dB
• CMRR 139 dB
• PSRR 130 dB
• Supply Voltage Range 2.2 V to 5.5 V
• Supply Current (per Amplifier) 1.1 mA
• Input Bias Current ±25 pA
• GBW 5 MHz
• Slew Rate 2.6 V/µs
• Operating Temperature Range −40°C to 125°C
• 5-Pin SOT-23, 8-Pin VSSOP and 8-Pin SOIC Packages

2 Applications

• Precision Instrumentation Amplifiers
• Battery Powered Instrumentation
• Thermocouple Amplifiers
• Bridge Amplifiers

3 Description

The LMP2021 and LMP2022 are single and dual precision operational amplifiers offering ultra low input offset voltage, near zero input offset voltage drift, very low input voltage noise and very high open loop gain. They are part of the LMP™ precision family and are ideal for instrumentation and sensor interfaces. The LMP202x has only 0.004 µV/°C of input offset voltage drift, and 0.4 µV of input offset voltage. These attributes provide great precision in high accuracy applications. The proprietary continuous auto zero correction circuitry ensures impressive CMRR and PSRR, removes the 1/f noise component, and eliminates the need for calibration in many circuits. With only 260 nVPP (0.1 Hz to 10 Hz) of input voltage noise and no 1/f noise component, the LMP202x are suitable for low frequency applications such as industrial precision weigh scales. The extremely high open loop gain of 160 dB drastically reduces gain error in high gain applications. With ultra precision DC specifications and very low noise, the LMP202x are ideal for position sensors, bridge sensors, pressure sensors, medical equipment and other high accuracy applications with very low error budgets. The LMP2021 is offered in 5-Pin SOT-23 and 8-Pin SOIC packages. The LMP2022 is offered in 8-Pin VSSOP and 8-Pin SOIC packages. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) LMP2021 SOIC (8) 4.90 mm x 3.91 mm SOT-23 (5) 2.90 mm x 1.60 mm LMP2022 SOIC (8) 4.90 mm x 3.91 mm VSSOP (8) 3.00 mm x 3.00 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. Bridge Amplifier The LMP202x support systems with up to 24 bits of accuracy.

LMP2021,LMP2022 SNOSAY9G –SEPTEMBER 2008–REVISED FEBRUARY 2016 www.ti.com Product Folder Links: LMP2021 LMP2022 Submit Documentation Feedback Copyright © 2008–2016, Texas Instruments Incorporated Table of Contents

5 Pin Configuration and Functions SC-70 and

VSSOP references from LMP2021 pinout

12 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision F (December 2014) to Revision G Page Changes from Revision E (March 2013) to Revision F Page

• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device Changes from Revision D (March 2013) to Revision E Page

+IN -IN 4 5 8N/C -IN +IN N/C OUT N/C OUT B 4 5 8OUT A -IN A +IN A -IN B +IN B A B LMP2021,LMP2022 www.ti.com SNOSAY9G –SEPTEMBER 2008–REVISED FEBRUARY 2016 Product Folder Links: LMP2021 LMP2022 Submit Documentation FeedbackCopyright © 2008–2016, Texas Instruments Incorporated

5 Pin Configuration and Functions

5 Pin SOT-23

D Package: LMP2021

8 Pin SOIC

D and DGK Packages: LMP2022

8 Pin VSSOP or SOIC

Pin Functions: LMP2021 PIN I/O DESCRIPTION NAME LMP2021 DBV D OUT 1 6 I Output +IN 3 3 I Non-Inverting Input -IN 4 2 O Inverting Input V- 2 4 P Negative Supply V+ 5 7 P Positive Supply N/C - 1 - No Internal Connection N/C - 5 - No Internal Connection N/C - 8 - No Internal Connection Pin Functions: LMP2022 PIN I/O DESCRIPTION NAME LMP2022 DGK +IN A 3 I Non-Inverting input, channel A +IN B 5 I Non-Inverting input, channel B –IN A 2 I Inverting input, channel A –IN B 6 I Inverting input, channel B OUT A 1 O Output, channel A OUT B 7 O Output, channel B V+ 8 P Positive (highest) power supply V– 4 P Negative (lowest) power supply

LMP2021,LMP2022 SNOSAY9G –SEPTEMBER 2008–REVISED FEBRUARY 2016 www.ti.com Product Folder Links: LMP2021 LMP2022 Submit Documentation Feedback Copyright © 2008–2016, Texas Instruments Incorporated (1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Recommended Operating Conditions indicate conditions for which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test conditions, see the Electrical Characteristics Tables. (2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications. (3) Package power dissipation should be observed. (4) The maximum power dissipation is a function of TJ(MAX), θJA, and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) - TA)/ θJA. All numbers apply for packages soldered directly onto a PC board.

6 Specifications

6.1 Absolute Maximum Ratings(1)(2)

VIN Differential –VS VS Supply Voltage (VS = V+ – V−) 6.0 V All Other Pins V+ + 0.3 V− − 0.3 V Output Short-Circuit Duration to V+ or V−(3) 5 seconds Junction Temperature(4) 150 °C Soldering Information Infrared or Convection (20 sec) 235 °C Wave Soldering Lead Temperature (10 sec) 260 °C Tstg Storage temperature range −65 150 °C (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2000 VCharged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±1000 Machine model ±200

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT Temperature Range −40 125 °C Supply Voltage (VS = V+ – V–) 2.2 5.5 V (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.4 Thermal Information

THERMAL METRIC(1) LMP2021, LMP2022 LMP2021 LMP2022 UNITD DBV DGK

8 PINS 5 PINS 8 PINS

RθJA Junction-to-ambient thermal resistance 106 164 217 °C/W

LMP2021,LMP2022 www.ti.com SNOSAY9G –SEPTEMBER 2008–REVISED FEBRUARY 2016 Product Folder Links: LMP2021 LMP2022 Submit Documentation FeedbackCopyright © 2008–2016, Texas Instruments Incorporated (1) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ > TA. (2) All limits are specified by testing, statistical analysis or design. (3) Typical values represent the most likely parametric norm at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped production material. (4) Offset voltage temperature drift is determined by dividing the change in VOS at the temperature extremes by the total temperature change. (5) The EMI Rejection Ratio is defined as EMIRR = 20Log ( VRF-PEAK/ΔVOS). 6.5 Electrical Characteristics: 2.5 V(1) Unless otherwise specified, all limits are ensured for TA = 25°C, V+ = 2.5 V, V− = 0 V, VCM = V+/2, RL >10 kΩ to V+/2. PARAMETER TEST CONDITIONS MIN(2) TYP(3) MAX(2) UNIT VOS Input Offset Voltage –5 –0.9 5 μV –40°C ≤ TJ ≤ 125°C –10 10 TCVOS Input Offset Voltage Drift(4) –0.02 0.001 0.02 μV/°C IB Input Bias Current –100 ±23 100 pA –40°C ≤ TJ ≤ 125°C –300 300 IOS Input Offset Current –200 ±57 200 pA –40°C ≤ TJ ≤ 125°C –250 250 CMRR Common Mode Rejection Ratio −0.2 V ≤ VCM ≤ 1.7 V, 0 V ≤ VCM ≤ 1.5 V 105 141 dB−0.2 V ≤ VCM ≤ 1.7 V, 0 V ≤ VCM ≤ 1.5 V, –40°C ≤ TJ ≤ 125°C 102 CMVR Input Common-Mode Voltage Range Large Signal CMRR ≥ 105 dB −0.2 1.7 VLarge Signal CMRR ≥ 102 dB, –40°C ≤ TJ ≤ 125°C 0 1.5 EMIRR Electro-Magnetic Interference Rejection Ratio(5) IN+ and IN− VRF-PEAK = 100 mVP (−20 dBVP) f = 400 MHz dB VRF-PEAK = 100 mVP (−20 dBVP) f = 900 MHz VRF-PEAK = 100 mVP (−20 dBVP) f = 1800 MHz VRF-PEAK = 100 mVP (−20 dBVP) f = 2400 MHz PSRR Power Supply Rejection Ratio 2.5 V ≤ V+ ≤ 5.5 V, VCM = 0 115 130 dB2.5 V ≤ V+ ≤ 5.5 V, VCM = 0 , –40°C ≤ TJ ≤ 125°C 112 2.2 V ≤ V+ ≤ 5.5 V, VCM = 0 110 130 AVOL Large Signal Voltage Gain RL = 10 kΩ to V+/2, VOUT = 0.5 V to 2 V 124 150 dB RL = 10 kΩ to V+/2, VOUT = 0.5 V to 2 V, –40°C ≤ TJ ≤ 125°C 119 RL = 2 kΩ to V+/2, VOUT = 0.5 V to 2 V 120 150 RL = 2 kΩ to V+/2, VOUT = 0.5 V to 2 V, –40°C ≤ TJ ≤ 125°C 115 VOUT Output Swing High RL = 10 kΩ to V+/2 38 50 mV from either rail RL = 10 kΩ to V+/2, –40°C ≤ TJ ≤ 125°C 70 RL = 2 kΩ to V+/2 62 85 RL = 2 kΩ to V+/2, –40°C ≤ TJ ≤ 125°C 115 Output Swing Low RL = 10 kΩ to V+/2 30 45 RL = 10 kΩ to V+/2, –40°C ≤ TJ ≤ 125°C 55 RL = 2 kΩ to V+/2 58 75 RL = 2 kΩ to V+/2, –40°C ≤ TJ ≤ 125°C 95 IOUT Linear Output Current Sourcing, VOUT = 2 V 30 50 mA Sinking, VOUT = 0.5 V 30 50

LMP2021,LMP2022 SNOSAY9G –SEPTEMBER 2008–REVISED FEBRUARY 2016 www.ti.com Product Folder Links: LMP2021 LMP2022 Submit Documentation Feedback Copyright © 2008–2016, Texas Instruments Incorporated Electrical Characteristics: 2.5 V(1) (continued) Unless otherwise specified, all limits are ensured for TA = 25°C, V+ = 2.5 V, V− = 0 V, VCM = V+/2, RL >10 kΩ to V+/2. PARAMETER TEST CONDITIONS MIN(2) TYP(3) MAX(2) UNIT (6) The number specified is the average of rising and falling slew rates and is measured at 90% to 10%. IS Supply Current Per Amplifier 0.95 1.10 mA Per Amplifier, –40°C ≤ TJ ≤ 125°C 1.37 SR Slew Rate(6) AV = +1, CL = 20 pF, RL = 10 kΩ VO = 2 VPP

2.5 V/μs

GBW Gain Bandwidth Product CL = 20 pF, RL = 10 kΩ 5 MHz GM Gain Margin CL = 20 pF, RL = 10 kΩ 10 dB ΦM Phase Margin CL = 20 pF, RL = 10 kΩ 60 deg CIN Input Capacitance Common Mode 12 pF Differential Mode 12 en Input-Referred Voltage Noise Density f = 0.1 kHz or 10 kHz, AV = 1000 11 nV/√Hz f = 0.1 kHz or 10 kHz, AV = 100 15 Input-Referred Voltage Noise 0.1 Hz to 10 Hz 260 nVPP

0.01 Hz to 10 Hz 330

In Input-Referred Current Noise f = 1 kHz 350 fA/√Hz tr Recovery time to 0.1%, RL = 10 kΩ, AV = −50, VOUT = 1.25 VPP Step, Duration = 50 μs 50 µs CT Cross Talk LMP2022, f = 1 kHz 150 dB

LMP2021,LMP2022 www.ti.com SNOSAY9G –SEPTEMBER 2008–REVISED FEBRUARY 2016 Product Folder Links: LMP2021 LMP2022 Submit Documentation FeedbackCopyright © 2008–2016, Texas Instruments Incorporated (1) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ > TA. (2) All limits are specified by testing, statistical analysis or design. (3) Typical values represent the most likely parametric norm at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped production material. (4) Offset voltage temperature drift is determined by dividing the change in VOS at the temperature extremes by the total temperature change. (5) The EMI Rejection Ratio is defined as EMIRR = 20Log ( VRF-PEAK/ΔVOS).

6.6 Electrical Characteristics: 5 V(1)

Unless otherwise specified, all limits are ensured for TA = 25°C, V+ = 5 V, V− = 0 V, VCM = V+/2, RL > 10 kΩ to V+/2. PARAMETER TEST CONDITIONS MIN(2) TYP(3) MAX(2) UNIT VOS Input Offset Voltage –5 −0.4 5 μV –40°C ≤ TJ ≤ 125°C –10 10 TCVOS Input Offset Voltage Drift(4) –0.02 −0.004 0.02 μV/°C IB Input Bias Current –100 ±25 100 pA –40°C ≤ TJ ≤ 125°C –300 300 IOS Input Offset Current –200 ±48 200 pA –40°C ≤ TJ ≤ 125°C –250 250 CMRR Common Mode Rejection Ratio −0.2 V ≤ VCM ≤ 4.2 V, 0 V ≤ VCM ≤ 4.0 V 120 139 dB−0.2 V ≤ VCM ≤ 4.2 V, 0 V ≤ VCM ≤ 4.0 V, –40°C ≤ TJ ≤ 125°C 115 CMVR Input Common-Mode Voltage Range Large Signal CMRR ≥ 120 dB –0.2 4.2 VLarge Signal CMRR ≥ 115 dB, –40°C ≤ TJ ≤ 125°C 0 4.0 EMIRR Electro-Magnetic Interference Rejection Ratio(5) IN+ and IN− VRF-PEAK = 100 mVP (−20 dBVP) f = 400 MHz dB VRF-PEAK = 100 mVP (−20 dBVP) f = 900 MHz VRF-PEAK = 100 mVP (−20 dBVP) f = 1800 MHz VRF-PEAK = 100 mVP (−20 dBVP) f = 2400 MHz PSRR Power Supply Rejection Ratio 2.5 V ≤ V+ ≤ 5.5 V, VCM = 0 115 130 dB2.5 V ≤ V+ ≤ 5.5 V, VCM = 0, –40°C ≤ TJ ≤ 125°C 112 2.2 V ≤ V+ ≤ 5.5 V, VCM = 0 110 130 AVOL Large Signal Voltage Gain RL = 10 kΩ to V+/2, VOUT = 0.5 V to 4.5 V 125 160 dB RL = 10 kΩ to V+/2, VOUT = 0.5 V to 4.5 V, –40°C ≤ TJ ≤ 125°C 120 RL = 2 kΩ to V+/2, VOUT = 0.5 V to 4.5 V 123 160 RL = 2 kΩ to V+/2, VOUT = 0.5 V to 4.5 V, –40°C ≤ TJ ≤ 125°C 118 VOUT Output Swing High RL = 10 kΩ to V+/2 83 135 mV from either rail RL = 10 kΩ to V+/2, –40°C ≤ TJ ≤ 125°C 170 RL = 2 kΩ to V+/2 120 160 RL = 2 kΩ to V+/2, –40°C ≤ TJ ≤ 125°C 204 Output Swing Low RL = 10 kΩ to V+/2 65 80 RL = 10 kΩ to V+/2, –40°C ≤ TJ ≤ 125°C 105 RL = 2 kΩ to V+/2 103 125 RL = 2 kΩ to V+/2, –40°C ≤ TJ ≤ 125°C 158 IOUT Linear Output Current Sourcing, VOUT = 4.5 V 30 50 mA Sinking, VOUT = 0.5 V 30 50

LMP2021,LMP2022 SNOSAY9G –SEPTEMBER 2008–REVISED FEBRUARY 2016 www.ti.com Product Folder Links: LMP2021 LMP2022 Submit Documentation Feedback Copyright © 2008–2016, Texas Instruments Incorporated Electrical Characteristics: 5 V(1) (continued) Unless otherwise specified, all limits are ensured for TA = 25°C, V+ = 5 V, V− = 0 V, VCM = V+/2, RL > 10 kΩ to V+/2. PARAMETER TEST CONDITIONS MIN(2) TYP(3) MAX(2) UNIT (6) The number specified is the average of rising and falling slew rates and is measured at 90% to 10%. IS Supply Current Per Amplifier 1.1 1.25 mA Per Amplifier, –40°C ≤ TJ ≤ 125°C 1.57 SR Slew Rate(6) AV = +1, CL = 20 pF, RL = 10 kΩ VO = 2 VPP

2.6 V/μs

GBW Gain Bandwidth Product CL = 20 pF, RL = 10 kΩ 5 MHz GM Gain Margin CL = 20 pF, RL = 10 kΩ 10 dB ΦM Phase Margin CL = 20 pF, RL = 10 kΩ 60 deg CIN Input Capacitance Common Mode 12 pF Differential Mode 12 en Input-Referred Voltage Noise Density f = 0.1 kHz or 10 kHz, AV= 1000 11 nV/√Hz f = 0.1 kHz or 10 kHz, AV= 100 15 Input-Referred Voltage Noise 0.1 Hz to 10 Hz Noise 260 nVPP

0.01 Hz to 10 Hz Noise 330

In Input-Referred Current Noise f = 1 kHz 350 fA/√Hz tr Input Overload Recovery time to 0.1%, RL = 10 kΩ, AV = −50, VOUT = 2.5 VPP Step, Duration = 50 μs 50 μs CT Cross Talk LMP2022, f = 1 kHz 150 dB

6.7 Typical Characteristics

Unless otherwise noted: TA = 25°C, RL > 10 kΩ, VS= V+ – V–, VS= 5 V, VCM = VS/2. Figure 1. Offset Voltage Distribution Figure 2. TCVOS Distribution Figure 3. Offset Voltage Distribution Figure 4. TCVOS Distribution Figure 5. Offset Voltage vs. Supply Voltage Figure 6. PSRR vs. Frequency

10 Ps/DIV

2 Ps/DIV

1 V/DIV OUTPUT

Unless otherwise noted: TA = 25°C, RL > 10 kΩ, VS= V+ – V–, VS= 5 V, VCM = VS/2. Figure 25. Output Swing High vs. Supply Voltage Figure 26. Output Swing Low vs. Supply Voltage Figure 27. Overload Recovery Time Figure 28. Overload Recovery Time Figure 29. Large Signal Step Response Figure 30. Small Signal Step Response

Unless otherwise noted: TA = 25°C, RL > 10 kΩ, VS= V+ – V–, VS= 5 V, VCM = VS/2. Figure 31. Large Signal Step Response Figure 32. Small Signal Step Response Figure 33. Output Voltage vs. Output Current Figure 34. Cross Talk Rejection Ratio vs. Frequency

LMP2021,LMP2022 www.ti.com SNOSAY9G –SEPTEMBER 2008–REVISED FEBRUARY 2016 Product Folder Links: LMP2021 LMP2022 Submit Documentation FeedbackCopyright © 2008–2016, Texas Instruments Incorporated

7 Detailed Description

7.1 Overview

The LMP202x are single and dual precision operational amplifiers with ultra low offset voltage, ultra low offset voltage drift, and very low input voltage noise with no 1/f and extended supply voltage range. The LMP202x offer on chip EMI suppression circuitry which greatly enhances the performance of these precision amplifiers in the presence of radio frequency signals and other high frequency disturbances. The LMP202x utilize proprietary auto zero techniques to measure and continuously correct the input offset error voltage. The LMP202x have a DC input offset voltage with a maximum value of ±5 μV and an input offset voltage drift maximum value of 0.02 µV/°C. The input voltage noise of the LMP202x is less than 11 nV/√Hz at a voltage gain of 1000 V/V and has no flicker noise component. This makes the LMP202x ideal for high accuracy, low frequency applications where lots of amplification is needed and the input signal has a very small amplitude. The proprietary input offset correction circuitry enables the LMP202x to have superior CMRR and PSRR performances. The combination of an open loop voltage gain of 160 dB, CMRR of 142 dB, PSRR of 130 dB, along with the ultra low input offset voltage of only −0.4 µV, input offset voltage drift of only −0.004 µV/°C, and input voltage noise of only 260 nVPP at 0.1 Hz to 10 Hz make the LMP202x great choices for high gain transducer amplifiers, ADC buffer amplifiers, DAC I-V conversion, and other applications requiring precision and long-term stability. Other features are rail-to-rail output, low supply current of 1.1 mA per amplifier, and a gain- bandwidth product of 5 MHz. The LMP202x have an extended supply voltage range of 2.2 V to 5.5 V, making them ideal for battery operated portable applications. The LMP2021 is offered in 5-pin SOT-23 and 8-pin SOIC packages. The LMP2022 is offered in 8-pin VSSOP and 8-Pin SOIC packages.

7.2 Functional Block Diagram

7.3 Feature Description

The amplifier's differential inputs consist of a non-inverting input (+IN) and an inverting input (–IN). The amplifier amplifies only the difference in voltage between the two inputs, which is called the differential input voltage. The output voltage of the op-amp Vout is given by Equation 1: VOUT = AOL (IN+ - IN-) (1) where AOL is the open-loop gain of the amplifier, typically around 100dB (100,000x, or 10uV per Volt).

7.4 Device Functional Modes

7.4.1 EMI Suppression

The near-ubiquity of cellular, Bluetooth, and Wi-Fi signals and the rapid rise of sensing systems incorporating wireless radios make electromagnetic interference (EMI) an evermore important design consideration for precision signal paths. Though RF signals lie outside the op amp band, RF carrier switching can modulate the DC offset of the op amp. Also some common RF modulation schemes can induce down-converted components. The added DC offset and the induced signals are amplified with the signal of interest and thus corrupt the measurement. The LMP202x use on chip filters to reject these unwanted RF signals at the inputs and power supply pins; thereby preserving the integrity of the precision signal path.

centimeters of PCB trace and wiring for sensors located close to the amplifier can pick up significant 1 GHz RF. information on EMIRR, please refer to AN-1698 (Literature Number SNOA497).

7.4.2 Input Voltage Noise

signal is smaller, a lower input voltage noise is quite advantageous and increases the signal to noise ratio. Figure 35 shows the input voltage noise of the LMP202x as the closed loop gain increases. Figure 35. Input Voltage Noise Density decreases with Gain Figure 36 shows the input voltage noise density does not have the 1/f component. Figure 36. Input Voltage Noise Density with no 1/f voltage noise and no 1/f noise allow more flexibility in circuit design.

8 Application and Implementation

validate and test their design implementation to confirm system functionality.

8.1 Application Information

8.1.1 Achieving Lower Noise With Filtering

shows a simple circuit that achieves this. In Figure 37 CF and the corner frequency of the filter resulting from CF and RF will reduce the total noise. Figure 37. Noise Reducing Filter for Lower Gains effect of the input voltage noise of the LMV771 is effectively not noticeable. Figure 38. Enhanced Filter to Further Reduce Noise at Higher Gains

between the noise performance of the two circuits. Figure 39. RMS Input Referred Noise vs. Frequency of 100V/V and 1000V/V. For these measurements and using Figure 37's circuit, RF = 49.7 kΩ and RIN = 497Ω. noise measured the circuit in Figure 38 has lower values and also depicts a more linear shape.

8.1.2 Input Bias Current

of pA. For this reason, the LMP202x is not recommeded for source impedances of 1 MΩ or greater. (resistance and capacitance), as well as the balance and matching of these impedances across the two inputs. to estimate what the actual bias current is without knowing the end circuit and associated capacitive strays. or auto zero amplifiers available from other vendors.

Figure 40. Input Bias Current of LMP202x is lower than Competitor A

8.1.3 Lowering the Input Bias Current

LMP202x varies with input impedance and feedback impedance. Once the value of a certain input resistance, i.e. this purpose, the total impedance seen by the input of the LMP202x needs to be calculated based on Figure 41. bias current, positive bias current, value. Figure 41. Input Bias Current vs. CG with RG = 1 GΩ

optimum value of CF will help reducing the input bias current. Figure 42. Input Bias Current vs. CF with RF = 1 GΩ IBIAS− are not individually specified, use the IBIAS value provided in datasheet graphs or tables for this calculation. outputs of the LMP2022 amplifier will be less than 200 nV.

8.1.4 Sensor Impedance

impedance seen by the auto correcting input stage.

8.1.5 Transient Response to Fast Inputs

there are additional considerations which can be viewed two perspectives: for sine waves and for steps. closed loop bandwidth should be kept below 20 kHz so as to avoid aliasing from the auto zero circuit. limitation manifests itself as an extended ramping and settling time, lasting ~100 µs.

8.1.6 Digital Acquisition Systems

several sources of noises such as: white noise or broad band noise, 1/f noise, thermal noise, and current noise. even further improved by adding a simple low pass filter following the amplification stage. Table 1. RMS Input Noise Performance

8.2 Typical Application

Figure 46 shows the Bridge Sensor Interface for these devices. Figure 46. LMP202x Used With ADC161S626

8.2.1 Design Requirements

used as the ADC driver is essential to maintaining total system accuracy. of the ADC. This is done by using one LMP2022 and one LMP2021 in front of the ADC161S626. signal and hence improve the overall system performance.

8.2.2 Detailed Design Procedure

output swing as well as the ADC's input dynamic range, and allows for some overload range.

feedback path of the LMP2022 amplifiers. voltage is used. This 2.5V reference is also used to power the bridge sensor and the inverting input of the ADC. to the system and improved the signal quality by removing common mode signals and high frequency noise.

8.2.3 Application Curve

Figure 47. Single Ended Output Results for Bridge Circuit

9 Power Supply Recommendations

temperature are presented in the Typical Characteristics. Supply voltages larger than 6 V can permanently damage the device.

10 Layout

10.1 Layout Guidelines

• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and op amp itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources local to the analog circuitry.
• Connect low-ESR, 0.1-μF ceramic bypass capacitors between each supply pin and ground, placed as close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single supply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective

methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes. SLOA089, Circuit Board Layout Techniques.

• In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If it is not possible to keep them separate, it is much better to cross the sensitive trace perpendicular as opposed to in parallel with the noisy trace.
• Place the external components as close to the device as possible. As shown in Typical Characteristics, keeping RF and RG close to the inverting input minimizes parasitic capacitance.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce leakage currents from nearby traces that are at different potentials.

10.2 Layout Example

Figure 48. Operational Amplifier Board Layout for Noninverting Configuration

11 Device and Documentation Support

11.1 Device Support

11.1.1 Development Support

11.2 Documentation Support

11.2.1 Related Documentation

SBOA015 (AB-028) — Feedback Plots Define Op Amp AC Performance. SLOA089 — Circuit Board Layout Techniques. SLOD006 — Op Amps for Everyone. SNOA497 — AN-1698 A Specification for EMI Hardened Operational Amplifiers. SBOA128 — EMI Rejection Ratio of Operational Amplifiers. TIPD128 — Capacitive Load Drive Solution using an Isolation Resistor. SBOA092 -— Handbook of Operational Amplifier Applications.

11.3 Related Links

resources, tools and software, and quick access to sample or buy. Table 2. Related Links

11.4 Trademarks

LMP is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.

11.5 Electrostatic Discharge Caution

during storage or handling to prevent electrostatic damage to the MOS gates.

11.6 Glossary

This glossary lists and explains terms, acronyms, and definitions.

LMP2021,LMP2022 www.ti.com SNOSAY9G –SEPTEMBER 2008–REVISED FEBRUARY 2016 Product Folder Links: LMP2021 LMP2022 Submit Documentation FeedbackCopyright © 2008–2016, Texas Instruments Incorporated

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 6-Feb-2026 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) LMP2021MA/NOPB Active Production SOIC (D) | 8 95 | TUBE Yes SN Level-1-260C-UNLIM -40 to 125 LMP20 21MA LMP2021MA/NOPB.A Active Production SOIC (D) | 8 95 | TUBE Yes SN Level-1-260C-UNLIM -40 to 125 LMP20 21MA LMP2021MAX/NOPB Active Production SOIC (D) | 8 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 LMP20 21MA LMP2021MAX/NOPB.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 LMP20 21MA LMP2021MF/NOPB Active Production SOT-23 (DBV) | 5 1000 | SMALL T&R Yes SN Level-1-260C-UNLIM -40 to 125 AF5A LMP2021MF/NOPB.A Active Production SOT-23 (DBV) | 5 1000 | SMALL T&R Yes SN Level-1-260C-UNLIM -40 to 125 AF5A LMP2021MFE/NOPB Active Production SOT-23 (DBV) | 5 250 | SMALL T&R Yes SN Level-1-260C-UNLIM -40 to 125 AF5A LMP2021MFE/NOPB.A Active Production SOT-23 (DBV) | 5 250 | SMALL T&R Yes SN Level-1-260C-UNLIM -40 to 125 AF5A LMP2021MFX/NOPB Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 AF5A LMP2021MFX/NOPB.A Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 AF5A LMP2022MA/NOPB Active Production SOIC (D) | 8 95 | TUBE Yes SN Level-1-260C-UNLIM -40 to 125 LMP20 22MA LMP2022MA/NOPB.A Active Production SOIC (D) | 8 95 | TUBE Yes SN Level-1-260C-UNLIM -40 to 125 LMP20 22MA LMP2022MAX/NOPB Active Production SOIC (D) | 8 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 LMP20 22MA LMP2022MAX/NOPB.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 LMP20 22MA LMP2022MM/NOPB Active Production VSSOP (DGK) | 8 1000 | SMALL T&R Yes SN Level-1-260C-UNLIM -40 to 125 AV5A LMP2022MM/NOPB.A Active Production VSSOP (DGK) | 8 1000 | SMALL T&R Yes SN Level-1-260C-UNLIM -40 to 125 AV5A LMP2022MME/NOPB Active Production VSSOP (DGK) | 8 250 | SMALL T&R Yes SN Level-1-260C-UNLIM -40 to 125 AV5A LMP2022MME/NOPB.A Active Production VSSOP (DGK) | 8 250 | SMALL T&R Yes SN Level-1-260C-UNLIM -40 to 125 AV5A LMP2022MMX/NOPB Active Production VSSOP (DGK) | 8 3500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 AV5A LMP2022MMX/NOPB.A Active Production VSSOP (DGK) | 8 3500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 AV5A (1) Status: For more details on status, see our product life cycle. Addendum-Page 1

www.ti.com 6-Feb-2026 (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 10-Aug-2026 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 10-Aug-2026 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMP2021MAX/NOPB SOIC D 8 2500 356.0 356.0 35.0 LMP2021MF/NOPB SOT-23 DBV 5 1000 208.0 191.0 35.0 LMP2021MFE/NOPB SOT-23 DBV 5 250 208.0 191.0 35.0 LMP2021MFX/NOPB SOT-23 DBV 5 3000 208.0 191.0 35.0 LMP2022MAX/NOPB SOIC D 8 2500 356.0 356.0 35.0 LMP2022MM/NOPB VSSOP DGK 8 1000 208.0 191.0 35.0 LMP2022MME/NOPB VSSOP DGK 8 250 208.0 191.0 35.0 LMP2022MMX/NOPB VSSOP DGK 8 3500 356.0 356.0 35.0 Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 10-Aug-2026 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) LMP2021MA/NOPB D SOIC 8 95 495 8 4064 3.05 LMP2021MA/NOPB.A D SOIC 8 95 495 8 4064 3.05 LMP2022MA/NOPB D SOIC 8 95 495 8 4064 3.05 LMP2022MA/NOPB.A D SOIC 8 95 495 8 4064 3.05 Pack Materials-Page 3

www.ti.com PACKAGE OUTLINE C .228-.244 TYP [5.80-6.19] .069 MAX [1.75] 6X .050 [1.27] 8X .012-.020 [0.31-0.51] .150 [3.81] .005-.010 TYP [0.13-0.25] 0 - 8 .004-.010 [0.11-0.25] .010 [0.25].016-.050 [0.41-1.27] 4X (0 -15 ) A .189-.197 [4.81-5.00] NOTE 3 B .150-.157 [3.81-3.98] NOTE 4 4X (0 -15 ) (.041) [1.04] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. 1 8 .010 [0.25] C A B PIN 1 ID AREA SEATING PLANE .004 [0.1] C SEE DETAIL A DETAIL A TYPICAL SCALE 2.800

www.ti.com EXAMPLE BOARD LAYOUT .0028 MAX [0.07] ALL AROUND .0028 MIN [0.07] ALL AROUND (.213) [5.4] 6X (.050 ) [1.27] 8X (.061 ) [1.55] 8X (.024) [0.6] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METAL SOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS EXPOSED METAL OPENING SOLDER MASK METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SYMM 4 5 SEE DETAILS SYMM

www.ti.com EXAMPLE STENCIL DESIGN 8X (.061 ) [1.55] 8X (.024) [0.6] 6X (.050 ) [1.27] (.213) [5.4] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X SYMM SYMM 4 5

www.ti.com PACKAGE OUTLINE C 0.22

0.08 TYP

0.25 3.0 2.6 2X 0.95 1.9 1.45 0.90 0.15

0.00 TYP

5X 0.5 0.3 0.6

0.3 TYP

0 TYP

1.9 (0.1) (0.15) 4X 0 -15 4X 4 -15 A 3.05 2.75 B1.75 1.45 (1.1) SOT-23 - 1.45 mm max heightDBV0005A SMALL OUTLINE TRANSISTOR 4214839/K 08/2024 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-178. 4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.25 mm per side. 5. Support pin may differ or may not be present.

0.2 C A B

0.1 C SCALE 4.000

www.ti.com EXAMPLE BOARD LAYOUT

0.07 MAX

0.07 MIN

5X (1.1) 5X (0.6) (2.6) (1.9) 2X (0.95) (R0.05) TYP 4214839/K 08/2024 SOT-23 - 1.45 mm max heightDBV0005A SMALL OUTLINE TRANSISTOR NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X PKG 3 4 SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL METALSOLDER MASK OPENING NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DETAILS EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN (2.6) (1.9) 2X(0.95) 5X (1.1) 5X (0.6) (R0.05) TYP SOT-23 - 1.45 mm max heightDBV0005A SMALL OUTLINE TRANSISTOR 4214839/K 08/2024 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X SYMM PKG 3 4

www.ti.com PACKAGE OUTLINE C 6X 0.65 1.95 8X 0.38 0.25 5.05

4.75 TYP

0.15 0.05 0.25 GAGE PLANE 0 -8

1.1 MAX

0.23 0.13 B 3.1 2.9 NOTE 4 A 3.1 2.9 NOTE 3 0.7 0.4 VSSOP - 1.1 mm max heightDGK0008A SMALL OUTLINE PACKAGE 4214862/A 04/2023

0.13 C A B

0.1 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-187. PowerPAD is a trademark of Texas Instruments. A 20 DETAIL A TYPICAL SCALE 4.000

www.ti.com EXAMPLE BOARD LAYOUT

0.05 MAX

0.05 MIN

8X (1.4) 8X (0.45) 6X (0.65) (4.4) (R0.05) TYP VSSOP - 1.1 mm max heightDGK0008A SMALL OUTLINE PACKAGE 4214862/A 04/2023 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. 8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. 9. Size of metal pad may vary due to creepage requirement. TM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 15X SYMM SYMM SEE DETAILS 15.000 METALSOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METALEXPOSED METAL SOLDER MASK DETAILS NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN 8X (1.4) 8X (0.45) 6X (0.65) (4.4) (R0.05) TYP VSSOP - 1.1 mm max heightDGK0008A SMALL OUTLINE PACKAGE 4214862/A 04/2023 NOTES: (continued) 11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 12. Board assembly site may have different recommendations for stencil design. TM SOLDER PASTE EXAMPLE SCALE: 15X SYMM SYMM

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