LMP2011 TI1

Document overview

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Technical content

20: Product Folder Sample & Buy T echnical Documents Tools & Software Support & Community LMP2011,LMP2012 SNOSA71L –OCTOBER 2004–REVISED SEPTEMBER 2015 LMP2011Single/LMP2012DualHighPrecision,Rail-to-RailOutputOperationalAmplifier

1 Features 3 Description

The LMP201x series are the first members of TI's1(For VS = 5 V, Typical Unless Otherwise Noted) new LMP™ precision amplifier family. The LMP201x• Low Ensured VOS Over Temperature 60 µV series offers unprecedented accuracy and stability in

  • Low Noise with No 1/f 35nV/√Hz space-saving miniature packaging, offered at an affordable price. This device utilizes patented auto-• High CMRR 130 dB zero techniques to measure and continually correct• High PSRR 120 dB the input offset error voltage. The result is an• High AVOL 130 dB amplifier which is ultra-stable over time and temperature. It has excellent CMRR and PSRR• Wide Gain-Bandwidth Product 3 MHz ratings, and does not exhibit the familiar 1/f voltage• High Slew Rate 4 V/µs and current noise increase that plagues traditional• Low Supply Current 930 µA amplifiers. The combination of the LMP201x
  • Rail-to-Rail Output 30 mV characteristics makes it a good choice for transducer amplifiers, high gain configurations, ADC buffer• No External Capacitors Required amplifiers, DAC I-V conversion, and any other 2.7-V to 5-V application requiring precision and long term2 Applications stability.
  • Precision Instrumentation Amplifiers Other useful benefits of the LMP201x are rail-to-rail• Thermocouple Amplifiers output, a low supply current of 930 µA, and wide
  • Strain Gauge Bridge Amplifier gain-bandwidth product of 3 MHz. These versatile features found in the LMP201x provide high performance and ease of use. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) SOIC (8) 4.90 mm × 3.91 mm LMP2011 SOT-23 (5) 2.90 mm × 1.60 mm SOIC (8) 4.90 mm × 3.91 mm LMP2012 VSSOP (8) 3.00 mm × 3.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Bridge Amplifier Offset Voltage vs Common Mode Voltage An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

LMP2011,LMP2012 SNOSA71L –OCTOBER 2004–REVISED SEPTEMBER 2015 www.ti.com Table of Contents

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision K (March 2013) to Revision L Page

  • Added Pin Configuration and Functions section, Storage Conditions table, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Changes from Revision J (March 2013) to Revision K Page

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5 Pin Configuration and Functions

Pin Functions: LMP2011 PIN NO. I/O DESCRIPTION NAME DBV D -IN 4 3 O Inverting input +IN 3 2 I Non-Inverting input N/C - 1 - No Internal Connection N/C - 5 - No Internal Connection N/C - 8 - No Internal Connection OUT 1 6 I Output V- 2 4 P Negative (lowest) power supply V+ 5 7 P Positive (highest) power supply D or DGK Package 8-Pin Dual SOIC and VSSOP Top View Pin Functions: LMP2012 PIN NO. I/O DESCRIPTION NAME D, DGK –IN A 2 I Inverting input, channel A +IN A 3 I Non-Inverting input, channel A –IN B 6 I Inverting input, channel B +IN B 5 I Non-Inverting input, channel B OUT A 1 O Output, channel A OUT B 7 O Output, channel B V– 4 P Negative (lowest) power supply V+ 8 P Positive (highest) power supply Copyright © 2004–2015, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: LMP2011 LMP2012

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6 Specifications

6.1 Absolute Maximum Ratings

See (1)(2) MIN MAX UNIT Supply Voltage 5.8 V Common-Mode Input Voltage (V-) - 0.3 (V+) + 0.3 V Lead Temperature (soldering 10 sec.) 300 °C Differential Input Voltage ±Supply Voltage Current at Input Pin 30 30 mA Current at Output Pin 30 30 mA Current at Power Supply Pin 50 30 mA Storage Temperature −65 150 °C (1) Absolute Maximum Ratings indicate limits beyond which damage may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and test conditions, see the Electrical Characteristics. (2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications.

6.2 ESD Ratings

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V(ESD) Electrostatic discharge V Machine model ±200 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

Supply Voltage 2.7 5.25 V Operating Temperature Range −40 125 °C

6.4 Thermal Information: LMP2011

THERMAL METRIC(1) D (SOIC) DBV (SOT-23) UNIT

8 PINS 5 PINS

RθJA Junction-to-ambient thermal resistance 119 164 °C/W RθJC(top) Junction-to-case (top) thermal resistance 66 116 °C/W RθJB Junction-to-board thermal resistance 60 28 °C/W ψJT Junction-to-top characterization parameter 17 13 °C/W ψJB Junction-to-board characterization parameter 59 27 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

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6.5 Thermal Information: LMP2012

THERMAL METRIC(1) D (SOIC) DGK (VSSOP) UNIT

8 PINS 8 PINS

RθJA Junction-to-ambient thermal resistance 110 157 °C/W RθJC(top) Junction-to-case (top) thermal resistance 50 51 °C/W RθJB Junction-to-board thermal resistance 52 77 °C/W ψJT Junction-to-top characterization parameter 8 5 °C/W ψJB Junction-to-board characterization parameter 51 75 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. 6.6 2.7-V DC Electrical Characteristics Unless otherwise specified, all limits ensured for TJ = 25°C, V+ = 2.7 V, V− = 0 V, V CM = 1.35 V, VO = 1.35 V, and RL > 1 MΩ. PARAMETER TEST CONDITIONS MIN(1) TYP(2) MAX(1) UNIT TJ = 25°C 0.8 25Input Offset Voltage (LMP2011 only) The temperature extremes 60 μV TJ = 25°C 0.8 36Input Offset VoltageVOS (LMP2012 only) The temperature extremes 60 TJ = 25°C 0.5 10 Offset Calibration Time ms The temperature extremes 12 Input Offset Voltage 0.015 μV/°C TCVOS Long-Term Offset Drift 0.006 μV/month Lifetime VOS Drift 2.5 μV IIN Input Current -3 pA IOS Input Offset Current 6 pA Input Differential 9RIND MΩResistance TJ = 25°C 95 130 Common Mode Rejection −0.3 ≤ VCM ≤ 0.9 V,CMRR dBThe temperature 90Ratio 0 ≤ VCM ≤ 0.9 V extremes TJ = 25°C 95 120Power Supply RejectionPSRR dBRatio The temperature extremes 90 TJ = 25°C 95 130 RL = 10 kΩ The temperature 90 extremes AVOL Open Loop Voltage Gain dB TJ = 25°C 90 124 RL = 2 kΩ The temperature 85 extremes (1) Limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlations using statistical quality control (SQC) method. (2) Typical values represent the most likely parametric norm. Copyright © 2004–2015, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: LMP2011 LMP2012

LMP2011,LMP2012 SNOSA71L –OCTOBER 2004–REVISED SEPTEMBER 2015 www.ti.com 2.7-V DC Electrical Characteristics (continued) Unless otherwise specified, all limits ensured for TJ = 25°C, V+ = 2.7 V, V− = 0 V, V CM = 1.35 V, VO = 1.35 V, and RL > 1 MΩ. PARAMETER TEST CONDITIONS MIN(1) TYP(2) MAX(1) UNIT TJ = 25°C 2.665 2.68 The temperature 2.655 extremesRL = 10 kΩ to 1.35 V, VVIN(diff) = ±0.5 V TJ = 25°C 0.033 0.060 The temperature 0.075 extremesOutput Swing (LMP2011 only) TJ = 25°C 2.630 2.65 The temperature 2.615 extremesRL = 2 kΩ to 1.35 V, VVIN(diff) = ±0.5 V TJ = 25°C 0.061 0.085 The temperature 0.105 extremes VO TJ = 25°C 2.64 2.68 The temperature 2.63 extremesRL = 10 kΩ to 1.35 V, VVIN(diff) = ±0.5 V TJ = 25°C 0.033 0.060 The temperature 0.075 extremesOutput Swing (LMP2012 only) TJ = 25°C 2.615 2.65 The temperature 2.6 extremesRL = 2 kΩ to 1.35 V, VVIN(diff) = ±0.5 V TJ = 25°C 0.061 0.085 The temperature 0.105 extremes TJ = 25°C 5 12 Sourcing, VO = 0 V, The temperature 3VIN(diff) = ±0.5 V extremes IO Output Current mA TJ = 25°C 5 18 VIN(diff) = ±0.5 V, The temperature 3Sinking, VO = 5 V extremes TJ = 25°C 0.919 1.20Supply Current perIS mAChannel The temperature extremes 1.50 6.7 2.7-V AC Electrical Characteristics TJ = 25°C, V+ = 2.7 V, V− = 0 V, VCM = 1.35 V, VO = 1.35 V, and RL > 1 MΩ. PARAMETER TEST CONDITIONS MIN(1) TYP(2) MAX(1) UNIT GBW Gain-Bandwidth Product 3 MHz SR Slew Rate 4 V/μs θ m Phase Margin 60 Deg Gm Gain Margin −14 dB en Input-Referred Voltage Noise 35 nV/√Hz enp-p Input-Referred Voltage Noise RS = 100 Ω, DC to 10 Hz 850 nVpp trec Input Overload Recovery Time 50 ms (1) Limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlations using statistical quality control (SQC) method. (2) Typical values represent the most likely parametric norm.

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LMP2011,LMP2012 www.ti.com SNOSA71L –OCTOBER 2004–REVISED SEPTEMBER 2015 6.8 5-V DC Electrical Characteristics Unless otherwise specified, all limits ensured for TJ = 25°C, V+ = 5 V, V− = 0 V, V CM = 2.5 V, VO = 2.5 V, and RL > 1MΩ. PARAMETER TEST CONDITIONS MIN(1) TYP(2) MAX(1) UNIT TJ = 25°C 0.12 25Input Offset Voltage (LMP2011 only) The temperature extremes 60 μV TJ = 25°C 0.12 36Input Offset VoltageVOS (LMP2012 only) The temperature extremes 60 TJ = 25°C 0.5 10 Offset Calibration Time ms The temperature extremes 12 Input Offset Voltage 0.015 μV/°C TCVOS Long-Term Offset Drift 0.006 μV/month Lifetime VOS Drift 2.5 μV IIN Input Current -3 pA IOS Input Offset Current 6 pA Input Differential 9RIND MΩResistance TJ = 25°C 100 130Common Mode −0.3 ≤ VCM ≤ 3.2,CMRR dBRejection Ratio 0 ≤ VCM ≤ 3.2 The temperature extremes 90 TJ = 25°C 95 120Power Supply RejectionPSRR dBRatio The temperature extremes 90 TJ = 25°C 105 130 RL = 10 kΩ The temperature extremes 100Open Loop VoltageAVOL dBGain TJ = 25°C 95 132 RL = 2 kΩ The temperature extremes 90 TJ = 25°C 4.96 4.978 The temperature extremes 0.085Output Swing (LMP2011 only) TJ = 25°C 4.895 4.919 The temperature extremes 0.140 VO TJ = 25°C 4.92 4.978 The temperature extremes 0.095Output Swing (LMP2012 only) TJ = 25°C 4.875 4.919 The temperature extremes 0.150 TJ = 25°C 8 15Sourcing, VO = 0 V, VIN(diff) = ±0.5 V The temperature extremes 6 IO Output Current mA TJ = 25°C 8 17Sinking, VO = 5 V, VIN(diff) = ±0.5 V The temperature extremes 6 TJ = 25°C 0.930 1.20Supply Current perIS mAChannel The temperature extremes 1.50 (1) Limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlations using statistical quality control (SQC) method. (2) Typical values represent the most likely parametric norm. Copyright © 2004–2015, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: LMP2011 LMP2012

LMP2011,LMP2012 SNOSA71L –OCTOBER 2004–REVISED SEPTEMBER 2015 www.ti.com 6.9 5-V AC Electrical Characteristics TJ = 25°C, V+ = 5 V, V− = 0 V, VCM = 2.5 V, VO = 2.5 V, and RL > 1MΩ. PARAMETER TEST CONDITIONS MIN(1) TYP(2) MAX(1) UNIT GBW Gain-Bandwidth Product 3 MHz SR Slew Rate 4 V/μs θ m Phase Margin 60 deg Gm Gain Margin −15 dB en Input-Referred Voltage Noise 35 nV/√Hz enp-p Input-Referred Voltage Noise RS = 100 Ω, DC to 10 Hz 850 nVpp trec Input Overload Recovery Time 50 ms (1) Limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlations using statistical quality control (SQC) method. (2) Typical values represent the most likely parametric norm.

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6.10 Typical Characteristics

TA=25C, VS= 5 V unless otherwise specified. Figure 1. Supply Current vs Supply Voltage Figure 2. Offset Voltage vs Supply Voltage Figure 3. Offset Voltage vs Common Mode Figure 4. Offset Voltage vs Common Mode Figure 5. Voltage Noise vs Frequency Figure 6. Input Bias Current vs Common Mode

TA=25C, VS= 5 V unless otherwise specified. Figure 7. PSRR vs Frequency Figure 8. PSRR vs Frequency Figure 9. Output Sourcing at 2.7 V Figure 10. Output Sourcing at 5 V Figure 11. Output Sinking at 2.7 V Figure 12. Output Sinking at 5 V

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TA=25C, VS= 5 V unless otherwise specified. Figure 19. Open Loop Gain and Phase vs RL at 2.7 V Figure 20. Open Loop Gain and Phase vs RL at 5 V Figure 22. Open Loop Gain and Phase vs CL at 5 VFigure 21. Open Loop Gain and Phase vs CL at 2.7 V Figure 23. Open Loop Gain and Phase vs Temperature Figure 24. Open Loop Gain and Phase vs Temperature

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7 Detailed Description

7.1 Overview

the input offset error voltage. The result is an amplifier which is ultra stable over time and temperature.

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 How the LMP201x Works

continuously monitors the input offset and corrects this error. result, the LMP201x has very low distortion of 0.02% and very low mixing products. Figure 28. The Output of a Chopper Stabilized Op Amp Figure 29. The Output of the LMP2011/LMP2012

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LMP2011,LMP2012 www.ti.com SNOSA71L –OCTOBER 2004–REVISED SEPTEMBER 2015 Feature Description (continued)

7.3.2 The Benefits of LMP201x: No 1/F Noise

Using patented methods, the LMP201x eliminates the 1/f noise present in other amplifiers. This noise, which increases as frequency decreases, is a major source of measurement error in all DC-coupled measurements. Low-frequency noise appears as a constantly-changing signal in series with any measurement being made. As a result, even when the measurement is made rapidly, this constantly-changing noise signal will corrupt the result. The value of this noise signal can be surprisingly large. For example: If a conventional amplifier has a flat-band noise level of 10 nV/√Hz and a noise corner of 10 Hz, the RMS noise at 0.001 Hz is 1 µV/√Hz. This is equivalent to a 0.50-µV peak-to-peak error, in the frequency range 0.001 Hz to 1.0 Hz. In a circuit with a gain of 1000, this produces a 0.50-mV peak-to-peak output error. This number of 0.001 Hz might appear unreasonably low, but when a data acquisition system is operating for 17 minutes, it has been on long enough to include this error. In this same time, the LMP201x will only have a 0.21-mV output error. This is smaller by 2.4×. This 1/f error gets even larger at lower frequencies. At the extreme, many people try to reduce this error by integrating or taking several samples of the same signal. This is also doomed to failure because the 1/f nature of this noise means that taking longer samples just moves the measurement into lower frequencies where the noise level is even higher. The LMP201x eliminates this source of error. The noise level is constant with frequency so that reducing the bandwidth reduces the errors caused by noise.

7.3.3 No External Capacitors Required

The LMP201x does not need external capacitors. This eliminates the problems caused by capacitor leakage and dielectric absorption, which can cause delays of several seconds from turn-on until the amplifier's error has settled.

7.3.4 Copper Leadframe

Another source of error that is rarely mentioned is the error voltage caused by the inadvertent thermocouples created when the common Kovar type IC package lead materials are soldered to a copper printed circuit board. These steel-based leadframe materials can produce over 35 μV/°C when soldered onto a copper trace. This can result in thermocouple noise that is equal to the LMP201x noise when there is a temperature difference of only 0.0014°C between the lead and the board! For this reason, the lead-frame of the LMP201x is made of copper. This results in equal and opposite junctions which cancel this effect. The extremely small size of the SOT-23 package results in the leads being very close together. This further reduces the probability of temperature differences and hence decreases thermal noise.

7.3.5 More Benefits

The LMP201x offers the benefits mentioned above and more. It has a rail-to-rail output and consumes only 950 µA of supply current while providing excellent DC and AC electrical performance. In DC performance, the LMP201x achieves 130 dB of CMRR, 120 dB of PSRR, and 130 dB of open loop gain. In AC performance, the LMP201x provides 3 MHz of gain-bandwidth product and 4 V/µs of slew rate.

7.4 Device Functional Modes

7.4.1 Input Currents

The LMP201x input currents are different than standard bipolar or CMOS input currents. Due to the auto-zero action of the input stage, the input current appears as a pulsating current at the chopping frequency (35 kHz) flowing in one input and out the other. Under most operating conditions, these currents are in the picoamp level and will have little or no effect in most circuits. These currents tend to increase slightly when the common-mode voltage is near the minus supply. (See the Typical Characteristics.) At high temperatures such as 85°C, the input currents become larger, 0.5 nA typical, and are both positive except when the VCM is near V−. If operation is expected at low common-mode voltages and high temperature, do not add resistance in series with the inputs to balance the impedances. Doing this can cause an increase in offset voltage. A small resistance such as 1 kΩ can provide some protection against very large transients or overloads, and will not increase the offset significantly. Copyright © 2004–2015, Texas Instruments Incorporated Submit Documentation Feedback 15 Product Folder Links: LMP2011 LMP2012

Because of these issues, the LMV201x is not recommended for source impedances over 1MΩ.

7.4.2 Overload Recovery

used to store the unadjusted offset voltage. Figure 30. Overload Recovery Test Circuit the output stage and large total GBW.

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8 Application and Implementation

validate and test their design implementation to confirm system functionality.

8.1 Application Information

ideal for industrial applications.

8.2 Typical Applications

8.2.1 Extending Supply Voltages and Output Swing with a Composite Amplifier

Figure 31. Inverting Composite Amplifier Figure 32. Non-Inverting Composite Amplifier

8.2.1.1 Design Requirements

set the dynamic performance of the overall amplifier. the worst case output shift due to VOS less than 4 mV.

8.2.1.2 Detailed Design Procedure

possibilities along with the measured performance in each case.

square-root relationship to the Bandwidth.

8.2.1.3 Application Results

Table 1 shows the results using various gains and compensation values. Table 1. Composite Amplifier Measured Performance

8.2.2 Precision Strain-gauge Amplifier

Figure 33. Precision Strain Gauge Amplifier specifying tighter-tolerance resistors, or by trimming.

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8.2.3 ADC Input Amplifier

Figure 34. DC Coupled ADC Driver

  • Very low offset voltage and offset voltage drift over time and temperature allow a high closed-loop gain setting without introducing any short-term or long-term errors. For example, when set to a closed-loop gain of 100 as the analog input amplifier for a 12-bit A/D converter, the overall conversion error over full operation temperature and 30 years life of the part (operating at 50°C) would be less than 5 LSBs.
  • Fast large-signal settling time to 0.01% of final value (1.4 μs) allows 12 bit accuracy at 100 KHZ or more sampling rate
  • No flicker (1/f) noise means unsurpassed data accuracy over any measurement period of time, no matter how long. Consider the following op amp performance, based on a typical low-noise, high-performance commercially-available device, for comparison: – Op amp flatband noise = 8 nV/√Hz – 1/f corner frequency = 100 Hz – AV = 2000 – Measurement time = 100 sec – Bandwidth = 2 Hz
  • This example will result in about 2.2 mVPP (1.9 LSB) of output noise contribution due to the op amp alone, compared to about 594 μVPP (less than 0.5 LSB) when that op amp is replaced with the LMP201x which has no 1/f contribution. If the measurement time is increased from 100 seconds to 1 hour, the improvement realized by using the LMP201x would be a factor of about 4.8 times (2.86 mVPP compared to 596 μV when LMP201x is used) mainly because the LMP201x accuracy is not compromised by increasing the observation time.
  • Copper leadframe construction minimizes any thermocouple effects which would degrade low level/high gain data conversion application accuracy (see discussion under The Benefits of the LMP201X section above).
  • Rail-to-Rail output swing maximizes the ADC dynamic range in 5-Volt single-supply converter applications. Below is a typical block diagram showing the LMP201x used as an ADC amplifier (Figure 34). Copyright © 2004–2015, Texas Instruments Incorporated Submit Documentation Feedback 19 Product Folder Links: LMP2011 LMP2012

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9 Power Supply Recommendations

The LMP201x is specified for operation from 2.7 V to 5.25 V (±1.35 V to ±2.625 V) over a –40°C to +125°C temperature range. Parameters that can exhibit significant variance with regard to operating voltage or temperature are presented in the Typical Characteristics. For proper operation, the power supplies must be properly decoupled. For decoupling the supply lines, TI recommends that 10-nF capacitors be placed as close as possible to the op amp power supply pins. For single supply, place a capacitor between V+ and V− supply leads. For dual supplies, place one capacitor between V+ and ground, and one capacitor between V- and ground. CAUTION Supply voltages larger than 6 V can permanently damage the device.

10 Layout

10.1 Layout Guidelines

For best operational performance of the device, use good printed circuit board (PCB) layout practices, including:

  • Connect low-ESR, 0.1-μF ceramic bypass capacitors between each supply pin and ground, placed as close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single supply applications.
  • Noise can propagate into analog circuitry through the power pins of the circuit as a whole and op amp itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources local to the analog circuitry.
  • Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes. A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital and analog grounds paying attention to the flow of the ground current. For more detailed information refer to SLOA089, Circuit Board Layout Techniques.
  • In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If it is not possible to keep them separate, it is much better to cross the sensitive trace perpendicular as opposed to in parallel with the noisy trace.
  • Place the external components as close to the device as possible. As shown in Layout Example, keeping RF and RG close to the inverting input minimizes parasitic capacitance.
  • Keep the length of input traces as short as possible. Always remember that the input traces are the most sensitive part of the circuit.

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10.2 Layout Example

Figure 35. Single Non-Inverting Amplifier Example Layout

11 Device and Documentation Support

11.1 Device Support

11.1.1 Development Support

11.2 Documentation Support

11.2.1 Related Documentation

  • SBOA015 (AB-028), Feedback Plots Define Op Amp AC Performance
  • SLOA089, Circuit Board Layout Techniques
  • SLOD006, Op Amps for Everyone
  • TIPD128, Capacitive Load Drive Solution using an Isolation Resistor
  • SBOA092, Handbook of Operational Amplifier Applications

11.3 Related Links

resources, tools and software, and quick access to sample or buy. Table 2. Related Links

11.4 Community Resources

solve problems with fellow engineers. contact information for technical support.

11.5 Trademarks

LMP, E2E are trademarks of Texas Instruments. All other trademarks are the property of their respective owners.

11.6 Electrostatic Discharge Caution

during storage or handling to prevent electrostatic damage to the MOS gates.

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11.7 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Copyright © 2004–2015, Texas Instruments Incorporated Submit Documentation Feedback 23 Product Folder Links: LMP2011 LMP2012

www.ti.com 5-Aug-2015 Addendum-Page 2 (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 6-Aug-2015 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMP2011MAX/NOPB SOIC D 8 2500 367.0 367.0 35.0 LMP2011MF SOT-23 DBV 5 1000 210.0 185.0 35.0 LMP2011MF/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0 LMP2011MFX/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0 LMP2012MAX/NOPB SOIC D 8 2500 367.0 367.0 35.0 LMP2012MM/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 LMP2012MMX/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 6-Aug-2015 Pack Materials-Page 2

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