LMK02002 Precision Clock Conditioner with Integrated PLL datasheet

Document overview

  • Manufacturer or author: Texas Instruments, Incorporated [SNAS418,*]
  • PDF pages: 24

Technical content

OSCin* R Divider Phase Detector N Divider CLKout0 CLKout0* CLKout1 CLKout1* CLKout2 CLKout2* CLKout3 CLKout3* Divider Delay Mux Divider Delay Mux Divider Delay Mux Divider Delay Mux Distribution Path CLK DATA LE Control Registers PWire Port Device Control LDGOE SYNC* CPout Clock Buffers Fin Fin* Charge Pump LMK02002 www.ti.com SNAS418 –AUGUST 2007 LMK02002PrecisionClockConditionerwithIntegratedPLL Check forSamples: LMK02002 1FEATURES DESCRIPTION The LMK02002 precisionclockconditionercombines 2• 20 fsAdditiveJitter the functions of jittercleaning/reconditioning,• IntegratedInteger-NPLL withOutstanding multiplication,and distributionof a referenceclock.NormalizedPhase Noise Contributionof-224 The deviceintegratesa highperformanceInteger-N dBc/Hz Phase Locked Loop (PLL),and fourLVPECL clock outputdistributionblocks.• Clock Output Frequency Range of1 to800 MHz Each clock distributionblock includes a

  • 4 LVPECL Clock Outputs programmable divider,a phase synchronization circuit,a programmable delay,a clockoutputmux,• DedicatedDividerand Delay Blocks on Each and an LVPECL outputbuffer.This allowsmultipleClock Output integer-relatedand phase-adjustedcopies of the• Pin Compatible FamilyofClockingDevices reference to be distributedto eight system
  • 3.15to3.45V Operation components.
  • Package: 48 Pin WQFN (7.0x 7.0x 0.8mm) The clock conditionercomes in a 48-pin WQFN package and is footprintcompatible with other TARGET APPLICATIONS clockingdevicesinthesame family.
  • Data ConverterClocking
  • Networking,SONET/SDH, DSLAM
  • WirelessInfrastructure
  • Medical
  • Testand Measurement
  • Military/Aerospace FunctionalBlock Diagram Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2Alltrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2007,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

4748 46 45 44 43 42 41 40 39 38 37 1413 15 16 17 18 19 20 21 22 23 24 36GND NC Vcc1 Vcc2 Vcc3 Vcc4 Vcc5 Vcc6 Vcc7 Vcc8 Vcc9 Vcc10 Vcc11 Vcc12 Vcc13 Vcc14 CLKuWire DATAuWire LEuWire NC LDObyp1 LDObyp2 GOE LD NC NC NC NC NC NC NC NC GND SYNC* OSCin OSCin* CPout Fin Fin* Bias CLKout0 CLKout0* CLKout1 CLKout1* CLKout2 CLKout2* CLKout3 CLKout3* DAP WQFN-48 Top Down View LMK02002 SNAS418 –AUGUST 2007 www.ti.com Connection Diagram Figure1. 48-PinWQFN Package Pin Descriptions Pin # Pin Name I/O Description 1,25 GND - Ground 2,7,14,15,17,18,20, NC - No Connectiontothesepins21,23,24 3,8,13,16,19,22,26, Vcc1,Vcc2,Vcc3,Vcc4,Vcc5,Vcc6,Vcc7,Vcc8, - Power Supply30,31,33,37,40,43,46 Vcc9,Vcc10,Vcc11,Vcc12,Vcc13,Vcc14

4 CLKuWire I MICROWIRE ClockInput

5 DATAuWire I MICROWIRE Data Input

6 LEuWire I MICROWIRE LatchEnableInput

9,10 LDObyp1, LDObyp2 - LDO Bypass

11 GOE I GlobalOutputEnable

12 LD O Lock Detectand TestOutput

27 SYNC* I GlobalClockOutputSynchronization

28,29 OSCin, OSCin* I OscillatorClockInput;Must be AC coupled

32 CPout O Charge Pump Output

34,35 Fin,Fin* I FrequencyInput;Must be AC coupled

36 Bias I BiasBypass

38,39 CLKout0,CLKout0* O LVPECL ClockOutput0 41,42 CLKout1,CLKout1* O LVPECL ClockOutput1

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www.ti.com SNAS418 –AUGUST 2007 Pin Descriptions(continued) Pin # Pin Name I/O Description 44,45 CLKout2,CLKout2* O LVPECL ClockOutput2 47,48 CLKout3,CLKout3* O LVPECL ClockOutput3 DAP DAP - DieAttachPad isGround These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates. AbsoluteMaximum Ratings (1)(2)(3) Parameter Symbol Ratings Units Power SupplyVoltage VCC -0.3to3.6 V InputVoltage VIN -0.3to(VCC + 0.3) V StorageTemperatureRange TSTG -65to150 °C Lead Temperature(solder4 s) TL +260 °C JunctionTemperature TJ 125 °C (1) "AbsoluteMaximum Ratings"indicatelimitsbeyond whichdamage tothedevicemay occur,includinginoperabilityand degradationof devicereliabilityand/orperformance.Functionaloperationofthedeviceand/ornon-degradationattheAbsoluteMaximum Ratingsor otherconditionsbeyond thoseindicatedintheRecommended OperatingConditionsisnotimplied.The Recommended Operating Conditionsindicateconditionsatwhichthedeviceisfunctionaland thedeviceshouldnotbe operatedbeyond such conditions. (2) Thisdeviceisa highperformanceintegratedcircuitwithESD handlingprecautions.Handlingofthisdeviceshouldonlybe done atESD protectedwork stations.The deviceisratedtoa HBM-ESD of> 2 kV,a MM-ESD of> 200 V,and a CDM-ESD of> 1.2kV. (3) IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheTISalesOffice/Distributorsforavailabilityand specifications. Recommended OperatingConditions Parameter Symbol Min Typ Max Units AmbientTemperature TA -40 25 85 °C Power SupplyVoltage VCC 3.15 3.3 3.45 V Package Thermal Resistance Package θJA θJ-PAD (ThermalPad) 48-LeadWQFN (1) 27.4° C/W 5.8° C/W (1) Specificationassumes 16 thermalviasconnectthedieattachpad totheembedded copperplaneon the4-layerJEDEC board.These viasplaya key roleinimprovingthethermalperformanceoftheWQFN. Itisrecommended thatthemaximum number ofviasbe used in theboardlayout. Copyright© 2007,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:LMK02002

SNAS418 –AUGUST 2007 www.ti.com ElectricalCharacteristics(1) (3.15V ≤ Vcc ≤ 3.45V,-40°C ≤ TA ≤ 85 °C, DifferentialInputs/Outputs;exceptas specified.Typicalvaluesrepresentmost likelyparametricnorms atVcc = 3.3V,TA = 25 °C, and attheRecommended OperationConditionsatthetimeofproduct characterizationand arenotspecified). Symbol Parameter Conditions Min Typ Max Units CurrentConsumption Entiredevice;CLKout0 & CLKout3 159enabledinBypass Mode ICC Power SupplyCurrent(2) mA Entiredevice;AllOutputsOff(no 70emitterresistorsplaced) ICC PD Power Down Current POWERDOWN = 1 1 mA ReferenceOscillator ReferenceOscillatorInputFrequencyfOSCin square 1 200 MHzRange forSquare Wave AC coupled;Differential(VOD ) Square Wave InputVoltageforOSCin andVOSCin square 0.2 1.6 VppOSCin* Frequency Input fFin FrequencyInputFrequencyRange 1 800 MHz SLEW Fin FrequencyInputSlew Rate See (3)(4) 0.5 V/ns DUTY Fin FrequencyInputDutyCycle 40 60 % PFin InputPower Range forFinorFin* AC coupled -13 8 dBm PLL fCOMP Phase DetectorFrequency 40 MHz VCPout = Vcc/2,PLL_CP_GAIN = 1x 100 VCPout = Vcc/2,PLL_CP_GAIN = 4x 400 ISRCE CPout Charge Pump SourceCurrent µA VCPout = Vcc/2,PLL_CP_GAIN = 16x 1600 VCPout = Vcc/2,PLL_CP_GAIN = 32x 3200 VCPout = Vcc/2,PLL_CP_GAIN = 1x -100 VCPout = Vcc/2,PLL_CP_GAIN = 4x -400 ISINKCPout Charge Pump SinkCurrent μA VCPout = Vcc/2,PLL_CP_GAIN = 16x -1600 VCPout = Vcc/2,PLL_CP_GAIN = 32x -3200 ICPoutTRI Charge Pump TRI-STATE Current 0.5V < VCPout < Vcc -0.5V 2 10 nA MagnitudeofCharge Pump VCPout = Vcc /2ICPout%MIS 3 %Sinkvs.SourceCurrentMismatch TA = 25°C MagnitudeofCharge Pump 0.5V < VCPout < Vcc -0.5VICPoutVTUNE 4 %Currentvs.Charge Pump VoltageVariationTA = 25°C MagnitudeofCharge Pump Currentvs.ICPoutTEMP 4 %TemperatureVariation PLL_CP_GAIN = 1x -117PLL 1/fNoiseat10 kHz Offset(5) PN10kHz dBc/HzNormalizedto1 GHz OutputFrequency PLL_CP_GAIN = 32x -122 (1) The ElectricalCharacteristicstableslistensuredspecificationsunderthelistedRecommended OperatingConditionsexceptas otherwisemodifiedorspecifiedby theElectricalCharacteristicsConditionsand/orNotes.Typicalspecificationsareestimationsonlyand arenotensured. (2) See CURRENT CONSUMPTION /POWER DISSIPATION CALCULATIONS formore currentconsumption/power dissipation calculationinformation. (3) Forallfrequenciestheslewrate,SLEW Fin,ismeasured between 20% and 80%. (4) Specificationisensuredby characterizationand isnottestedinproduction. (5) A specificationinmodelingPLL in-bandphase noiseisthe1/fflickernoise,LPLL_flicker(f),whichisdominantclosetothecarrier.Flicker noisehas a 10 dB/decadeslope.PN10kHz isnormalizedtoa 10 kHz offsetand a 1 GHz carrierfrequency.PN10kHz = LPLL_flicker(10 kHz)-20log(Fout/1 GHz),where LPLL_flicker(f)isthesinglesideband phase noiseofonlytheflickernoise's contributiontototalnoise, L(f).To measure LPLL_flicker(f)itisimportanttobe on the10 dB/decadeslopeclosetothecarrier.A highphase detectorfrequencyand a cleancrystalareimportanttoisolatingthisnoisesourcefromthetotalphase noise,L(f).LPLL_flicker(f)can be masked by thereference oscillatorperformanceifa lowpower ornoisysourceisused.The totalPLL inbandphase noiseperformanceisthesum ofLPLL_flicker(f) and LPLL_flat(f).

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www.ti.com SNAS418 –AUGUST 2007 ElectricalCharacteristics(1)(continued) (3.15V ≤ Vcc ≤ 3.45V,-40°C ≤ TA ≤ 85 °C, DifferentialInputs/Outputs;exceptas specified.Typicalvaluesrepresentmost likelyparametricnorms atVcc = 3.3V,TA = 25 °C, and attheRecommended OperationConditionsatthetimeofproduct characterizationand arenotspecified). Symbol Parameter Conditions Min Typ Max Units PLL_CP_GAIN = 1x -219 PN1Hz NormalizedPhase NoiseContribution(6) dBc/Hz PLL_CP_GAIN = 32x -224 Clock DistributionSection(7)-LVPECL Clock Outputs (CLKout0 toCLKout3) CLKoutX_MUX = 20R L = 100 Ω Bypass DistributionPath= CLKoutX_MUX =JitterADD AdditiveRMS Jitter(7) 800 MHz fs DividedBandwidth= 75CLKoutX_DIV =12 kHz to20 MHz Equalloadingand identicalclock tSKEW CLKoutX toCLKoutY (4) configuration -30 ±3 30 ps Termination= 50 Ω toVcc -2 V Vcc -VOH OutputHighVoltage V0.98 Termination= 50 Ω toVcc -2 V Vcc -VOL OutputLow Voltage CLKoutX outputfrequency= 200 MHz V1.8 VOD DifferentialOutputVoltage 660 810 965 mV DigitalLVTTL Interfaces(8) VIH High-LevelInputVoltage 2.0 Vcc V VIL Low-LevelInputVoltage 0.8 V IIH High-LevelInputCurrent VIH = Vcc -5.0 5.0 µA IIL Low-LevelInputCurrent VIL= 0 -40.0 5.0 µA Vcc -VOH High-LevelOutputVoltage IOH = +500 µA V0.4 VOL Low-LevelOutputVoltage IOL = -500µA 0.4 V DigitalMICROWIRE Interfaces(9) VIH High-LevelInputVoltage 1.6 Vcc V VIL Low-LevelInputVoltage 0.4 V IIH High-LevelInputCurrent VIH = Vcc -5.0 5.0 µA IIL Low-LevelInputCurrent VIL= 0 -5.0 5.0 µA MICROWIRE Timing tCS Data toClockSetUp Time See Data InputTiming 25 ns tCH Data toClockHoldTime See Data InputTiming 8 ns tCWH ClockPulseWidthHigh See Data InputTiming 25 ns tCWL ClockPulseWidthLow See Data InputTiming 25 ns tES ClocktoEnableSetUp Time See Data InputTiming 25 ns tCES EnabletoClockSetUp Time See Data InputTiming 25 ns tEWH EnablePulseWidthHigh See Data InputTiming 25 ns (6) A specificationinmodelingPLL in-bandphase noiseistheNormalizedPhase NoiseContribution,LPLL_flat(f),ofthePLL and isdefined as PN1Hz = LPLL_flat(f)– 20log(N)– 10log(fCOMP ).LPLL_flat(f)isthesinglesideband phase noisemeasured atan offsetfrequency,f,ina 1 Hz Bandwidthand fCOMP isthephase detectorfrequencyofthesynthesizer.LPLL_flat(f)contributestothetotalnoise,L(f).To measure LPLL_flat(f)theoffsetfrequency,f,must be chosen sufficientlysmallerthentheloopbandwidthofthePLL,and yetlargeenough toavoid a substantialnoisecontributionfromthereferenceand flickernoise.LPLL_flat(f)can be masked by thereferenceoscillatorperformanceif a lowpower ornoisysourceisused. (7) The ClockDistributionSectionincludesallpartsofthedeviceexceptthePLL section.TypicalAdditiveJitterspecificationsapplytothe clockdistributionsectiononly. (8) AppliestoGOE, LD, and SYNC*. (9) AppliestoCLKuWire,DATAuWire, and LEuWire. Copyright© 2007,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:LMK02002

SNAS418 –AUGUST 2007 www.ti.com SerialData Timing Diagram Data bitsseton theDATAuWire signalare clockedintoa shiftregister,MSB first,on each risingedge ofthe CLKuWire signal.On the risingedge of the LEuWire signal,the data issent from the shiftregisterto the addressedregisterdeterminedby theLSB bits.Aftertheprogramming iscompletetheCLKuWire, DATAuWire, and LEuWire signalsshouldbe returnedtoa lowstate. Charge Pump CurrentSpecificationDefinitions I1= Charge Pump SinkCurrentatVCPout = Vcc -ΔV I2= Charge Pump SinkCurrentatVCPout = Vcc/2 I3= Charge Pump SinkCurrentatVCPout = ΔV I4= Charge Pump SourceCurrentatVCPout = Vcc -ΔV I5= Charge Pump SourceCurrentatVCPout = Vcc/2 I6= Charge Pump SourceCurrentatVCPout = ΔV ΔV = Voltageoffsetfromthepositiveand negativesupplyrails.Definedtobe 0.5V forthisdevice. Charge Pump Output CurrentMagnitude Variationvs.Charge Pump Output Voltage

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www.ti.com SNAS418 –AUGUST 2007 Charge Pump CurrentSpecificationDefinitions(continued) Charge Pump Sink Currentvs.Charge Pump Output Source CurrentMismatch Charge Pump Output CurrentMagnitude Variationvs.Temperature FunctionalDescription The LMK02002 precisionclockconditionercombines thefunctionsofjittercleaning/reconditioning,multiplication, and distributionofa referenceclock.The deviceintegratesa highperformanceInteger-NPhase Locked Loop (PLL),and fourLVPECL clockoutputdistributionblocks. Each clockdistributionblockincludesa programmabledivider,a phase synchronizationcircuit,a programmable delay,a clockoutputmux, and an LVPECL outputbuffer.Thisallowsmultipleinteger-relatedand phase-adjusted copiesofthereferencetobe distributedtoeightsystemcomponents. The clockconditionercomes ina 48-pinWQFN package and isfootprintcompatiblewithotherclockingdevices inthesame family. BIAS PIN To properlyuse thedevice,bypass Bias(pin36) witha low leakage1 µF capacitorconnectedtoVcc.Thisis importantforlownoiseperformance. LDO BYPASS To properlyuse thedevice,bypass LDObyp1 (pin9)witha 10 µF capacitorand LDObyp2 (pin10)witha 0.1µF capacitor. OSCILLATOR INPUT PORT (OSCin,OSCin*) The purposeofOSCin istoprovidethePLL witha referencesignal.The OSCin portmust be AC coupled,refer to the System LevelDiagram in the ApplicationInformationsection.The OSCin portmay be drivensingle endedlyby AC groundingOSCin* witha 0.1µF capacitor. FREQUENCY INPUT PORT (Fin,Fin*) The purposeofFinistoprovidethePLL witha feedbacksignalfroman externaloscillator.The Finportmay be drivensingleendedlyby AC groundingFin*. Copyright© 2007,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:LMK02002

SYNC* CLKout0 CLKout1 CLKout2 LMK02002 SNAS418 –AUGUST 2007 www.ti.com CLKout DELAYS Each individualclockoutputincludesa delayadjustment.Clockoutputdelayregisters(CLKoutX_DLY) supporta 150 ps stepsizeand rangefrom0 to2250 ps oftotaldelay. LVPECL OUTPUTS Each LVPECL outputmay be disabledindividuallyby programmingtheCLKoutX_EN bits.Alltheoutputsmay be disabledsimultaneouslyby pullingtheGOE pinloworprogrammingEN_CLKout_Globalto0. GLOBAL CLOCK OUTPUT SYNCHRONIZATION The SYNC* pinsynchronizesthe clockoutputs.When the SYNC* pinisheldina logiclow state,the divided outputsarealsoheldina logiclow state.When theSYNC* pingoes high,thedividedclockoutputsareactivated and willtransitiontoa highstatesimultaneously.Clocksinthebypassed stateare notaffectedby SYNC* and arealwayssynchronizedwiththedividedoutputs. The SYNC* pinmust be heldlow forgreaterthanone clockcycleoftheFrequencyInputport,alsoknown as the distributionpath.Once thislow eventhas been registered,theoutputswillnotreflectthelow stateforfourmore cycles.Similarlyonce theSYNC* pinbecomes high,theoutputswillnotsimultaneouslytransitionhighuntilfour more distributionpathclockcycleshave passed.See thetimingdiagrambelow forfurtherdetail.Inthetiming diagram below the clocks are programmed as CLKout0_MUX = Bypassed, CLKout1_MUX = Divided, CLKout1_DIV = 2,CLKout2_MUX = Divided,and CLKout2_DIV = 4. SYNC* Timing Diagram The SYNC* pinprovidesan internalpull-upresistoras shown on thefunctionalblockdiagram.IftheSYNC* pin isnot terminatedexternallythe clockoutputswilloperatenormally.Ifthe SYNC* functionisnot used,clock outputsynchronizationisnotspecified. CLKout OUTPUT STATES Each clockoutputmay be individuallyenabledwiththeCLKoutX_EN bits.Each individualoutputenablecontrol bit is gated with the Global Output Enable input pin (GOE) and the Global Output Enable bit (EN_CLKout_Global). Allclockoutputscan be disabledsimultaneouslyifthe GOE pin is pulledlow by an externalsignalor EN_CLKout_Globalissetto0. CLKoutX EN_CLKout GOE pin Clock X Output State _EN bit _Globalbit 1 1 Low Low Don'tcare 0 Don'tcare Off

0 Don'tcare Don'tcare Off

1 1 High/No Connect Enabled

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www.ti.com SNAS418 –AUGUST 2007 When an LVPECL outputisintheOffstate,theoutputsareata voltageofapproximately1 volt. GLOBAL OUTPUT ENABLE AND LOCK DETECT The GOE pinprovidesan internalpull-upresistor.Ifitisnotterminatedexternally,theclockoutputstatesare determinedby theClockOutputEnablebits(CLKoutX_EN) and theEN_CLKout_Globalbit. By programming the PLL_MUX registerto DigitalLock DetectActiveHigh (See PLL_MUX[3:0] --Multiplexer ControlforLD Pin),theLock Detect(LD)pincan be connectedtotheGOE pininwhichcase alloutputsareset lowautomaticallyifthesynthesizerisnotlocked. POWER ON RESET When supplyvoltagetothedeviceincreasesmonotonicallyfrom ground toVcc,thepower on resetcircuitsets allregistersto theirdefaultvalues,see RESET bit--R0 onlyformore informationon defaultregistervalues. Voltageshouldbe appliedtoallVcc pinssimultaneously. GeneralProgramming Information The LMK02002 deviceisprogrammed usingseveral32-bitregisterswhich controlthe device'soperation.The registersconsistofa datafieldand an addressfield.The last4 registerbits,ADDR[3:0]formtheaddressfield. The remaining28 bitsformthedatafieldDATA[27:0]. Duringprogramming,LEuWire islow and serialdataisclockedinon therisingedge ofclock(MSB first).When LEuWire goes high,dataistransferredtotheregisterbank selectedby theaddressfield.Only registersR0 to R7, R11, R14, and R15 need tobe programmed forproperdeviceoperation. ItisrequiredtoprogramregisterR14. RECOMMENDED PROGRAMMING SEQUENCE The recommended programming sequence involvesprogramming R0 withthe resetbitset (RESET = 1) to ensurethedeviceisina defaultstate.Itisnotnecessarytoprogram R0 again.Registersare programmed in orderwithR15 beingthelastregisterprogrammed.An example programmingsequence isshown below.

  • Program R0 withtheresetbitset(RESET = 1).Thisensuresthedeviceisina defaultstate.
  • Program R4 toR7 as necessarywithdesiredclockswithappropriateenable,mux, divider,and delaysettings.
  • Program R11 withDIV4 settingifnecessary.
  • Program R14 withglobalclockoutputbit,power down setting,PLL mux setting,and PLL R divider.Itis requiredtoprogramregisterR14. – R14 must be programmed in accordance withthe registermap as shown in the registermap (see Table1).
  • Program R15 withPLL chargepump gain,and PLL N divider. Copyright© 2007,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:LMK02002

SNAS418 –AUGUST 2007 www.ti.com Table1.LMK02002 REGISTER MAP Re gist 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 er Data [27:0] A3 A2 A1 A0 RE R0 SE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T CLCLKout0 Kou CLKout0_DIV CLKout0_DLYR4 0 0 0 0 0 0 0 0 0 0 0 0 0 _MUX 0 1 0 0t0_ [7:0] [3:0][1:0] EN CLCLKout1 Kou CLKout1_DIV CLKout1_DLYR5 0 0 0 0 0 0 0 0 0 0 0 0 0 _MUX 0 1 0 1t1_ [7:0] [3:0][1:0] EN CLCLKout2 Kou CLKout2_DIV CLKout2_DLYR6 0 0 0 0 0 0 0 0 0 0 0 0 0 _MUX 0 1 1 0t2_ [7:0] [3:0][1:0] EN CLCLKout3 Kou CLKout3_DIV CLKout3_DLYR7 0 0 0 0 0 0 0 0 0 0 0 0 0 _MUX 0 1 1 1t3_ [7:0] [3:0][1:0] EN DIVR11 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 14 EN PO TRI PLL_CL WE - _CKou PLL_MUX PLL_RR14 0 0 1 0 RD ST P_ 0 0 0 0 1 1 1 0t_Gl [3:0] [11:0]OW AT POoba N E Ll PLL_ CP_ PLL_NR15 0 0 0 0 0 0 0 0 1 1 1 1GAIN [17:0] [1:0]

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www.ti.com SNAS418 –AUGUST 2007 REGISTER R4 toR7 RegistersR4 throughR7 controlthe eightclockoutputs.RegisterR4 controlsCLKout0, RegisterR5 controls CLKout1,and so on.There isone additionalbitinregisterR0 calledRESET. Asidefrom this,thefunctionsof thesebitsare identical.The X inCLKoutX_MUX, CLKoutX_DIV, CLKoutX_DLY, and CLKoutX_EN denotethe actualclockoutputwhichmay be from0 to3. RESET bit--R0 only ThisbitisonlyinregisterR0. The use ofthisbitisoptionaland itshouldbe setto'0'ifnotused.Settingthisbit toa '1'forcesallregisterstotheirpower on resetconditionand thereforeautomaticallyclearsthisbit.Ifthisbitis set,allotherR0 bitsare ignoredand R0 needs to be programmed againifused withitspropervaluesand RESET = 0. Default BitBitName BitState BitDescription RegisterBitValue Location RESET 0 No reset,normaloperation Resettopower on defaults R0 31 CLKoutX_MUX 0 Bypassed CLKoutX mux mode 18:17 CLKoutX_EN 0 Disabled CLKoutX enable 16 R4 toR7 CLKoutX_DIV 1 Divideby 2 CLKoutX clockdivide 15:8 CLKoutX_DLY 0 0 ps CLKoutX clockdelay 7:4 DIV4 0 PDF ≤ 20 MHz Phase DetectorFrequency R11 15 EN_CLKout_Global 1 Normal -CLKouts normal Globalclockoutputenable 27 POWERDOWN 0 Normal -Deviceactive Devicepower down 26 PLL_CP_TRI 0 Normal -PLL active TRI-STATE PLL chargepump 25 R14 PLL_CP_POL 0 NegativePolarityCP Polarityofchargepump 24 PLL_MUX 0 Disabled MultiplexercontrolforLD pin 23:20 PLL_R 10 R divider= 10 PLL R dividevalue 19:8 PLL_CP_GAIN 0 100 uA Charge pump current 31:30 R15 PLL_N 760 N divider= 760 PLL N dividevalue 25:8 CLKoutX_MUX[1:0] --Clock Output Multiplexers These bitscontrolthe Clock OutputMultiplexerforeach clockoutput.Changing between the differentmodes changes the blocksinthe signalpath and thereforeincursa delayrelativeto the bypass mode. The different MUX modes and associateddelaysarelistedbelow. CLKoutX_MUX[1:0] Mode Added Delay RelativetoBypass Mode

0 Bypassed (default) 0 ps

1 Divided 100 ps

400 ps2 Delayed (Inadditiontotheprogrammed delay) 500 ps3 Dividedand Delayed (Inadditiontotheprogrammed delay) CLKoutX_DIV[7:0]--Clock Output Dividers These bitscontrolthe clockoutputdividervalue.In orderforthese dividersto be active,the respective CLKoutX_MUX (See CLKoutX_MUX[1:0] --Clock Output Multiplexers) bitmust be set to either"Divided"or "Dividedand Delayed"mode. Afterallthedividersareprogramed,theSYNC* pinmust be used toensurethatall edges of the clockoutputsare aligned(See GLOBAL CLOCK OUTPUT SYNCHRONIZATION ).The Clock OutputDividersfollowthe VCO Dividerso the finalclockdivideforan outputisVCO Divider× Clock Output Divider.By addingthedividerblocktotheoutputpatha fixeddelayofapproximately100 ps isincurred. The actualClockOutputDividevalueistwicethebinaryvalueprogrammed as listedinthetablebelow. Copyright© 2007,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:LMK02002

SNAS418 –AUGUST 2007 www.ti.com CLKoutX_DIV[7:0] Clock Output Dividervalue 0 0 0 0 0 0 0 0 Invalid 0 0 0 0 0 0 0 1 2 (default) 0 0 0 0 0 0 1 0 4 0 0 0 0 0 0 1 1 6 0 0 0 0 0 1 0 0 8 0 0 0 0 0 1 0 1 10 1 1 1 1 1 1 1 1 510 CLKoutX_DLY[3:0] --Clock Output Delays These bitscontrolthedelaystagesforeach clockoutput.Inorderforthesedelaystobe active,therespective CLKoutX_MUX (See CLKoutX_MUX[1:0] --Clock OutputMultiplexers) bitmust be setto either"Delayed"or "Dividedand Delayed"mode. By addingthedelayblocktotheoutputpatha fixeddelayofapproximately400 ps isincurredinadditiontothedelayshown inthetablebelow. CLKoutX_DLY[3:0] Delay (ps) 0 0 (default) 1 150 2 300 3 450 4 600 5 750 6 900 7 1050 8 1200 9 1350 10 1500 11 1650 12 1800 13 1950 14 2100 15 2250 CLKoutX_EN bit--Clock Output Enables These bitscontrolwhether an individualclockoutputis enabled or not.Ifthe EN_CLKout_Global bit(See EN_CLKout_Global bit--GlobalClockOutputEnable)issettozeroorifGOE pinisheldlow,allCLKoutX_EN bitstateswillbe ignoredand allclockoutputswillbe disabled.See CLKout OUTPUT STATES formore informationon CLKout states. CLKoutX_EN bit Conditions CLKoutX State

0 EN_CLKout_Globalbit= 1 Disabled(default)

GOE pin= High/No Connect11 Enabled REGISTER R11 Thisregisteronlyhas one bitand onlyneeds tobe programmed inthecase thatthephase detectorfrequencyis greaterthan20 MHz and digitallockdetectisused.Otherwise,itisautomaticallydefaultedtothecorrectvalues. DIV4 Thisbitdividesthefrequencypresentedtothedigitallockdetectcircuitryby 4.Itisnecessarytogeta reliable outputfromthedigitallockdetectoutputinthecase ofa phase detectorfrequencygreaterthan20 MHz.

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www.ti.com SNAS418 –AUGUST 2007 DIV4 DigitalLock DetectCircuitryMode

0 Not divided;Phase detectorfrequency≤ 20 MHz (default)

1 Dividedby 4;Phase detectorfrequency> 20 MHz

The LMK02002 requiresregisterR14 tobe programmed as shown intheregistermap (seeTable1). PLL_R[11:0]--R DividerValue These bitsprogramthePLL R Dividerand areprogrammed inbinaryfashion. PLL_R[11:0] PLL R DivideValue 0 0 0 0 0 0 0 0 0 0 0 0 Invalid 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 2 0 0 0 0 0 0 0 0 1 0 1 0 10 (default) 1 1 1 1 1 1 1 1 1 1 1 1 4095 PLL_MUX[3:0] --MultiplexerControlforLD Pin These bitssettheoutputmode oftheLD pin.The tablebelowlistsseveraldifferentmodes. PLL_MUX[3:0] Output Type LD Pin Function

0 Hi-Z Disabled(default)

1 Push-Pull LogicHigh

2 Push-Pull LogicLow

3 Push-Pull DigitalLock Detect(ActiveHigh)

4 Push-Pull DigitalLock Detect(ActiveLow)

5 Push-Pull AnalogLock Detect

6 Open DrainNMOS AnalogLock Detect

7 Open DrainPMOS AnalogLock Detect

8 Invalid

9 Push-Pull N DividerOutput/2(50% DutyCycle)

10 Invalid

11 Push-Pull R DividerOutput/2(50% DutyCycle)

POWERDOWN bit--Device Power Down Thisbitcan power down thedevice.Enablingthisbitpowers down theentiredeviceand allblocks,regardlessof thestateofany oftheotherbitsorpins. POWERDOWN bit Mode

0 Normal Operation(default)

1 EntireDevicePowered Down

EN_CLKout_Global bit--GlobalClock Output Enable ThisbitoverridestheindividualCLKoutX_EN bits(See CLKoutX_EN bit--ClockOutputEnables).When thisbit issetto0,allclockoutputsare disabled,regardlessofthestateofany oftheotherbitsor pins.See CLKout OUTPUT STATES formore informationon CLKout states. Copyright© 2007,Texas InstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:LMK02002

SNAS418 –AUGUST 2007 www.ti.com EN_CLKout_Global bit Clock Outputs

0 AllOff

1 Normal Operation(default)

PLL_CP_TRI bit--PLL Charge Pump TRI-STATE ThisbitsetsthePLL chargepump TRI-STATE. PLL_CP_TRI PLL Charge Pump

1 TRI-STATE

PLL_CP_POL bit--PLL Charge Pump Polarity Thisbitsetsthepolarityofthechargepump toeithernegativeorpositive.A negativechargepump isused witha VCO orVCXO whichdecreasesfrequencywithincreasingtuningvoltage.A positivechargepump isused witha VCO orVCXO whichincreasesfrequencywithincreasingtuningvoltage. PLL_CP_POL PLL Charge Pump Polarity

0 Negative(default)

1 Positive

PLL_N[17:0]--PLL N Divider These bitsprogram the dividevalueforthe PLL N Divider.The PLL N Dividerfollowsthe VCO Dividerand precedesthePLL phase detector.SincetheVCO DividerisalsointhefeedbackpathfromtheVCO tothePLL Phase Detector,the totalN dividevalue,N Total, isalsoinfluencedby the VCO Dividervalue.N Total= PLL N Divider× VCO Divider.The VCO frequencyiscalculatedas,fVCO = fOSCin × PLL N Divider× VCO Divider/PLL R Divider.Since the PLL N dividerisa pure binarycounter,thereare no illegaldividevaluesforPLL_N[17:0] exceptfor0. PLL_N[17:0] PLL N DividerValue 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Invalid 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 0 1 1 1 1 1 0 0 0 760 (default) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 262143 PLL_CP_GAIN[1:0] --PLL Charge Pump Gain These bitssetthechargepump gainofthePLL. PLL_CP_GAIN[1:0] Charge Pump Gain 0 1x (default) 1 4x 2 16x 3 32x

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(optional) To Host CLKout0 CLKout0* CLKout1 CLKout1* CLKout2 CLKout2* CLKout3 CLKout3* To System SYNC* OSCin OSCin* Bias Vcc LDObyp1 LDObyp2 10 PF 0.1 PF 1 PF0.1 PF 0.1 PF LMK02002 Fin Fin* 0.1 PF0.1 PF 100Ö 100Ö LMK02002 www.ti.com SNAS418 –AUGUST 2007

APPLICATION INFORMATION

The followingshows the LMK02002 in a typicalapplication.In thissetup the clock may be multiplied, reconditioned,and redistributed. Figure2. TypicalApplication BIAS PIN To properlyuse thedevice,bypass Bias(pin36) witha low leakage1 µF capacitorconnectedtoVcc.Thisis importantforlownoiseperformance. LDO BYPASS To properlyuse thedevice,bypass LDObyp1 (pin9)witha 10 µF capacitorand LDObyp2 (pin10)witha 0.1µF capacitor. CURRENT CONSUMPTION /POWER DISSIPATION CALCULATIONS Due tothemyriadofpossibleconfigurationsthefollowingtableservestoprovideenough informationtoallowthe usertocalculateestimatedcurrentconsumptionoftheLMK02002. UnlessotherwisenotedVcc = 3.3V, TA = 25 °C. Copyright© 2007,Texas InstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:LMK02002

SNAS418 –AUGUST 2007 www.ti.com Table2. Block CurrentConsumption PowerCurrent Power DissipatedinBlock Condition Consumption at Dissipatedin LVPECL emitter3.3V (mA) device(mW) resistors(mW) Entiredevice, Alloutputsoff;No LVPECL emitterresistorsconnected 70 231 -corecurrent Clockbuffers The lowclockbufferisenabledanytimeone ofCLKout0 9 29.7 -(internal) throughCLKout3 areenabled LVPECL output,bypassmode (includes120 Ω emitter 40 72 60resistors) LVPECL output,disabledmode (includes120 Ω emitterOutputbuffers 17.4 38.3 19.1resistors) LVPECL output,disabledmode. No emitterresistors 0 0 -placed;open outputs Divideenabled,divide= 2 5.3 17.5 -Dividecircuitry peroutput Divideenabled,divide> 2 8.5 28.0 - Delayenabled,delay< 8 5.8 19.1 -Delaycircuitryper output Delayenabled,delay> 7 9.9 32.7 - Entiredevice CLKout0 & CLKout3 enabledinbypassmode 159 404.7 120 From Table2 thecurrentconsumptioncan be calculatedinany configuration.For example,thecurrentforthe entiredevicewithtwo LVPECL (CLKout0and CLKout3)outputsinbypass mode can be calculatedby addingup thefollowingblocks:corecurrent,clockbuffers,and two LVPECL outputbuffercurrents.There willalsobe two LVPECL outputsdrawingemittercurrent,but some of the power from the currentdraw isdissipatedin the external120 Ω resistorswhichdoesn'tadd tothepower dissipationbudgetforthedevice.Ifdelaysordividesare switchedin,thentheadditionalcurrentforthesestagesneeds tobe added as well. For power dissipatedby thedevice,thetotalcurrententeringthedeviceismultipliedby thevoltageatthedevice minus the power dissipatedin any emitterresistorsconnectedto any of the LVPECL outputs.Ifno emitter resistorsare connectedto the LVPECL outputs,thispower willbe 0 watts.For example,inthe case of two LVPECL (CLKout0and CLKout3)operatingat3.3volts,we calculate3.3V × (70+ 9 + 40 + 40)mA = 3.3V × 159 mA = 524.7mW. Because theLVPECL outputshave emitterresistorshooked up and thepower dissipated by theseresistorsis60 mW foreach clock,thetotaldevicepower dissipationis524.7mW - 120 mW = 404.7 mW. When an LVPECL outputisactive,~1.9V istheaveragevoltageon each outputas calculatedfromtheLVPECL VOH & VOL typicalspecification.Thereforethepower dissipatedineach emitterresistorisapproximately(1.9V)2 / 120 Ω = 30 mW. When an LVPECL outputisdisabled,the emitterresistorvoltageis~1.07 V. Thereforethe power dissipatedineach emitterresistorisapproximately(1.07V)2 /120 Ω = 9.5mW. THERMAL MANAGEMENT Power consumptionof the LMK02002 can be high enough to requireattentionto thermalmanagement. For reliabilityand performancereasonsthedietemperatureshouldbe limitedtoa maximum of125 °C. Thatis,as an estimate,TA (ambienttemperature)plusdevicepower consumptiontimesθJA shouldnotexceed 125 °C. The package ofthedevicehas an exposed pad thatprovidestheprimaryheatremovalpathas wellas excellent electricalgroundingtotheprintedcircuitboard.To maximize theremovalofheatfrom thepackage a thermal landpatternincludingmultipleviastoa groundplanemust be incorporatedon thePCB withinthefootprintofthe package.The exposed pad must be soldereddown toensureadequateheatconductionoutofthepackage.A recommended landand viapatternisshown inFigure3.More informationon solderingWQFN packages can be obtainedatwww.ti.com.

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0.33 mm, typ 1.2 mm, typ 5.0 mm, min LMK02002 www.ti.com SNAS418 –AUGUST 2007 Figure3. To minimizejunctiontemperatureitisrecommended thata simpleheatsinkbe builtintothePCB (iftheground planelayerisnotexposed).Thisisdone by includinga copperarea ofabout2 squareincheson theopposite sideof the PCB from the device.Thiscopper area may be platedor soldercoatedto preventcorrosionbut shouldnot have conformalcoating(ifpossible),which couldprovidethermalinsulation.The viasshown in Figure3 shouldconnectthesetopand bottomcopperlayersand totheground layer.These viasactas “heat pipes” tocarrythethermalenergyaway from thedevicesideoftheboard towhere itcan be more effectively dissipated. Copyright© 2007,Texas InstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:LMK02002

www.ti.com 11-Nov-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) LMK02002ISQ/NOPB Active Production WQFN (RHS) | 48 250 | SMALL T&R Yes SN Level-3-260C-168 HR -40 to 85 K02002 I LMK02002ISQ/NOPB.A Active Production WQFN (RHS) | 48 250 | SMALL T&R Yes SN Level-3-260C-168 HR -40 to 85 K02002 I LMK02002ISQX/NOPB Active Production WQFN (RHS) | 48 2500 | LARGE T&R Yes SN Level-3-260C-168 HR -40 to 85 K02002 I LMK02002ISQX/NOPB.A Active Production WQFN (RHS) | 48 2500 | LARGE T&R Yes SN Level-3-260C-168 HR -40 to 85 K02002 I (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 1-Aug-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 1-Aug-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMK02002ISQ/NOPB WQFN RHS 48 250 208.0 191.0 35.0 LMK02002ISQX/NOPB WQFN RHS 48 2500 356.0 356.0 36.0 Pack Materials-Page 2

www.ti.com PACKAGE OUTLINE C SEE TERMINAL DETAIL 48X 0.30 0.18 5.1 0.1 48X 0.5 0.3 0.8 0.7 (A) TYP 0.05 0.00 44X 0.5 5.5 2X 5.5 A 7.15 6.85 B 7.15 6.85 0.30 0.18 0.5 0.3 (0.2) WQFN - 0.8 mm max heightRHS0048A PLASTIC QUAD FLATPACK - NO LEAD 4214990/B 04/2018 DIM A OPT 1 OPT 2 (0.1) (0.2) PIN 1 INDEX AREA 0.08 C SEATING PLANE 12 25 13 24 48 37 (OPTIONAL) PIN 1 ID 0.1 C A B 0.05 EXPOSED THERMAL PAD

49 SYMM

NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. SCALE 1.800 DETAIL OPTIONAL TERMINAL TYPICAL

www.ti.com EXAMPLE BOARD LAYOUT

0.07 MIN

0.07 MAX

48X (0.25) 48X (0.6) ( 0.2) TYP VIA 44X (0.5) (6.8) (6.8) (1.25) TYP ( 5.1) (R0.05) TYP (1.25) TYP (1.05) TYP (1.05) TYP WQFN - 0.8 mm max heightRHS0048A PLASTIC QUAD FLATPACK - NO LEAD 4214990/B 04/2018 SYMM 13 24 3748 SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:12X NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL METAL EDGE SOLDER MASK OPENING SOLDER MASK DETAILS NON SOLDER MASK DEFINED (PREFERRED) EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN 48X (0.6) 48X (0.25) 44X (0.5) (6.8) (6.8) 16X ( 1.05) (0.625) TYP (R0.05) TYP (1.25) TYP (1.25) TYP (0.625) TYP WQFN - 0.8 mm max heightRHS0048A PLASTIC QUAD FLATPACK - NO LEAD 4214990/B 04/2018 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SYMM METAL TYP SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 49 68% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:15X SYMM 13 24 3748

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