LMK02000

LMK02000 Precision Clock Conditioner with Integrated PLL datasheet (Rev. D)

Document overview

• Manufacturer or author: Texas Instruments, Incorporated [SNAS390,D]
• PDF pages: 29

Technical content

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LMK02000 SNAS390D – NOVEMBER 2006– REVISED SEPTEMBER 2007 PrecisionClockConditionerwithIntegratedPLL Check for Samples: LMK02000 All trademarks are the property of their respective owners.

1 Features

1• 20 fs Additive Jitter

• Integrated Integer-N PLL with Outstanding Normalized Phase Noise Contribution of -224 dBc/Hz
• Clock Output Frequency Range of 1 to 800 MHz
• 3 LVDS and 5 LVPECL Clock Outputs
• Dedicated Divider and Delay Blocks on Each Clock Output
• Pin Compatible Family of Clocking Devices
• 3.15 to 3.45 V Operation
• Package: 48 Pin WQFN (7.0 x 7.0 x 0.8 mm)

2 Target Applications

• Data Converter Clocking
• Networking, SONET/SDH, DSLAM
• Wireless Infrastructure
• Medical
• Test and Measurement
• Military / Aerospace

3 Description

The LMK02000 precision clock conditioner combines the functions of jitter cleaning/reconditioning, multiplication, and distribution of a reference clock. The device integrates a high performance Integer-N Phase Locked Loop (PLL), three LVDS, and five LVPECL clock output distribution blocks. Each clock distribution block includes a programmable divider, a phase synchronization circuit, a programmable delay, a clock output mux, and an LVDS or LVPECL output buffer. This allows multiple integer-related and phase-adjusted copies of the reference to be distributed to eight system components. The clock conditioner comes in a 48-pin WQFN package and is footprint compatible with other clocking devices in the same family.

OSCin* R Divider Phase Detector N Divider CLKout0 CLKout0* CLKout1 CLKout1* CLKout2 CLKout2* CLKout3 CLKout3* CLKout4 CLKout4* CLKout5 CLKout5* CLKout6 CLKout6* CLKout7 CLKout7* Divider Delay Mux Divider Delay Mux Divider Delay Mux Divider Delay Mux Divider Delay Mux Divider Delay Mux Divider Delay Mux Divider Delay Mux Distribution Path CLK DATA LE Control Registers PWire Port Device Control LDGOE SYNC* Fin Fin* Charge Pump CPout Low Clock Buffers High Clock Buffers LMK02000 SNAS390D – NOVEMBER 2006– REVISED SEPTEMBER 2007 www.ti.com Product Folder Links: LMK02000 Submit Documentation Feedback Copyright © 2006–2007, Texas Instruments Incorporated

3.1 Functional Block Diagram

3.2 Connection Diagram

Figure 1. 48-Pin WQFN Package

4 CLKuWire I MICROWIRE Clock Input

5 DATAuWire I MICROWIRE Data Input

6 LEuWire I MICROWIRE Latch Enable Input

11 GOE I Global Output Enable

12 LD O Lock Detect and Test Output

27 SYNC* I Global Clock Output Synchronization

SNAS390D – NOVEMBER 2006– REVISED SEPTEMBER 2007 www.ti.com Product Folder Links: LMK02000 Submit Documentation Feedback Copyright © 2006–2007, Texas Instruments Incorporated Connection Diagram (continued) Pin Descriptions (continued) Pin # Pin Name I/O Description

32 CPout O Charge Pump Output

34, 35 Fin, Fin* I Frequency Input; Must be AC coupled

36 Bias I Bias Bypass

38, 39 CLKout4, CLKout4* O LVPECL Clock Output 4 41, 42 CLKout5, CLKout5* O LVPECL Clock Output 5 44, 45 CLKout6, CLKout6* O LVPECL Clock Output 6 47, 48 CLKout7, CLKout7* O LVPECL Clock Output 7 DAP DAP - Die Attach Pad is Ground These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. (1) "Absolute Maximum Ratings" indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. (2) This device is a high performance integrated circuit with ESD handling precautions. Handling of this device should only be done at ESD protected work stations. The device is rated to a HBM-ESD of > 2 kV, a MM-ESD of > 200 V, and a CDM-ESD of > 1.2 kV. (3) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications.

4 Absolute Maximum Ratings (1)(2)(3)

Parameter Symbol Ratings Units Power Supply Voltage VCC -0.3 to 3.6 V Input Voltage VIN -0.3 to (VCC + 0.3) V Storage Temperature Range TSTG -65 to 150 °C Lead Temperature (solder 4 s) TL +260 °C Junction Temperature TJ 125 °C

5 Recommended Operating Conditions

Parameter Symbol Min Typ Max Units Ambient Temperature TA -40 25 85 °C Power Supply Voltage VCC 3.15 3.3 3.45 V (1) Specification assumes 16 thermal vias connect the die attach pad to the embedded copper plane on the 4-layer JEDEC board. These vias play a key role in improving the thermal performance of the WQFN. It is recommended that the maximum number of vias be used in the board layout.

6 Package Thermal Resistance

Package θJA θJ-PAD (Thermal Pad) 48-Lead WQFN (1) 27.4° C/W 5.8° C/W

www.ti.com SNAS390D – NOVEMBER 2006– REVISED SEPTEMBER 2007 Product Folder Links: LMK02000 Submit Documentation FeedbackCopyright © 2006–2007, Texas Instruments Incorporated (1) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not ensured. (2) See CURRENT CONSUMPTION / POWER DISSIPATION CALCULATIONS for more current consumption / power dissipation calculation information. (3) For all frequencies the slew rate, SLEWFin, is measured between 20% and 80%. (4) Specification is ensured by characterization and is not tested in production. (5) A specification in modeling PLL in-band phase noise is the 1/f flicker noise, LPLL_flicker(f), which is dominant close to the carrier. Flicker noise has a 10 dB/decade slope. PN10kHz is normalized to a 10 kHz offset and a 1 GHz carrier frequency. PN10kHz = LPLL_flicker(10 kHz) - 20log(Fout / 1 GHz), where LPLL_flicker(f) is the single side band phase noise of only the flicker noise's contribution to total noise, L(f). To measure LPLL_flicker(f) it is important to be on the 10 dB/decade slope close to the carrier. A high phase detector frequency and a clean crystal are important to isolating this noise source from the total phase noise, L(f). LPLL_flicker(f) can be masked by the reference oscillator performance if a low power or noisy source is used. The total PLL inband phase noise performance is the sum of LPLL_flicker(f) and LPLL_flat(f).

7 Electrical Characteristics (1)

(3.15 V ≤ Vcc ≤ 3.45 V, -40 °C ≤ TA ≤ 85 °C, Differential Inputs/Outputs; except as specified. Typical values represent most likely parametric norms at Vcc = 3.3 V, TA = 25 °C, and at the Recommended Operation Conditions at the time of product characterization and are not specified). Symbol Parameter Conditions Min Typ Max Units Current Consumption ICC Power Supply Current (2) Entire device; CLKout0 & CLKout4 enabled in Bypass Mode 145.8 mA Entire device; All Outputs Off (no emitter resistors placed) 70 ICCPD Power Down Current POWERDOWN = 1 1 mA Reference Oscillator fOSCin square Reference Oscillator Input Frequency Range for Square Wave AC coupled; Differential (VOD) 1 200 MHz VOSCinsquare Square Wave Input Voltage for OSCin and OSCin* 0.2 1.6 Vpp Frequency Input fFin Frequency Input Frequency Range 1 800 MHz SLEWFin Frequency Input Slew Rate (3)(4)0.5 V/ns DUTYFin Frequency Input Duty Cycle 40 60 % PFin Input Power Range for Fin or Fin* AC coupled -13 8 dBm PLL fCOMP Phase Detector Frequency 40 MHz ISRCECPout Charge Pump Source Current VCPout = Vcc/2, PLL_CP_GAIN = 1x 100 µA VCPout = Vcc/2, PLL_CP_GAIN = 4x 400 VCPout = Vcc/2, PLL_CP_GAIN = 16x 1600 VCPout = Vcc/2, PLL_CP_GAIN = 32x 3200 ISINKCPout Charge Pump Sink Current VCPout = Vcc/2, PLL_CP_GAIN = 1x -100 μA VCPout = Vcc/2, PLL_CP_GAIN = 4x -400 VCPout = Vcc/2, PLL_CP_GAIN = 16x -1600 VCPout = Vcc/2, PLL_CP_GAIN = 32x -3200 ICPoutTRI Charge Pump TRI-STATE Current 0.5 V < VCPout < Vcc - 0.5 V 2 10 nA ICPout%MIS Magnitude of Charge Pump Sink vs. Source Current Mismatch VCPout = Vcc / 2 TA = 25°C 3 % ICPoutVTUNE Magnitude of Charge Pump Current vs. Charge Pump Voltage Variation 0.5 V < VCPout < Vcc - 0.5 V TA = 25°C 4 % ICPoutTEMP Magnitude of Charge Pump Current vs. Temperature Variation 4 % PN10kHz PLL 1/f Noise at 10 kHz Offset (5) Normalized to 1 GHz Output Frequency PLL_CP_GAIN = 1x -117 dBc/Hz PLL_CP_GAIN = 32x -122

SNAS390D – NOVEMBER 2006– REVISED SEPTEMBER 2007 www.ti.com Product Folder Links: LMK02000 Submit Documentation Feedback Copyright © 2006–2007, Texas Instruments Incorporated Electrical Characteristics (1) (continued) (3.15 V ≤ Vcc ≤ 3.45 V, -40 °C ≤ TA ≤ 85 °C, Differential Inputs/Outputs; except as specified. Typical values represent most likely parametric norms at Vcc = 3.3 V, TA = 25 °C, and at the Recommended Operation Conditions at the time of product characterization and are not specified). Symbol Parameter Conditions Min Typ Max Units (6) A specification in modeling PLL in-band phase noise is the Normalized Phase Noise Contribution, LPLL_flat(f), of the PLL and is defined as PN1Hz = LPLL_flat(f) – 20log(N) – 10log(fCOMP). LPLL_flat(f) is the single side band phase noise measured at an offset frequency, f, in a 1 Hz Bandwidth and fCOMP is the phase detector frequency of the synthesizer. LPLL_flat(f) contributes to the total noise, L(f). To measure LPLL_flat(f) the offset frequency, f, must be chosen sufficiently smaller then the loop bandwidth of the PLL, and yet large enough to avoid a substantial noise contribution from the reference and flicker noise. LPLL_flat(f) can be masked by the reference oscillator performance if a low power or noisy source is used. (7) The Clock Distribution Section includes all parts of the device except the PLL section. Typical Additive Jitter specifications apply to the clock distribution section only. (8) Applies to GOE, LD, and SYNC*. PN1Hz Normalized Phase Noise Contribution (6) PLL_CP_GAIN = 1x -219 dBc/Hz PLL_CP_GAIN = 32x -224 Clock Distribution Section (7) - LVDS Clock Outputs (CLKout0 to CLKout2) JitterADD Additive RMS Jitter (7) RL = 100 Ω Distribution Path =

800 MHz

Bandwidth = 12 kHz to 20 MHz CLKoutX_MUX = Bypass 20 fsCLKoutX_MUX = Divided CLKoutX_DIV = tSKEW CLKoutX to CLKoutY (4) Equal loading and identical clock configuration RL = 100 Ω -30 ±4 30 ps VOD Differential Output Voltage RL = 100 Ω 250 350 450 mV ΔVOD Change in magnitude of VOD for complementary output states RL = 100 Ω -50 50 mV VOS Output Offset Voltage RL = 100 Ω 1.070 1.25 1.370 V ΔVOS Change in magnitude of VOS for complementary output states RL = 100 Ω -35 35 mV ISA ISB Clock Output Short Circuit Current single ended Single ended outputs shorted to GND -24 24 mA ISAB Clock Output Short Circuit Current differential Complementary outputs tied together -12 12 mA Clock Distribution Section (7) - LVPECL Clock Outputs (CLKout3 to CLKout7) JitterADD Additive RMS Jitter (7) RL = 100 Ω Distribution Path = Bandwidth = 12 kHz to 20 MHz CLKoutX_MUX = Bypass 20 fsCLKoutX_MUX = Divided CLKoutX_DIV = tSKEW CLKoutX to CLKoutY (4) Equal loading and identical clock configuration Termination = 50 Ω to Vcc - 2 V -30 ±3 30 ps VOH Output High Voltage Termination = 50 Ω to Vcc - 2 V Vcc - 0.98 V VOL Output Low Voltage Vcc - 1.8 V VOD Differential Output Voltage 660 810 965 mV Digital LVTTL Interfaces (8) VIH High-Level Input Voltage 2.0 Vcc V VIL Low-Level Input Voltage 0.8 V IIH High-Level Input Current VIH = Vcc -5.0 5.0 µA IIL Low-Level Input Current VIL = 0 -40.0 5.0 µA VOH High-Level Output Voltage IOH = +500 µA Vcc - 0.4 V

www.ti.com SNAS390D – NOVEMBER 2006– REVISED SEPTEMBER 2007 Product Folder Links: LMK02000 Submit Documentation FeedbackCopyright © 2006–2007, Texas Instruments Incorporated Electrical Characteristics (1) (continued) (3.15 V ≤ Vcc ≤ 3.45 V, -40 °C ≤ TA ≤ 85 °C, Differential Inputs/Outputs; except as specified. Typical values represent most likely parametric norms at Vcc = 3.3 V, TA = 25 °C, and at the Recommended Operation Conditions at the time of product characterization and are not specified). Symbol Parameter Conditions Min Typ Max Units (9) Applies to CLKuWire, DATAuWire, and LEuWire. VOL Low-Level Output Voltage IOL = -500 µA 0.4 V Digital MICROWIRE Interfaces (9) VIH High-Level Input Voltage 1.6 Vcc V VIL Low-Level Input Voltage 0.4 V IIH High-Level Input Current VIH = Vcc -5.0 5.0 µA IIL Low-Level Input Current VIL = 0 -5.0 5.0 µA MICROWIRE Timing tCS Data to Clock Set Up Time See Data Input Timing 25 ns tCH Data to Clock Hold Time See Data Input Timing 8 ns tCWH Clock Pulse Width High See Data Input Timing 25 ns tCWL Clock Pulse Width Low See Data Input Timing 25 ns tES Clock to Enable Set Up Time See Data Input Timing 25 ns tCES Enable to Clock Set Up Time See Data Input Timing 25 ns tEWH Enable Pulse Width High See Data Input Timing 25 ns

SNAS390D – NOVEMBER 2006– REVISED SEPTEMBER 2007 www.ti.com Product Folder Links: LMK02000 Submit Documentation Feedback Copyright © 2006–2007, Texas Instruments Incorporated

8 Serial Data Timing Diagram

Data bits set on the DATAuWire signal are clocked into a shift register, MSB first, on each rising edge of the CLKuWire signal. On the rising edge of the LEuWire signal, the data is sent from the shift register to the addressed register determined by the LSB bits. After the programming is complete the CLKuWire, DATAuWire, and LEuWire signals should be returned to a low state.

www.ti.com SNAS390D – NOVEMBER 2006– REVISED SEPTEMBER 2007 Product Folder Links: LMK02000 Submit Documentation FeedbackCopyright © 2006–2007, Texas Instruments Incorporated

9 Charge Pump Current Specification Definitions

I1 = Charge Pump Sink Current at VCPout = Vcc - ΔV I2 = Charge Pump Sink Current at VCPout = Vcc/2 I3 = Charge Pump Sink Current at VCPout = ΔV I4 = Charge Pump Source Current at VCPout = Vcc - ΔV I5 = Charge Pump Source Current at VCPout = Vcc/2 I6 = Charge Pump Source Current at VCPout = ΔV ΔV = Voltage offset from the positive and negative supply rails. Defined to be 0.5 V for this device. Charge Pump Output Current Magnitude Variation vs. Charge Pump Output Voltage Charge Pump Sink Current vs. Charge Pump Output Source Current Mismatch Charge Pump Output Current Magnitude Variation vs. Temperature

SNAS390D – NOVEMBER 2006– REVISED SEPTEMBER 2007 www.ti.com Product Folder Links: LMK02000 Submit Documentation Feedback Copyright © 2006–2007, Texas Instruments Incorporated Charge Pump Current Specification Definitions (continued)

www.ti.com SNAS390D – NOVEMBER 2006– REVISED SEPTEMBER 2007 Product Folder Links: LMK02000 Submit Documentation FeedbackCopyright © 2006–2007, Texas Instruments Incorporated

10 Functional Description

The LMK02000 precision clock conditioner combines the functions of jitter cleaning/reconditioning, multiplication, and distribution of a reference clock. The device integrates a high performance Integer-N Phase Locked Loop (PLL), three LVDS, and five LVPECL clock output distribution blocks. Each clock distribution block includes a programmable divider, a phase synchronization circuit, a programmable delay, a clock output mux, and an LVDS or LVPECL output buffer. This allows multiple integer-related and phase-adjusted copies of the reference to be distributed to eight system components. The clock conditioner comes in a 48-pin WQFN package and is footprint compatible with other clocking devices in the same family.

10.1 BIAS PIN

To properly use the device, bypass Bias (pin 36) with a low leakage 1 µF capacitor connected to Vcc. This is important for low noise performance.

10.2 LDO BYPASS

To properly use the device, bypass LDObyp1 (pin 9) with a 10 µF capacitor and LDObyp2 (pin 10) with a 0.1 µF capacitor.

10.3 OSCILLATOR INPUT PORT (OSCin, OSCin*)

The purpose of OSCin is to provide the PLL with a reference signal. The OSCin port must be AC coupled, refer to the System Level Diagram in the Application Information section. The OSCin port may be driven single endedly by AC grounding OSCin* with a 0.1 µF capacitor.

10.4 FREQUENCY INPUT PORT (Fin, Fin*)

The purpose of Fin is to provide the PLL with a feedback signal from an external oscillator. The Fin port may be driven single endedly by AC grounding Fin*.

10.5 CLKout DELAYS

Each individual clock output includes a delay adjustment. Clock output delay registers (CLKoutX_DLY) support a 150 ps step size and range from 0 to 2250 ps of total delay.

10.6 LVDS/LVPECL OUTPUTS

Each LVDS or LVPECL output may be disabled individually by programming the CLKoutX_EN bits. All the outputs may be disabled simultaneously by pulling the GOE pin low or programming EN_CLKout_Global to 0.

10.7 GLOBAL CLOCK OUTPUT SYNCHRONIZATION

The SYNC* pin synchronizes the clock outputs. When the SYNC* pin is held in a logic low state, the divided outputs are also held in a logic low state. When the SYNC* pin goes high, the divided clock outputs are activated and will transition to a high state simultaneously. Clocks in the bypassed state are not affected by SYNC* and are always synchronized with the divided outputs. The SYNC* pin must be held low for greater than one clock cycle of the Frequency Input port, also known as the distribution path. Once this low event has been registered, the outputs will not reflect the low state for four more cycles. Similarly once the SYNC* pin becomes high, the outputs will not simultaneously transition high until four more distribution path clock cycles have passed. See the timing diagram below for further detail. In the timing diagram below the clocks are programmed as CLKout0_MUX = Bypassed, CLKout1_MUX = Divided, CLKout1_DIV = 2, CLKout2_MUX = Divided, and CLKout2_DIV = 4.

SYNC* CLKout0 CLKout1 CLKout2 LMK02000 SNAS390D – NOVEMBER 2006– REVISED SEPTEMBER 2007 www.ti.com Product Folder Links: LMK02000 Submit Documentation Feedback Copyright © 2006–2007, Texas Instruments Incorporated

10.8 SYNC* Timing Diagram

The SYNC* pin provides an internal pull-up resistor as shown on the functional block diagram. If the SYNC* pin is not terminated externally the clock outputs will operate normally. If the SYNC* function is not used, clock output synchronization is not specified.

10.9 CLKout OUTPUT STATES

Each clock output may be individually enabled with the CLKoutX_EN bits. Each individual output enable control bit is gated with the Global Output Enable input pin (GOE) and the Global Output Enable bit (EN_CLKout_Global). All clock outputs can be disabled simultaneously if the GOE pin is pulled low by an external signal or EN_CLKout_Global is set to 0. CLKoutX _EN bit EN_CLKout _Global bit GOE pin Clock X Output State 1 1 Low Low Don't care 0 Don't care Off

0 Don't care Don't care Off

1 1 High / No Connect Enabled When an LVDS output is in the Off state, the outputs are at a voltage of approximately 1.5 volts. When an LVPECL output is in the Off state, the outputs are at a voltage of approximately 1 volt.

10.10 GLOBAL OUTPUT ENABLE AND LOCK DETECT

The GOE pin provides an internal pull-up resistor. If it is not terminated externally, the clock output states are determined by the Clock Output Enable bits (CLKoutX_EN) and the EN_CLKout_Global bit. By programming the PLL_MUX register to Digital Lock Detect Active High (See PLL_MUX[3:0] -- Multiplexer Control for LD Pin), the Lock Detect (LD) pin can be connected to the GOE pin in which case all outputs are set low automatically if the synthesizer is not locked.

10.11 POWER ON RESET

When supply voltage to the device increases monotonically from ground to Vcc, the power on reset circuit sets all registers to their default values, see RESET Bit -- R0 only for more information on default register values. Voltage should be applied to all Vcc pins simultaneously.

10.12 General Programming Information

The LMK02000 device is programmed using several 32-bit registers which control the device's operation. The registers consist of a data field and an address field. The last 4 register bits, ADDR[3:0] form the address field. The remaining 28 bits form the data field DATA[27:0].

www.ti.com SNAS390D – NOVEMBER 2006– REVISED SEPTEMBER 2007 Product Folder Links: LMK02000 Submit Documentation FeedbackCopyright © 2006–2007, Texas Instruments Incorporated General Programming Information (continued) During programming, LEuWire is low and serial data is clocked in on the rising edge of clock (MSB first). When LEuWire goes high, data is transferred to the register bank selected by the address field. Only registers R0 to R7, R11, R14, and R15 need to be programmed for proper device operation. It is required to program register R14.

10.12.1 RECOMMENDED PROGRAMMING SEQUENCE

The recommended programming sequence involves programming R0 with the reset bit set (RESET = 1) to ensure the device is in a default state. It is not necessary to program R0 again, but if R0 is programmed again, the reset bit is programmed clear (RESET = 0). Registers are programmed in order with R15 being the last register programmed. An example programming sequence is shown below.

• Program R0 with the reset bit set (RESET = 1). This ensures the device is in a default state. When the reset bit is set in R0, the other R0 bits are ignored. – If R0 is programmed again, the reset bit is programmed clear (RESET = 0).
• Program R0 to R7 as necessary with desired clocks with appropriate enable, mux, divider, and delay settings.
• Program R11 with DIV4 setting if necessary.
• Program R14 with global clock output bit, power down setting, PLL mux setting, and PLL R divider. It is required to program register R14. – R14 must be programmed in accordance with the register map as shown in the register map (see Table 1).
• Program R15 with PLL charge pump gain, and PLL N divider.

Table 1. LMK02000 REGISTER MAP

Table 1. LMK02000 REGISTER MAP (continued)

SNAS390D – NOVEMBER 2006– REVISED SEPTEMBER 2007 www.ti.com Product Folder Links: LMK02000 Submit Documentation Feedback Copyright © 2006–2007, Texas Instruments Incorporated

10.12.2 REGISTER R0 to R7

Registers R0 through R7 control the eight clock outputs. Register R0 controls CLKout0, Register R1 controls CLKout1, and so on. There is one additional bit in register R0 called RESET. Aside from this, the functions of these bits are identical. The X in CLKoutX_MUX, CLKoutX_DIV, CLKoutX_DLY, and CLKoutX_EN denote the actual clock output which may be from 0 to 7.

10.12.2.1 RESET Bit -- R0 only

This bit is only in register R0. The use of this bit is optional and it should be set to '0' if not used. Setting this bit to a '1' forces all registers to their power on reset condition and therefore automatically clears this bit. If this bit is set, all other R0 bits are ignored and R0 needs to be programmed again if used with its proper values and RESET = 0. Bit Name Default Bit Value Bit State Bit Description Register Bit Location RESET 0 No reset, normal operation Reset to power on defaults R0 31 CLKoutX_MUX 0 Bypassed CLKoutX mux mode R0 to R7 18:17 CLKoutX_EN 0 Disabled CLKoutX enable 16 CLKoutX_DIV 1 Divide by 2 CLKoutX clock divide 15:8 CLKoutX_DLY 0 0 ps CLKoutX clock delay 7:4 DIV4 0 PDF ≤ 20 MHz Phase Detector Frequency R11 15 EN_CLKout_Global 1 Normal - CLKouts normal Global clock output enable R14 POWERDOWN 0 Normal - Device active Device power down 26 PLL_CP_TRI 0 Normal - PLL active TRI-STATE PLL charge pump 25 PLL_CP_POL 0 Negative Polarity CP Polarity of charge pump 24 PLL_MUX 0 Disabled Multiplexer control for LD pin 23:20 PLL_R 10 R divider = 10 PLL R divide value 19:8 PLL_CP_GAIN 0 100 uA Charge pump current R15 31:30 PLL_N 760 N divider = 760 PLL N divide value 25:8

10.12.2.2 CLKoutX_MUX[1:0] -- Clock Output Multiplexers

These bits control the Clock Output Multiplexer for each clock output. Changing between the different modes changes the blocks in the signal path and therefore incurs a delay relative to the bypass mode. The different MUX modes and associated delays are listed below. CLKoutX_MUX[1:0] Mode Added Delay Relative to Bypass Mode

0 Bypassed (default) 0 ps

1 Divided 100 ps

2 Delayed 400 ps

(In addition to the programmed delay)

3 Divided and Delayed 500 ps

(In addition to the programmed delay)

10.12.2.3 CLKoutX_DIV[7:0] -- Clock Output Dividers

These bits control the clock output divider value. In order for these dividers to be active, the respective CLKoutX_MUX (See CLKoutX_MUX[1:0] -- Clock Output Multiplexers) bit must be set to either "Divided" or "Divided and Delayed" mode. After all the dividers are programed, the SYNC* pin must be used to ensure that all edges of the clock outputs are aligned (See GLOBAL CLOCK OUTPUT SYNCHRONIZATION). By adding the divider block to the output path a fixed delay of approximately 100 ps is incurred. The actual Clock Output Divide value is twice the binary value programmed as listed in the table below.

www.ti.com SNAS390D – NOVEMBER 2006– REVISED SEPTEMBER 2007 Product Folder Links: LMK02000 Submit Documentation FeedbackCopyright © 2006–2007, Texas Instruments Incorporated CLKoutX_DIV[7:0] Clock Output Divider value 0 0 0 0 0 0 0 0 Invalid 0 0 0 0 0 0 0 1 2 (default) 0 0 0 0 0 0 1 0 4 0 0 0 0 0 0 1 1 6 0 0 0 0 0 1 0 0 8 0 0 0 0 0 1 0 1 10 1 1 1 1 1 1 1 1 510

10.12.2.4 CLKoutX_DLY[3:0] -- Clock Output Delays

These bits control the delay stages for each clock output. In order for these delays to be active, the respective CLKoutX_MUX (See CLKoutX_MUX[1:0] -- Clock Output Multiplexers) bit must be set to either "Delayed" or "Divided and Delayed" mode. By adding the delay block to the output path a fixed delay of approximately 400 ps is incurred in addition to the delay shown in the table below. CLKoutX_DLY[3:0] Delay (ps) 0 0 (default) 1 150 2 300 3 450 4 600 5 750 6 900 7 1050 8 1200 9 1350 10 1500 11 1650 12 1800 13 1950 14 2100 15 2250

10.12.2.5 CLKoutX_EN bit -- Clock Output Enables

These bits control whether an individual clock output is enabled or not. If the EN_CLKout_Global bit (See EN_CLKout_Global Bit -- Global Clock Output Enable) is set to zero or if GOE pin is held low, all CLKoutX_EN bit states will be ignored and all clock outputs will be disabled. See CLKout OUTPUT STATES for more information on CLKout states. CLKoutX_EN bit Conditions CLKoutX State

0 EN_CLKout_Global bit = 1

GOE pin = High / No Connect 1 Disabled (default)

1 Enabled

10.12.3 REGISTER R11

This register only has one bit and only needs to be programmed in the case that the phase detector frequency is greater than 20 MHz and digital lock detect is used. Otherwise, it is automatically defaulted to the correct values.

10.12.3.1 DIV4

This bit divides the frequency presented to the digital lock detect circuitry by 4. It is necessary to get a reliable output from the digital lock detect output in the case of a phase detector frequency greater than 20 MHz.

SNAS390D – NOVEMBER 2006– REVISED SEPTEMBER 2007 www.ti.com Product Folder Links: LMK02000 Submit Documentation Feedback Copyright © 2006–2007, Texas Instruments Incorporated DIV4 Digital Lock Detect Circuitry Mode

0 Not divided; Phase detector frequency ≤ 20 MHz (default)

1 Divided by 4; Phase detector frequency > 20 MHz

10.12.4 REGISTER R14

The LMK02000 requires register R14 to be programmed as shown in the register map (see Table 1).

10.12.4.1 PLL_R[11:0] -- R Divider Value

These bits program the PLL R Divider and are programmed in binary fashion. PLL_R[11:0] PLL R Divide Value 0 0 0 0 0 0 0 0 0 0 0 0 Invalid 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 2 0 0 0 0 0 0 0 0 1 0 1 0 10 (default) 1 1 1 1 1 1 1 1 1 1 1 1 4095

10.12.4.2 PLL_MUX[3:0] -- Multiplexer Control for LD Pin

These bits set the output mode of the LD pin. The table below lists several different modes. PLL_MUX[3:0] Output Type LD Pin Function

0 Hi-Z Disabled (default)

1 Push-Pull Logic High

2 Push-Pull Logic Low

3 Push-Pull Digital Lock Detect (Active High)

4 Push-Pull Digital Lock Detect (Active Low)

5 Push-Pull Analog Lock Detect

6 Open Drain NMOS Analog Lock Detect

7 Open Drain PMOS Analog Lock Detect

8 Invalid

9 Push-Pull N Divider Output/2 (50% Duty Cycle)

10 Invalid

11 Push-Pull R Divider Output/2 (50% Duty Cycle)

10.12.4.3 POWERDOWN Bit -- Device Power Down

This bit can power down the device. Enabling this bit powers down the entire device and all blocks, regardless of the state of any of the other bits or pins. POWERDOWN bit Mode

0 Normal Operation (default)

1 Entire Device Powered Down

10.12.4.4 EN_CLKout_Global Bit -- Global Clock Output Enable

This bit overrides the individual CLKoutX_EN bits (See CLKoutX_EN bit -- Clock Output Enables). When this bit is set to 0, all clock outputs are disabled, regardless of the state of any of the other bits or pins. See CLKout OUTPUT STATES for more information on CLKout states.

www.ti.com SNAS390D – NOVEMBER 2006– REVISED SEPTEMBER 2007 Product Folder Links: LMK02000 Submit Documentation FeedbackCopyright © 2006–2007, Texas Instruments Incorporated EN_CLKout_Global bit Clock Outputs

0 All Off

1 Normal Operation (default)

10.12.4.5 PLL_CP_TRI Bit -- PLL Charge Pump TRI-STATE

This bit sets the PLL charge pump TRI-STATE. PLL_CP_TRI PLL Charge Pump

1 TRI-STATE

10.12.4.6 PLL_CP_POLBbit -- PLL Charge Pump Polarity

This bit sets the polarity of the charge pump to either negative or positive. A negative charge pump is used with a VCO or VCXO which decreases frequency with increasing tuning voltage. A positive charge pump is used with a VCO or VCXO which increases frequency with increasing tuning voltage. PLL_CP_POL PLL Charge Pump Polarity

0 Negative (default)

1 Positive

10.12.5 Register R15

10.12.5.1 PLL_N[17:0] -- PLL N Divider

These bits program the divide value for the PLL N Divider. The PLL N Divider precedes the PLL phase detector. The VCO or VCXO frequency is calculated as, fVCO = fOSCin × PLL N Divider / PLL R Divider. Since the PLL N divider is a pure binary counter, there are no illegal divide values for PLL_N[17:0] except for 0. PLL_N[17:0] PLL N Divider Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Invalid 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 0 1 1 1 1 1 0 0 0 760 (default) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 262143

10.12.5.2 PLL_CP_GAIN[1:0] -- PLL Charge Pump Gain

These bits set the charge pump gain of the PLL. PLL_CP_GAIN[1:0] Charge Pump Gain 0 1x (default) 1 4x 2 16x 3 32x

11.1 SYSTEM LEVEL DIAGRAM

reconditioned, and redistributed. Figure 2. Typical Application

11.2 BIAS PIN

important for low noise performance.

11.3 LDO BYPASS

11.4 CURRENT CONSUMPTION / POWER DISSIPATION CALCULATIONS

Table 2. Block Current Consumption

3.3 V (mA)

power dissipated in each emitter resistor is approximately (1.07 V)2 / 120 Ω = 9.5 mW.

11.5 THERMAL MANAGEMENT

estimate, TA (ambient temperature) plus device power consumption times θJA should not exceed 125 °C.

www.ti.com 11-Nov-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) LMK02000ISQ/NOPB Active Production WQFN (RHS) | 48 250 | SMALL T&R Yes SN Level-3-260C-168 HR -40 to 85 K02000 I LMK02000ISQ/NOPB.A Active Production WQFN (RHS) | 48 250 | SMALL T&R Yes SN Level-3-260C-168 HR -40 to 85 K02000 I (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 1-Aug-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 1-Aug-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMK02000ISQ/NOPB WQFN RHS 48 250 208.0 191.0 35.0 Pack Materials-Page 2

www.ti.com PACKAGE OUTLINE C SEE TERMINAL DETAIL 48X 0.30 0.18 5.1 0.1 48X 0.5 0.3 0.8 0.7 (A) TYP 0.05 0.00 44X 0.5 5.5 2X 5.5 A 7.15 6.85 B 7.15 6.85 0.30 0.18 0.5 0.3 (0.2) WQFN - 0.8 mm max heightRHS0048A PLASTIC QUAD FLATPACK - NO LEAD 4214990/B 04/2018 DIM A OPT 1 OPT 2 (0.1) (0.2) PIN 1 INDEX AREA 0.08 C SEATING PLANE 12 25 13 24 48 37 (OPTIONAL) PIN 1 ID 0.1 C A B 0.05 EXPOSED THERMAL PAD

49 SYMM

NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. SCALE 1.800 DETAIL OPTIONAL TERMINAL TYPICAL

www.ti.com EXAMPLE BOARD LAYOUT

0.07 MIN

0.07 MAX

48X (0.25) 48X (0.6) ( 0.2) TYP VIA 44X (0.5) (6.8) (6.8) (1.25) TYP ( 5.1) (R0.05) TYP (1.25) TYP (1.05) TYP (1.05) TYP WQFN - 0.8 mm max heightRHS0048A PLASTIC QUAD FLATPACK - NO LEAD 4214990/B 04/2018 SYMM 13 24 3748 SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:12X NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL METAL EDGE SOLDER MASK OPENING SOLDER MASK DETAILS NON SOLDER MASK DEFINED (PREFERRED) EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN 48X (0.6) 48X (0.25) 44X (0.5) (6.8) (6.8) 16X ( 1.05) (0.625) TYP (R0.05) TYP (1.25) TYP (1.25) TYP (0.625) TYP WQFN - 0.8 mm max heightRHS0048A PLASTIC QUAD FLATPACK - NO LEAD 4214990/B 04/2018 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SYMM METAL TYP SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 49 68% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:15X SYMM 13 24 3748

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