LMC7111

LMC7111 Tiny CMOS Operational Amplifier With Rail-to-Rail Input and Output datasheet (Rev. F)

Document overview

• Manufacturer or author: Texas Instruments, Incorporated [SNOS753,F]
• PDF pages: 27

Technical content

LMC7111 Tiny CMOS Operational Amplifier With Rail-to-Rail Input and Output

1 Features

• Tiny 5-pin SOT-23 package saves space
• Very wide common-mode input range
• Specified at 2.7V, 5V, and 10V
• Typical supply current 25μA at 5V
• 50kHz gain-bandwidth at 5V
• Similar to popular LMC6462
• Output to within 20mV of supply rail at 100kΩ load
• Good capacitive load drive

2 Applications

• Mobile communications
• Portable computing
• Current sensing for battery chargers
• Voltage reference buffering
• Sensor interface
• Stable bias for GaAs RF amps

3 Description

The LMC7111 is a micropower CMOS operational amplifier available in the space-saving SOT-23 package. This package makes the LMC7111 an excellent choice for space- and weight-critical designs. The wide common-mode input range enables the design of battery-monitoring circuits that sense signals greater than the V+ supply. The main benefits of the tiny package are most apparent in small, portable, electronic devices, such as mobile phones, pagers, and portable computers. The tiny amplifiers can be placed on a board where needed, simplifying board layout.

Package Information

PART NUMBER PACKAGE(1) PACKAGE SIZE(2) LM7111 DBV (SOT-23, 5) 2.9mm × 2.8mm (1) For more information, see Section 10. (2) The package size (length × width) is a nominal value and includes pins, where applicable. 1OUT 2V+ 3+IN 4 –IN 5 V Not to scale S u p p l y V o l t a g e ( V ) Supply Current (µA) 1 3 5 7 9 1 1 1 0 1 5 2 0 2 5 3 0 3 5 4 0 - 5 5 ° C - 4 0 ° C 0 ° C 2 5 ° C 8 5 ° C 1 2 5 ° C Supply Current vs Supply Voltage LMC7111 SNOS753F – AUGUST 1999 – REVISED JANUARY 2025 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

10 Mechanical, Packaging, and Orderable

4 Pin Configuration and Functions

3+IN 4 –IN 5 V Not to scale Figure 4-1. DBV Package, 5-Pin SOT-23 (Top View) Table 4-1. Pin Functions PIN TYPE DESCRIPTION NO. NAME

1 OUT Output Output

2 V+ Power Positive supply

3 +IN Input Noninverting input 4 −IN Input Inverting input

5 V− Power Negative supply

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5 Specifications

5.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT Differential input voltage ±Supply voltage V VS Supply voltage, VS = (V+) – (V–) 11 V Voltage at input/output pin (V–) – 0.3 (V+) + 0.3 V Current at input pin ±5 mA ISC Output short circuit(2) ±30 mA Supply pin current 30 mA Lead temperature (soldering, 10s) 260 °C Tstg Storage temperature –65 150 °C TJ Junction temperature(3) 150 °C (1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime. (2) Applies to both single-supply and split-supply operation. Continuous short operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature at 150°C. (3) The maximum power dissipation is a function of TJ(MAX), RθJA and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) – TA) / RθJA. All numbers apply for packages soldered directly into a printed circuit board (PCB).

5.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1000 V (1) JEDEC document JEP155 states that 500V HBM allows safe manufacturing with a standard ESD control process.

5.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VS Supply voltage, VS = (V+) – (V–) 2.5 11 V TJ Junction temperature –40 85 °C

5.4 Thermal Information

THERMAL METRIC(1) LMC7111 UNITDBV (SOT-23)

5 PINS

RθJA Junction-to-ambient thermal resistance 325 °C/W (1) For information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. www.ti.com LMC7111 SNOS753F – AUGUST 1999 – REVISED JANUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: LMC7111

5.5 Electrical Characteristics for VS = 2.7V or ±1.35V at TA = +25°C, V+ = 2.7V, V– = 0V, VCM = VO = V+ / 2, and RL > 1MΩ (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OFFSET VOLTAGE VOS Input offset voltage ±0.9 ±7 mV TJ = –40°C to +85°C ±9 dVOS/dT Input offset voltage drift ±10 µV/°C PSRR Power-supply rejection ratio Positive 55 60 dB TJ = –40°C to +85°C 50 Negative 55 60 TJ = –40°C to +85°C 50 INPUT BIAS CURRENT IB Input bias current (1) ±0.1 ±1 pA TJ = –40°C to +85°C ±20 IOS Input offset current (1) ±0.01 ±0.5 pA TJ = –40°C to +85°C ±10 INPUT VOLTAGE VCM Input common-mode voltage To positive rail CMRR ≥ 47dB 2.7 2.8 V TJ = –40°C to +85°C 2.25 To negative rail CMRR ≥ 41dB –0.10 0.0 TJ = –40°C to +85°C 0.40 To positive rail CMRR ≥ 47dB, V+ = 3V 3.0 3.2 TJ = –40°C to +85°C 2.8 To negative rail, CMRR > 47dB, V+ = 3V –0.25 0.0 To positive rail CMRR ≥ 47dB, V+ = 3.3V 3.4 3.5 TJ = –40°C to +85°C 3.2 To negative rail CMRR ≥ 47dB, V+ = 3.3V –0.25 –0.10 TJ = –40°C to +85°C 0.0 INPUT IMPEDANCE RIN Input resistance > 10 TΩ CIN Input capacitance Common mode 3 pF OPEN-LOOP GAIN AOL Open-loop voltage gain Sourcing 400 V/mV Sinking 150 FREQUENCY RESPONSE GBW Gain bandwidth product 40 kHz SR Slew rate 0.015 V/µs OUTPUT VO Voltage output swing Positive rail RL = 100kΩ 2.68 2.69 V TJ = –40°C to +85°C 2.40 Negative rail RL = 100kΩ 0.10 0.20 TJ = –40°C to +85°C 0.08 Positive rail RL = 10kΩ 2.60 2.65 TJ = –40°C to +85°C 2.40 Negative rail RL = 10kΩ 0.03 0.10 TJ = –40°C to +85°C 0.3 ISC Short-circuit current Sourcing (VO = 0V) and sinking (VO = 2.7V) 1 7 mA TJ = –40°C to +85°C 0.7 POWER SUPPLY IQ Quiescent current per amplifier 20 50 µA TJ = –40°C to +85°C 65 (1) Input bias current specified by design and processing. LMC7111 SNOS753F – AUGUST 1999 – REVISED JANUARY 2025 www.ti.com

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5.6 Electrical Characteristics for VS = 5V or ±2.5V at TA = +25°C, V+ = 5V, V– = 0V, VCM = VO = VS / 2, and RL > 1MΩ (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OFFSET VOLTAGE VOS Input offset voltage ±0.9 mV dVOS/dT Input offset voltage drift TJ = –40°C to +85°C 2 µV/°C PSRR Power-supply rejection ratio Positive, 5V < V+ < 10V, V– = 0V 60 85 dB Negative, –5V < V– < –10V, V+ = 0V 60 85 INPUT BIAS CURRENT IB Input bias current (1) ±0.1 ±1 pA TJ = –40°C to +85°C ±20 IOS Input offset current (1) ±.01 ±0.5 pA TJ = –40°C to +85°C ±10 NOISE INPUT VOLTAGE VCM Common-mode voltage range To positive rail CMRR ≥ 50dB 5.20 5.25 V TJ = –40°C to +85°C 5.0 To negative rail CMRR ≥ 50dB –0.3 –0.2 TJ = –40°C to +85°C 0.0 CMRR Common-mode rejection ratio 0V < VCM < 5V 60 85 dB INPUT IMPEDANCE RIN Input resistance >10 TΩ CIN Common mode input capacitance 3 pF OPEN-LOOP GAIN AOL Open-loop voltage gain Sourcing 500 V/mV Sinking 200 FREQUENCY RESPONSE GBW Gain bandwidth product 50 kHz SR Slew rate Voltage follower with 1V step input, RL = 100kΩ to 1.5V, f = 1kHz, VO = 1VPP 0.010 0.027 V/µs OUTPUT VO Voltage output swing RL = 100kΩ Positive rail 4.98 4.99 V Negative rail 0.01 0.02 RL = 10kΩ Positive rail 4.9 4.98 Negative rail 0.02 0.1 ISC Short-circuit current Sourcing VO = 0V 5 7 mA TJ = –40°C to +85°C 3.5 Sinking VO = 3V 5 7 TJ = –40°C to +85°C 3.5 POWER SUPPLY IQ Quiescent current per amplifier 25 µA (1) Input bias current specified by design and processing. www.ti.com LMC7111 SNOS753F – AUGUST 1999 – REVISED JANUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: LMC7111

5.7 Electrical Characteristics for VS = 10V or ±5V

at TA = +25°C, V+ = 10V, V- = 0V, VCM = VO = V+ / 2, and RL > 1MΩ (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OFFSET VOLTAGE VOS Input offset voltage ±0.9 ±7 mV TJ = –40°C to +85°C ±9 dVOS/dT Input offset voltage drift TJ = –40°C to +85°C 2 µV/°C PSRR Power supply rejection ratio Positive 5V < VS < 10V, V– = 0V, VO = 2.5V 80 dB Negative INPUT BIAS CURRENT IB Input bias current (1) ±0.1 ±1 pA TJ = –40°C to +85°C ±20 IOS Input offset current (1) ±0.01 ±0.5 pA TJ = –40°C to +85°C ±10 NOISE en Input voltage noise density f = 1kHz, VCM = 1V 110 nV/√Hz in Input current noise density f = 1kHz 0.03 pA/√Hz INPUT VOLTAGE VCM Common-mode voltage range To positive rail CMRR ≥ 50dB 10.15 10.2 V TJ = –40°C to +85°C 10.0 To negative rail CMRR ≥ 50dB –0.2 –0.15 TJ = –40°C to +85°C 0.0 INPUT IMPEDANCE RIN Input resistance >10 TΩ CIN Common mode input capacitance 3 pF OPEN-LOOP GAIN AOL Open-loop voltage gain RL = 100kΩ Sourcing 500 V/mV Sinking 200 FREQUENCY RESPONSE GBW Gain bandwidth product 50 kHz SR Slew rate Voltage follower with 1V step input, RL = 100kΩ to 5V, f = 1kHz, VO = 2VPP

0.03 V/µs

θm Phase margin 50 ° OUTPUT VO Voltage output swing RL = 100kΩ Positive rail, 9.98 9.99 V Negative rail 0.01 0.02 RL = 10kΩ Positive rail 9.90 9.98 Negative rail 0.02 0.1 ISC Short-circuit current Sourcing VO = 0V 25 20 mA TJ = –40°C to +85°C 7 Sinking VO = 10V 30 20 TJ = –40°C to +85°C 7 POWER SUPPLY IQ Quiescent current per amplifier 25 60 µA TJ = –40°C to +85°C 75 (1) Input bias current specified by design and processing. LMC7111 SNOS753F – AUGUST 1999 – REVISED JANUARY 2025 www.ti.com

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5.8 Typical Characteristics

at TA = 25°C (unless otherwise specified) S u p p l y V o l t a g e ( V ) Supply Current (µA) 1 3 5 7 9 1 1 1 0 1 5 2 0 2 5 3 0 3 5 4 0 - 5 5 ° C - 4 0 ° C 0 ° C 2 5 ° C 8 5 ° C 1 2 5 ° C Figure 5-1. Supply Current vs Supply Voltage Figure 5-2. Voltage Noise vs Frequency 5.9 Typical Characteristics: 2.7V at TA = 25°C (unless otherwise specified) C o m m o n - M o d e V o l t a g e ( V ) Input Offset Voltage (mV) - 6 - 4 - 2 Figure 5-3. Offset Voltage vs Common-Mode Voltage at 2.7V Figure 5-4. Sinking Output vs Output Voltage Figure 5-5. Sourcing Output vs Output Voltage Figure 5-6. Gain and Phase vs Capacitive Load at 2.7V www.ti.com LMC7111 SNOS753F – AUGUST 1999 – REVISED JANUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: LMC7111

5.9 Typical Characteristics: 2.7V (continued) at TA = 25°C (unless otherwise specified) Figure 5-7. Gain and Phase vs Capacitive Load at 2.7V Figure 5-8. Gain and Phase vs Capacitive Load at 2.7V

5.10 Typical Characteristics: 3V

at TA = 25°C (unless otherwise specified) Figure 5-9. Voltage Noise vs Common-Mode Voltage at 3V Figure 5-10. Output Voltage vs Input Voltage at 3V C o m m o n - M o d e V o l t a g e ( V ) Input Offset Voltage (mV) - 6 - 4 - 2 Figure 5-11. Offset Voltage vs Common-Mode Voltage at 3V Figure 5-12. Sourcing Output vs Output Voltage LMC7111 SNOS753F – AUGUST 1999 – REVISED JANUARY 2025 www.ti.com

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5.10 Typical Characteristics: 3V (continued)

at TA = 25°C (unless otherwise specified) Figure 5-13. Sinking Output vs Output Voltage Figure 5-14. Gain and Phase vs Capacitive Load at 3V Figure 5-15. Gain and Phase vs Capacitive Load at 3V Figure 5-16. Gain and Phase vs Capacitive Load at 3V

5.11 Typical Characteristics: 5V

at TA = 25°C (unless otherwise specified) Figure 5-17. Voltage Noise vs Common-Mode Voltage at 5V Figure 5-18. Output Voltage vs Input Voltage at 5V www.ti.com LMC7111 SNOS753F – AUGUST 1999 – REVISED JANUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: LMC7111

5.11 Typical Characteristics: 5V (continued)

at TA = 25°C (unless otherwise specified) C o m m o n - M o d e V o l t a g e ( V ) Input Offset Voltage (mV) - 6 - 4 - 2 Figure 5-19. Offset Voltage vs Common-Mode Voltage at 5V Figure 5-20. Sourcing Output vs Output Voltage Figure 5-21. Sinking Output vs Output Voltage Figure 5-22. Gain and Phase vs Capacitive Load at 5V Figure 5-23. Gain and Phase vs Capacitive Load at 5V Figure 5-24. Gain and Phase vs Capacitive Load at 5V LMC7111 SNOS753F – AUGUST 1999 – REVISED JANUARY 2025 www.ti.com

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at TA = 25°C (unless otherwise specified) Figure 5-25. Noninverting Small-Signal Pulse Response at 5V Figure 5-26. Noninverting Small-Signal Pulse Response at 5V Figure 5-27. Noninverting Small-Signal Pulse Response at 5V Figure 5-28. Noninverting Large-Signal Pulse Response at 5V Figure 5-29. Noninverting Large-Signal Pulse Response at 5V Figure 5-30. Noninverting Large-Signal Pulse Response at 5V www.ti.com LMC7111 SNOS753F – AUGUST 1999 – REVISED JANUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: LMC7111

at TA = 25°C (unless otherwise specified) Figure 5-31. Inverting Small-Signal Pulse Response at 5V Figure 5-32. Inverting Small-Signal Pulse Response at 5V Figure 5-33. Inverting Small-Signal Pulse Response at 5V Figure 5-34. Inverting Large-Signal Pulse Response at 5V Figure 5-35. Inverting Large-Signal Pulse Response at 5V Figure 5-36. Inverting Large-Signal Pulse Response at 5V LMC7111 SNOS753F – AUGUST 1999 – REVISED JANUARY 2025 www.ti.com

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5.12 Typical Characteristics: 10V

at TA = 25°C (unless otherwise specified) Figure 5-37. Voltage Noise vs Common-Mode Voltage at 10V Figure 5-38. Output Voltage vs Input Voltage at 10V C o m m o n - M o d e V o l t a g e ( V ) Input Offset Voltage (mV) - 5 - 2 . 5 0 2 . 5 5 - 6 - 4 - 2 Figure 5-39. Offset Voltage vs Common-Mode Voltage at 10V Figure 5-40. Sourcing Output vs Output Voltage Figure 5-41. Sinking Output vs Output Voltage Figure 5-42. Gain and Phase vs Capacitive Load at 10V www.ti.com LMC7111 SNOS753F – AUGUST 1999 – REVISED JANUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: LMC7111

5.12 Typical Characteristics: 10V (continued)

at TA = 25°C (unless otherwise specified) Figure 5-43. Gain and Phase vs Capacitive Load at 10V Figure 5-44. Gain and Phase vs Capacitive Load at 10V Figure 5-45. Noninverting Small-Signal Pulse Response at 10V Figure 5-46. Noninverting Large-Signal Pulse Response at 10V Figure 5-47. Inverting Small-Signal Pulse Response at 10V Figure 5-48. Inverting Large-Signal Pulse Response at 10V LMC7111 SNOS753F – AUGUST 1999 – REVISED JANUARY 2025 www.ti.com

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6 Detailed Description

6.1 Feature Description

6.1.1 Benefits of the LMC7111 Tiny Amp

6.1.1.1 Size

The small footprint of the SOT-23-5 packaged tiny amplifier, (0.12in × 0.118in, 3.05mm × 3mm) saves space on printed circuit boards, and enable the design of smaller electronic products. Many customers prefer smaller and lighter products because the designs can contribute to overall weight reduction in applications.

6.1.1.2 Height

The height (0.056 inches, 1.43mm) of the tiny amplifier makes the device an excellent choice for use in a wide range of circuit boards in which a thin profile is required.

6.1.1.3 Signal Integrity

Signals can pick up noise between the signal source and the amplifier. By using a physically smaller amplifier package, the Tiny amp can be placed closer to the signal source, reducing noise pickup and increasing signal integrity. The Tiny amp can also be placed next to the signal destination, such as a buffer for the reference of an analog to digital converter.

6.1.1.4 Simplified Board Layout

The tiny amplifier can simplify board layout in several ways. Avoid long PCB traces by correctly placing amplifiers instead of routing signals to a dual or quad device. By using multiple tiny amplifiers instead of duals or quads, complex signal routing and possibly crosstalk can be reduced.

6.1.1.5 Low Supply Current

The typical 25 μA supply current of the LMC7111 extends battery life in portable applications, and can allow for the reduction of battery size in some applications.

6.1.1.6 Wide Voltage Range

The LMC7111 is characterized at 2.7V, 3V, 3.3V, 5V and 10V. Performance data is provided at these popular voltages. This wide voltage range makes the LMC7111 a good choice for devices where the voltage can vary over the life of the batteries.

6.1.2 Input Common-Mode Voltage Range

The LMC7111 does not exhibit phase inversion when an input voltage exceeds the negative supply voltage. The absolute maximum input voltage is 300mV beyond either rail at room temperature. Voltages greatly exceeding this maximum rating can cause excessive current to flow in or out of the input pins, adversely affecting reliability. Applications that exceed this rating must externally limit the maximum input current to ±5mA with an input resistor as shown in Figure 6-1. Figure 6-1. RI Input Current Protection for Voltages Exceeding the Supply Voltage

6.1.3 Output Swing

The LMC71111 output goes to within 100mV of either power supply rail for a 10k Ω load, and to 20mV of the rail for a 100k Ω load. This feature makes the LMC7111 useful to drive transistors connected to the same power supply. By going very close to the supply, the LMC7111 can turn the transistors all the way on or off. www.ti.com LMC7111 SNOS753F – AUGUST 1999 – REVISED JANUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: LMC7111

7 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

7.1 Application Information

7.1.1 Capacitive Load Tolerance

The LMC7111 can typically directly drive a 300pF load with V S = 10V at unity gain without oscillating. The unity gain follower is the most sensitive configuration. Direct capacitive loading reduces the phase margin of op-amps. The combination of the op-amp output impedance and the capacitive load induces phase lag. This results in either an underdamped pulse response or oscillation. Capacitive load compensation can be accomplished using resistive isolation as shown in Figure 7-1. This simple technique is useful for isolating the capacitive input of multiplexers and A/D converters. Figure 7-1. Resistive Isolation of a 330pF Capacitive Load LMC7111 SNOS753F – AUGUST 1999 – REVISED JANUARY 2025 www.ti.com

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7.1.2 Compensating for Input Capacitance When Using Large-Value Feedback Resistors

When using very large value feedback resistors, (usually > 500k Ω) the large feed back resistance can react with the input capacitance due to transducers, photodiodes, and circuit board parasitics to reduce phase margins. The effect of input capacitance can be compensated for by adding a feedback capacitor. The feedback capacitor (as in Figure 7-2), Cf is first estimated by: (1) or R1 CIN ≤ R2 Cf (2) which typically provides significant overcompensation. Printed circuit board stray capacitance can be larger or smaller than that of a breadboard, so the actual optimum value for CFcan be different. Check C F values on the actual circuit. (Refer to the LMC660 quad CMOS amplifier data sheet for a more detailed discussion.) Figure 7-2. Canceling the Effect of Input Capacitance

7.1.3 Dual and Quad Devices With Similar Performance

The dual LMC6462 and quad LMC6464 devices achieve performance similar to the LMC7111. Both devices are available in both conventional through-hole and surface-mount packaging. See also the LMC646x data sheet for details. www.ti.com LMC7111 SNOS753F – AUGUST 1999 – REVISED JANUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: LMC7111

7.2 Typical Application

7.2.1 Biasing GaAs RF Amplifiers

The capacitive load capability, low current draw, and small size of the SOT-23 LMC7111 make this device a good choice for providing a stable negative bias to other integrated circuits. The very small size of the LMC7111 and the LM4040 reference take up very little board space. Note: CF and Risolation prevent oscillations when driving capacitive loads. Figure 7-3. Stable Negative Bias

7.2.2 Reference Buffer for Analog-to-Digital Converters

The LMC7111 can be used as a voltage reference buffer for an analog-to-digital converter (ADC). This configuration works best for ADCs with the reference input is a static load, such as dual slope integrating ADCs. Converters with a reference input that is a dynamic load (the reference current changes with time) can require a faster device, such as the LMC7101 or the LMC7131. The small size of the LMC7111 allows this device to be placed close to the reference input. The low supply current (25μA typical) saves power. For ADC reference inputs that require higher accuracy and lower offset voltage, see the LMC646x data sheet . The LMC6462 has performance similar to the LMC7111. The LMC6462 is available in two grades with reduced input voltage offset. LMC7111 SNOS753F – AUGUST 1999 – REVISED JANUARY 2025 www.ti.com

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8 Device and Documentation Support

8.1 Device Support

8.1.1 Spice Macromodel

A SPICE macromodel is available for the LMC7111. This model includes simulation of:

• Input common-mode voltage range
• Frequency and transient response
• Quiescent and dynamic supply current
• Output swing dependence on loading conditions and many more characteristics as listed on the macro model disk. Visit the LMC7111 product page on http://www.ti.com for the spice model.

8.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

8.3 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

8.4 Trademarks

TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.

8.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

8.6 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

9 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision E (March 2013) to Revision F (January 2025) Page www.ti.com LMC7111 SNOS753F – AUGUST 1999 – REVISED JANUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: LMC7111

Changes from Revision D (March 2013) to Revision E (March 2013) Page

10 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. LMC7111 SNOS753F – AUGUST 1999 – REVISED JANUARY 2025 www.ti.com

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www.ti.com 7-Oct-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) LMC7111BIM5/NOPB Obsolete Production SOT-23 (DBV) | 5 - - Call TI Call TI -40 to 85 A01B LMC7111BIM5X/NOPB Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 85 A01B LMC7111BIM5X/NOPB.A Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 85 A01B LMC7111BIM5X/NOPB.B Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 85 A01B (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 15-Jul-2026 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 15-Jul-2026 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMC7111BIM5X/NOPB SOT-23 DBV 5 3000 208.0 191.0 35.0 LMC7111BIM5X/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0 LMC7111BIM5X/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0 Pack Materials-Page 2

www.ti.com PACKAGE OUTLINE C 0.22

0.08 TYP

0.25 3.0 2.6 2X 0.95 1.9 1.45 0.90 0.15

0.00 TYP

5X 0.5 0.3 0.6

0.3 TYP

0 TYP

1.9 (0.1) (0.15) 4X 0 -15 4X 4 -15 A 3.05 2.75 B1.75 1.45 (1.1) SOT-23 - 1.45 mm max heightDBV0005A SMALL OUTLINE TRANSISTOR 4214839/K 08/2024 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-178. 4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.25 mm per side. 5. Support pin may differ or may not be present.

0.2 C A B

0.1 C SCALE 4.000

www.ti.com EXAMPLE BOARD LAYOUT

0.07 MAX

0.07 MIN

5X (1.1) 5X (0.6) (2.6) (1.9) 2X (0.95) (R0.05) TYP 4214839/K 08/2024 SOT-23 - 1.45 mm max heightDBV0005A SMALL OUTLINE TRANSISTOR NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X PKG 3 4 SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL METALSOLDER MASK OPENING NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DETAILS EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN (2.6) (1.9) 2X(0.95) 5X (1.1) 5X (0.6) (R0.05) TYP SOT-23 - 1.45 mm max heightDBV0005A SMALL OUTLINE TRANSISTOR 4214839/K 08/2024 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X SYMM PKG 3 4

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