LMC7101 Tiny, Low-Power Operational Amplifier With Rail-to-Rail Input and Output datasheet
Document overview
- Manufacturer or author: Texas Instruments, Incorporated [SBOSAL2,*]
- PDF pages: 36
Technical content
LMC7101 Tiny, Low-Power Operational Amplifier With Rail-to-Rail Input and Output
1 Features
- Tiny 5-Pin SOT-23 package saves space; typical circuit layouts take half the space of 8-pin SOIC designs
- Specified for 2.7V, 3V, 5V, and 15V supplies
- Typical supply current 0.5mA at 5V
- Typical total harmonic distortion of 0.01% at 5V
- 1MHz gain bandwidth
- Specified to industrial temperature: –40°C to +85°C
- Similar to popular LMC6482 and LMC6484
- Rail-to-rail input and output
2 Applications
- Mobile communications
- Notebooks and PDAs
- Battery-powered products
- Sensor interface
- Automotive applications
3 Description
The LMC7101 device is a high-performance, automotive, CMOS operational amplifier available in a space-saving, 5-pin, SOT-23 tiny package. This design makes the LMC7101 an excellent choice for space- and weight-critical designs. The performance is similar to the single amplifier of the LMC6482 and LMC6484, with rail-to-rail input and output, high open- loop gain, low distortion, and low-supply currents. The main benefits of the tiny package are most apparent in small, portable electronic devices, such as mobile phones, pagers, notebook computers, personal digital assistants, and PCMCIA cards. The tiny amplifiers can be placed on a board where needed, thus simplifying board layout.
Package Information
PART NUMBER PACKAGE(1) PACKAGE SIZE(2) LMC7101 DBV (SOT-23, 5) 2.9mm × 2.8mm (1) For more information, see Section 10. (2) The package size (length × width) is a nominal value and includes pins, where applicable. RES11A10 REF OUT LMC7101 IN− IN+ Difference Amplifier Application With RES11A LMC7101 SBOSAL2 – SEPTEMBER 1999 – REVISED JANUARY 2025 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.
10 Mechanical, Packaging, and Orderable
4 Pin Configuration and Functions
3+IN 4 –IN 5 V Not to scale Figure 4-1. DBV Package, 5-Pin SOT-23 (Top View) Table 4-1. Pin Functions PIN TYPE DESCRIPTION NO. NAME
1 OUT Output Output
2 V+ Power Positive supply
3 +IN Input Noninverting input 4 −IN Input Inverting input
5 V− Power Negative supply
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5 Specifications
5.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) (2) MIN MAX UNIT Difference Input voltage ±Supply voltage V Voltage at input and output pins (V–) – 0.3 (V+) + 0.3 V VS Supply voltage, VS = (V+) – (V–) 16 V Current at input pin –5 5 mA Current at output pin(3) –35 35 mA Current at power supply pin 35 mA Lead temperature (soldering, 10s) 260 °C TJ Junction temperature(4) 150 °C Tstg Storage temperature –65 150 °C (1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime. (2) If Military/Aerospace specified devices are required, contact the TI Sales Office or Distributors for availability and specifications. (3) Applies to both single-supply and split-supply operation. Continuous short operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature at 150°C (4) The maximum power dissipation is a function of TJ(MAX), RθJA and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) – TA) / RθJA. All numbers apply for packages soldered directly into a PC board.
5.2 ESD Ratings
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1000 V Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000 (1) JEDEC document JEP155 states that 500V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250V CDM allows safe manufacturing with a standard ESD control process.
5.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VS Supply voltage, VS = (V+) – (V–) 2.7 15.5 V TJ Junction temperature –40 85 °C
5.4 Thermal Information
THERMAL METRIC(1) LMC7101 UNITDBV (SOT)
5 PINS
RθJA Junction-to-ambient thermal resistance 193.5 °C/W RθJC(top) Junction-to-case(top) thermal resistance 128.5 °C/W RθJB Junction-to-board thermal resistance 88.9 °C/W ψJT Junction-to-top characterization parameter 66.8 °C/W ψJB Junction-to-board characterization parameter 88.6 °C/W RθJC(bot) Junction-to-case(bottom) thermal resistance N/A °C/W (1) For information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. www.ti.com LMC7101 SBOSAL2 – SEPTEMBER 1999 – REVISED JANUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: LMC7101
5.5 Electrical Characteristics for VS = ±1.35V or 2.7V at TJ = 25°C, V+ = 2.7V, V– = 0V, VCM = VOUT = V+ / 2, and RL > 1MΩ connected to V+ / 2 (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OFFSET VOLTAGE VOS Input offset voltage LMC7101A ±0.11 ±6 mV LMC7101B ±0.11 ±9 dVOS/dT Input offset voltage drift TJ = –40°C to +85°C 1 µV/°C PSRR Power-supply rejection ratio V+ = 1.35V to 1.65V, V– = –1.35V to –1.65V, VCM = 0V 45 60 dB INPUT BIAS CURRENT IB Input bias current TJ = –40°C to +85°C ±1 ±64 pA IOS Input offset current TJ = –40°C to +85°C ±0.5 ±32 pA INPUT VOLTAGE VCM Input common-mode voltage For CMRR ≥ 47dB Positive 2.7 3 V Negative 0 0 CMRR Common-mode rejection 0V ≤ VCM ≤ 2.7V 47 70 dB INPUT IMPEDANCE RIN Input resistance > 1 TΩ CIN Common-mode input capacitance 3 pF FREQUENCY RESPONSE GBW Gain bandwidth product 0.6 MHz SR Slew rate(1) (V+) = 15V, 10V step, RL = 100kΩ to 7.5V, VOUT = 10VPP, f = 1kHz 0.7 V/µs OUTPUT VO Voltage output swing Positive rail RL = 2kΩ 2.15 2.45 V RL = 10kΩ 2.64 2.68 Negative rail RL = 2kΩ 0.25 0.5 RL = 10kΩ 0.025 0.06 POWER SUPPLY IQ Quiescent current per amplifier 500 810 µA TJ = –40°C to +85°C 500 950 (1) Number specified is the slower of the positive and negative slew rates. LMC7101 SBOSAL2 – SEPTEMBER 1999 – REVISED JANUARY 2025 www.ti.com
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5.6 Electrical Characteristics for VS = ±1.5V or 3V at TJ = 25°C, V+ = 3V, V– = 0V, VCM = VOUT = V+ / 2, and RL = 1MΩ connected to V+ / 2 (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OFFSET VOLTAGE VOS Input offset voltage LMC7101A ±0.11 ±3 mV LMC7101B ±0.11 ±7 dVOS/dT Input offset voltage drift TJ = –40°C to +85°C 1 µV/°C PSRR Power-supply rejection ratio V+ = 1.5V to 7.5V V– = –1.5V to –7.5V VOUT = VCM = 0V LMC7101A 68 80 dB LMC7101B 60 80 INPUT BIAS CURRENT IB Input bias current TJ = –40°C to +85°C ±1 ±64 pA IOS Input offset current TJ = –40°C to +85°C ±0.5 ±32 pA INPUT VOLTAGE VCM Input common-mode voltage For CMRR ≥ 47dB Positive 3 3.3 V Negative 0 0 CMRR Common-mode rejection 0V ≤ VCM ≤ 3V 47 70 dB INPUT IMPEDANCE RIN Input resistance > 1 TΩ CIN Common-mode input capacitance 3 pF OUTPUT VO Voltage output swing Positive rail RL = 2kΩ 2.6 2.8 V RL = 600Ω 2.5 2.7 Negative rail RL = 2kΩ 0.2 0.4 RL = 600Ω 0.37 0.6 POWER SUPPLY IQ Quiescent current per amplifier 500 810 µA TJ = –40°C to +85°C 500 950 www.ti.com LMC7101 SBOSAL2 – SEPTEMBER 1999 – REVISED JANUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: LMC7101
5.7 Electrical Characteristics for VS = ±2.5V or 5V at TJ = 25°C, V+ = 5V, V– = 0V, VCM = VOUT = V+ / 2, and RL = 1MΩ connected to V+ / 2 (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OFFSET VOLTAGE VOS Input offset voltage LMC7101A ±0.11 ±3 mV LMC7101B ±0.11 ±7 dVOS/dT Input offset voltage drift TJ = –40°C to +85°C 1 µV/°C PSRR Power-supply rejection ratio Positive V+ = 5V to 15V V– = 0V, VOUT = 1.5V LMC7101A 70 82 dB LMC7101B 65 82 LMC7101A TJ = –40°C to +85°C 65 82 LMC7101B TJ = –40°C to +85°C 62 82 Negative V+ = –5V to –15V V– = 0V, VOUT = –1.5V LMC7101A 70 82 LMC7101B 65 82 LMC7101A TJ = –40°C to +85°C 65 82 LMC7101B TJ = –40°C to +85°C 62 82 INPUT BIAS CURRENT IB Input bias current pA TJ = –40°C to +85°C ±64 IOS Input offset current ±0.5 pA TJ = –40°C to +85°C ±32 NOISE THD Total harmonic distortion f = 10kHz, G = – 2V/V, RL = 10kΩ, VOUT = 4Vpp 0.01 % INPUT VOLTAGE VCM Input common-mode voltage To positive rail CMRR > 50dB 5.2 5.3 V TJ = –40°C to +85°C 5 5.3 To negative rail CMRR > 50dB –0.3 –0.2 CMRR Common-mode rejection ratio 0V ≤ VCM ≤ 5V 52 75 dB TJ = –40°C to +85°C 51 74 INPUT IMPEDANCE RIN Input resistance > 1 TΩ CIN Input capacitance 3 pF FREQUENCY RESPONSE GBW Gain bandwidth product 1 MHz SR Slew rate 1 V/µs LMC7101 SBOSAL2 – SEPTEMBER 1999 – REVISED JANUARY 2025 www.ti.com
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5.7 Electrical Characteristics for VS = ±2.5V or 5V (continued) at TJ = 25°C, V+ = 5V, V– = 0V, VCM = VOUT = V+ / 2, and RL = 1MΩ connected to V+ / 2 (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OUTPUT VO Voltage output swing Positive rail RL = 2kΩ 4.7 4.9 V Negative rail RL = 2kΩ 0.1 0.18 TJ = –40°C to +85°C 0.1 0.24 Positive rail RL = 600Ω 4.5 4.7 TJ = –40°C to +85°C 4.24 4.7 Negative rail RL = 600Ω 0.3 0.5 TJ = –40°C to +85°C 0.3 0.65 ISC Short-circuit current Sourcing VOUT = 0V 16 24 mA TJ = –40°C to +85°C 11 24 Sinking VOUT = 5V 11 19 TJ = –40°C to +85°C 7.5 19 POWER SUPPLY IQ Quiescent current per amplifier 0.5 0.85 mA TJ = –40°C to +85°C 0.5 1 www.ti.com LMC7101 SBOSAL2 – SEPTEMBER 1999 – REVISED JANUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: LMC7101
5.8 Electrical Characteristics for VS = ±7.5V or 15V at TJ = 25°C, V+ = 15V, V– = 0V, VCM = VOUT = V+ / 2, and RL = 1MΩ connected to V+ / 2 (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OFFSET VOLTAGE VOS Input offset voltage ±0.26 mV dVOS/dT Input offset voltage drift TJ = –40°C to +85°C 1 µV/°C PSRR Power-supply rejection ratio Positive V+ = 5V to 15V V– = 0V, VOUT = 1.5V LMC7101A 70 82 dB LMC7101B 65 82 LMC7101A TJ = –40°C to +85°C 65 82 LMC7101B TJ = –40°C to +85°C 60 82 Negative V+ = –5V to –15V V– = 0V, VOUT = –1.5V LMC7101A 70 82 LMC7101B 65 82 LMC7101A TJ = –40°C to +85°C 65 82 LMC7101B TJ = –40°C to +85°C 62 82 INPUT BIAS CURRENT IB Input bias current pA TJ = –40°C to +85°C ±64 IOS Input offset current ±0.5 pA TJ = –40°C to +85°C ±32 NOISE en Input voltage noise density f = 1kHz, VCM = 1V 37 nV/√Hz in Input current noise density f = 1kHz 6.8 fA/√Hz THD Total harmonic distortion f = 10kHz, G = – 2V/V, RL = 10kΩ, VOUT = 8.5Vpp 0.01 % INPUT VOLTAGE VCM Input common-mode voltage To positive rail CMRR > 50dB 15.2 15.3 V TJ = –40°C to +85°C 15 15.3 To negative rail CMRR > 50dB –0.3 –0.2 CMRR Common-mode rejection ratio 0V ≤ VCM ≤15V 62 82 dB TJ = –40°C to +85°C 60 82 INPUT IMPEDANCE RIN Input resistance > 1 TΩ CIN Input capacitance 3 pF OPEN-LOOP GAIN AOL Open-loop voltage gain Sourcing 7.5V < VO < 12.5V, VCM = 1.5V RL = 2kΩ to 7.5V 80 340 V/mV TJ = –40°C to +85°C 40 340 Sinking 2.5V < VO < 7.5V, VCM = 1.5V RL = 2kΩ to 7.5V 15 24 TJ = –40°C to +85°C 10 24 Sourcing, VCM = 1.5V, 7.5V < VO < 12.5V, RL = 600Ω 34 300 Sinking, VCM = 1.5V, 2.5V < VO < 7.5V, RL = 600Ω 6 15 LMC7101 SBOSAL2 – SEPTEMBER 1999 – REVISED JANUARY 2025 www.ti.com
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5.8 Electrical Characteristics for VS = ±7.5V or 15V (continued) at TJ = 25°C, V+ = 15V, V– = 0V, VCM = VOUT = V+ / 2, and RL = 1MΩ connected to V+ / 2 (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT FREQUENCY RESPONSE GBW Gain bandwidth product 1.1 MHz SR Slew rate(1) VS = 15V, 10V step, RL = 100kΩ to 7.5V VOUT = 10VPP, f = 1kHz 0.5 1.1 V/µs θm Phase margin 45 ° Gm Gain margin 10 dB OUTPUT VO Voltage output swing Positive rail RL = 2kΩ 14.4 14.7 V TJ = –40°C to +85°C 14.2 14.7 Negative rail RL = 2kΩ 0.16 0.32 TJ = –40°C to +85°C 0.16 0.45 Positive rail RL = 600Ω 13.4 14.1 TJ = –40°C to +85°C 13 14.1 Negative rail RL = 600Ω 0.5 1 ISC Short-circuit current(2) Sourcing VOUT = 0V 30 50 mA TJ = –40°C to +85°C 20 50 Sinking VOUT = 12V 30 50 TJ = –40°C to +85°C 20 50 POWER SUPPLY IQ Quiescent current per amplifier 0.8 1.5 mA TJ = –40°C to +85°C 0.8 1.71 (1) Number specified is the slower of the positive and negative slew rates. (2) Do not short circuit output to V+ when V+ is greater than 12V or reliability can be adversely affected. www.ti.com LMC7101 SBOSAL2 – SEPTEMBER 1999 – REVISED JANUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: LMC7101
5.9 Typical Characteristics for VS = 2.7V at V+ = 2.7V, V– = 0V, and TA = 25°C (unless otherwise specified) Figure 5-1. Open-Loop Frequency Response Figure 5-2. Input Voltage vs Output Voltage Figure 5-3. Gain and Phase vs Capacitance Load Figure 5-4. Gain and Phase vs Capacitance Load Figure 5-5. dVOS vs Supply Voltage Common-Mode Voltage (V) Input Offset Voltage (mV) 5 typical units Figure 5-6. Input Offset Voltage vs Common-Mode Voltage LMC7101 SBOSAL2 – SEPTEMBER 1999 – REVISED JANUARY 2025 www.ti.com
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5.10 Typical Characteristics for VS = 3V
at V+ = 3V, V– = 0V, and TA = 25°C (unless otherwise specified) Figure 5-9. Open-Loop Frequency Response Figure 5-10. Input Voltage vs Output Voltage Figure 5-11. Sourcing Current vs Output Voltage Figure 5-12. Sinking Current vs Output Voltage LMC7101 SBOSAL2 – SEPTEMBER 1999 – REVISED JANUARY 2025 www.ti.com
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5.11 Typical Characteristics for VS = 5V
at V+ = 5V, V– = 0V, and TA = 25°C (unless otherwise specified) Figure 5-13. Open-Loop Frequency Response Figure 5-14. Input Voltage vs Output Voltage Figure 5-15. Sourcing Current vs Output Voltage Figure 5-16. Sinking Current vs Output Voltage www.ti.com LMC7101 SBOSAL2 – SEPTEMBER 1999 – REVISED JANUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: LMC7101
5.12 Typical Characteristics for VS = 15V
at V+ = 15V, V– = 0V, and TA = 25°C (unless otherwise specified) Figure 5-17. Open-Loop Frequency Response Figure 5-18. Input Voltage vs Output Voltage Figure 5-19. Sourcing Current vs Output Voltage Figure 5-20. Sinking Current vs Output Voltage Common-Mode Voltage (V) Input Offset Voltage (mV) 5 typical units Figure 5-21. Input Offset Voltage vs Common-Mode Voltage Figure 5-22. CMRR vs Input Voltage LMC7101 SBOSAL2 – SEPTEMBER 1999 – REVISED JANUARY 2025 www.ti.com
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5.12 Typical Characteristics for VS = 15V (continued)
at V+ = 15V, V– = 0V, and TA = 25°C (unless otherwise specified) Figure 5-23. Supply Current vs Supply Voltage Figure 5-24. Input Current vs Temperature Common-Mode Voltage (V) Input Bias Current (pA) -0.75 -0.5 -0.25 0.25 0.5 0.75 IBN IBP IOS Figure 5-25. Input Bias Current vs Common-Mode Voltage Figure 5-26. Output Voltage Swing vs Supply Voltage Figure 5-27. Input Voltage Noise vs Frequency Figure 5-28. Positive PSRR vs Frequency www.ti.com LMC7101 SBOSAL2 – SEPTEMBER 1999 – REVISED JANUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: LMC7101
at V+ = 15V, V– = 0V, and TA = 25°C (unless otherwise specified) Figure 5-29. Negative PSRR vs Frequency Figure 5-30. CMRR vs Frequency Figure 5-31. Open-Loop Frequency Response at –40°C Figure 5-32. Open-Loop Frequency Response at 25°C Figure 5-33. Open-Loop Frequency Response at 85°C Figure 5-34. Gain and Phase vs Capacitive Load LMC7101 SBOSAL2 – SEPTEMBER 1999 – REVISED JANUARY 2025 www.ti.com
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at V+ = 15V, V– = 0V, and TA = 25°C (unless otherwise specified) Figure 5-35. Gain and Phase vs Capacitive Load Figure 5-36. Output Impedance vs Frequency Figure 5-37. Slew Rate vs Temperature Figure 5-38. Slew Rate vs Supply Voltage Figure 5-39. Inverting Small-Signal Pulse Response Figure 5-40. Inverting Small-Signal Pulse Response www.ti.com LMC7101 SBOSAL2 – SEPTEMBER 1999 – REVISED JANUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: LMC7101
at V+ = 15V, V– = 0V, and TA = 25°C (unless otherwise specified) Figure 5-41. Inverting Small-Signal Pulse Response Figure 5-42. Inverting Large-Signal Pulse Response Figure 5-43. Inverting Large-Signal Pulse Response Figure 5-44. Inverting Large-Signal Pulse Response Figure 5-45. Noninverting Small-Signal Pulse Response Figure 5-46. Noninverting Small-Signal Pulse Response LMC7101 SBOSAL2 – SEPTEMBER 1999 – REVISED JANUARY 2025 www.ti.com
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at V+ = 15V, V– = 0V, and TA = 25°C (unless otherwise specified) Figure 5-47. Noninverting Small-Signal Pulse Response Figure 5-48. Noninverting Large-Signal Pulse Response Figure 5-49. Noninverting Large-Signal Pulse Response Figure 5-50. Noninverting Large-Signal Pulse Response Figure 5-51. Stability vs Capacitive Load Figure 5-52. Stability vs Capacitive Load www.ti.com LMC7101 SBOSAL2 – SEPTEMBER 1999 – REVISED JANUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: LMC7101
at V+ = 15V, V– = 0V, and TA = 25°C (unless otherwise specified) Figure 5-53. Stability vs Capacitive Load Figure 5-54. Stability vs Capacitive Load Figure 5-55. Stability vs Capacitive Load Figure 5-56. Stability vs Capacitive Load LMC7101 SBOSAL2 – SEPTEMBER 1999 – REVISED JANUARY 2025 www.ti.com
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6 Detailed Description
6.1 Overview
The LMC7101 is a single-channel, low-power operational amplifier available in a space-saving SOT-23 package, offering rail-to-rail input and output operation across a wide range of power-supply configurations. The LMC7101 is also available in an automotive-grade variant, see LMC7101Q-Q1.
6.2 Functional Block Diagram
IN– IN+ OUT
6.3 Feature Description
6.3.1 Benefits of the LMC7101 Tiny Amplifier
6.3.1.1 Size
The small footprint of the SOT-23-5 packaged tiny amplifier, (0.12in × 0.118in, 3.05mm × 3mm) saves space on printed circuit boards, and enable the design of smaller electronic products. Many customers prefer smaller and lighter products because the designs can contribute to overall weight reduction in portable electronics.
6.3.1.2 Height
The 0.056 inches (1.43mm) height of the tiny LMC7101 amplifier makes the device an excellent choice for use in a wide range of circuit boards in which a thin profile is required.
6.3.1.3 Signal Integrity
Signals can pick up noise between the signal source and the amplifier. By using a physically smaller amplifier package, the tiny amplifier can be placed closer to the signal source, thus reducing noise pickup and increasing signal integrity. The tiny amplifier can also be placed next to the signal destination, such as a buffer, for the reference of an analog-to-digital converter.
6.3.1.4 Simplified Board Layout
The tiny LMC7101 amplifier can simplify board layout in several ways. Avoid long PCB traces by correctly placing amplifiers instead of routing signals to a dual or quad device. By using multiple tiny amplifiers instead of duals or quads, complex signal routing and possibly crosstalk can be reduced.
6.3.1.5 Low THD
The high open-loop gain of the LMC7101 amplifier helps to achieve very low audio distortion—typically 0.01% at 10kHz with a 10k Ω load at 5V supplies. This makes the tiny amplifier an excellent choice for audio and low-frequency signal-processing applications.
6.3.1.6 Low Supply Current
The typical 0.5mA supply current of the LMC7101 can help improve thermal performance on high density circuit boards, and can allow the reduction of the overall board size in some applications.
6.3.1.7 Wide Voltage Range
The LMC7101 is characterized at 15V, 5V and 3V. Performance data is provided at these popular voltages. This wide voltage range makes the LMC7101 a good choice for devices where the supply voltage can vary. www.ti.com LMC7101 SBOSAL2 – SEPTEMBER 1999 – REVISED JANUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: LMC7101
6.4 Device Functional Modes
6.4.1 Input Common Mode
6.4.1.1 Input Common-Mode Voltage Range
The LMC7101 does not exhibit phase inversion when an input voltage exceeds the negative supply voltage. Figure 6-1 shows an input voltage exceeding both supplies with no resulting phase inversion of the output. The absolute maximum input voltage is 300mV beyond either rail at room temperature. Voltages greatly exceeding this maximum rating, as in Figure 6-2 , can cause excessive current to flow in or out of the input pins, thus adversely affecting reliability. The input voltage signal exceeds the amplifier power supply voltage with no output phase inversion. Figure 6-1. Input Voltage The ±7.5V input signal greatly exceeds the 3V supply in Figure 6-3 causing no phase inversion due to RI. Figure 6-2. Input Signal Applications that exceed this rating must externally limit the maximum input current to ±5mA with an input resistor as shown in Figure 6-3. LMC7101VIN VOUT Ri = 10kΩ Figure 6-3. RI Input Current Protection for Voltages Exceeding the Supply Voltage LMC7101 SBOSAL2 – SEPTEMBER 1999 – REVISED JANUARY 2025 www.ti.com
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7 Application and Implementation
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.
7.1 Application Information
7.1.1 Rail-to-Rail Output
The approximate output resistance of the LMC7101 is 180 Ω sourcing and 130 Ω sinking at V S = 3V and 110 Ω sourcing and 80Ω sinking at VS = 5V. Using the calculated output resistance, maximum output voltage swing can be estimated as a function of load.
7.1.2 Capacitive Load Tolerance
The LMC7101 can typically directly drive a 100pF load with V S = 15V at unity gain without oscillating. The unity gain follower is the most sensitive configuration. Direct capacitive loading reduces the phase margin of operational amplifiers. The combination of the output impedance and the capacitive load of the operational amplifier induces phase lag, which results in either an underdamped pulse response or oscillation. Capacitive load compensation can be accomplished using resistive isolation as shown in Figure 7-1. This simple technique is useful for isolating the capacitive input of multiplexers and A/D converters. LMC7101VIN VOUT 300 330pF Figure 7-1. Resistive Isolation of a 330pF Capacitive Load www.ti.com LMC7101 SBOSAL2 – SEPTEMBER 1999 – REVISED JANUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: LMC7101
7.1.3 Compensating for Input Capacitance When Using Large Value Feedback Resistors
When using very large value feedback resistors, (usually >500 k Ω) the large feed back resistance can react with the input capacitance due to transducers, photo diodes, and circuit board parasitics to reduce phase margins. The effect of input capacitance can be compensated for by adding a feedback capacitor. The feedback capacitor (as in Figure 7-2 ), C f is first estimated by Equation 1 and Equation 2 , which typically provides significant overcompensation. 2πR 1 C IN ≥ 1 2πR 2 C f (1) 2πR 1 C IN ≤ 2πR 2 C f (2) Printed circuit board stray capacitance can be larger or smaller than that of a breadboard, so the actual optimum value for CF can be different. The values of CF must be checked on the actual circuit. LMC7101 VIN VOUT Cf CIN R2R1 Figure 7-2. Canceling the Effect of Input Capacitance
7.2 Typical Application
Figure 7-3 shows a high input impedance noninverting circuit. This circuit gives a closed-loop gain equal to the ratio of the sum of R1 and R2 to R1 and a closed-loop 3dB bandwidth equal to the amplifier unity-gain frequency divided by the closed-loop gain. This design has the benefit of a very high input impedance, which is equal to the differential input impedance multiplied by loop gain (open loop gain / closed loop gain). In dc-coupled applications, input impedance is not as important as input current and the voltage drop across the source resistance. The amplifier output can go into saturation if the input is allowed to float, which can be important if the amplifier must be switched from source to source. LMC7101VIN VOUT R1 V+ Figure 7-3. Example Application LMC7101 SBOSAL2 – SEPTEMBER 1999 – REVISED JANUARY 2025 www.ti.com
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7.2.1 Design Requirements
For this example application, the supply voltage is 5V, and 100 × ±5% of noninverting gain is necessary. The signal input impedance is approximately 10kΩ.
7.2.2 Detailed Design Procedure
Use the equation for a noninverting amplifier configuration; G = 1 + R2 / R1, set R1 to 10k Ω, and R2 to 99 × R1, which is 990k Ω. Replacing the 990k Ω resistor with a more readily available 1M Ω resistor results in a gain of 101, which is within the desired gain tolerance. The gain-frequency characteristic of the amplifier and the feedback network must be such that oscillation does not occur. To meet this condition, the phase shift through amplifier and feedback network must never exceed 180° for any frequency where the gain of the amplifier and the feedback network is greater than unity. In practical applications, the phase shift must not approach 180° because this is the situation of conditional stability. The most critical case occurs when the attenuation of the feedback network is zero.
7.2.3 Application Curve
Gain = 1 + R /R2 1 = 101 (as shown) V (mV)IN V (V) O Figure 7-4. Output Response www.ti.com LMC7101 SBOSAL2 – SEPTEMBER 1999 – REVISED JANUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: LMC7101
7.3 Power Supply Recommendations
For proper operation, the power supplies must be decoupled. For supply decoupling, TI recommends placing 10nF to 1µF capacitors as close as possible to the operational-amplifier power supply pins. For single supply configurations, place a capacitor between the V+ and V − supply pins. For dual supply configurations, place one capacitor between V+ and ground, and place a second capacitor between V − and ground. Bypass capacitors must have a low ESR of less than 0.1Ω.
7.4 Layout
7.4.1 Layout Guidelines
Care must be taken to minimize the loop area formed by the bypass capacitor connection between supply pins and ground. A ground plane underneath the device is recommended; any bypass components to ground must have a nearby via to the ground plane. The optimum bypass capacitor placement is closest to the corresponding supply pin. Use of thicker traces from the bypass capacitors to the corresponding supply pins can lower the power-supply inductance and provide a more stable power supply. The feedback components must be placed as close as possible to the device to minimize stray parasitics.
7.4.2 Layout Example
Figure 7-5. LMC7101 Example Layout LMC7101 SBOSAL2 – SEPTEMBER 1999 – REVISED JANUARY 2025 www.ti.com
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8 Device and Documentation Support
8.1 Documentation Support
8.1.1 Related Documentation
For related documentation, see the following:
- Texas Instruments, LMC66x CMOS Dual Operational Amplifiers data sheet
- Texas Instruments, RES11A Matched, Thin-Film Resistor Dividers With 1kΩ Inputs data sheet
8.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.
8.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.
8.4 Trademarks
TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.
8.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
8.6 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
9 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision SNOS719G (September 2015) to Revision * (January 2025) Page www.ti.com LMC7101 SBOSAL2 – SEPTEMBER 1999 – REVISED JANUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 27 Product Folder Links: LMC7101
- Changed CMRR MIN for TJ = –40°C to +85°C from 55dB to 51dB for LMC7101B and from 60dB to 51dB for
10 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. LMC7101 SBOSAL2 – SEPTEMBER 1999 – REVISED JANUARY 2025 www.ti.com
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www.ti.com 5-Mar-2026 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) LMC7101AIM5X/NOPB Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU | SN Level-1-260C-UNLIM -40 to 85 A00A LMC7101AIM5X/NOPB.A Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 A00A LMC7101AIM5X/NOPB.B Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 A00A LMC7101BIM5/NOPB Obsolete Production SOT-23 (DBV) | 5 - - Call TI Call TI -40 to 85 A00B LMC7101BIM5X/NOPB Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU | SN Level-1-260C-UNLIM -40 to 85 A00B LMC7101BIM5X/NOPB.A Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 A00B LMC7101BIM5X/NOPB.B Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 A00B (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1
www.ti.com 5-Mar-2026 Addendum-Page 2
PACKAGE MATERIALS INFORMATION www.ti.com 15-Jul-2026 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION www.ti.com 15-Jul-2026 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMC7101AIM5X/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0 LMC7101AIM5X/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0 LMC7101AIM5X/NOPB SOT-23 DBV 5 3000 208.0 191.0 35.0 LMC7101AIM5X/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0 LMC7101BIM5X/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0 LMC7101BIM5X/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0 LMC7101BIM5X/NOPB SOT-23 DBV 5 3000 208.0 191.0 35.0 LMC7101BIM5X/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0 Pack Materials-Page 2
www.ti.com PACKAGE OUTLINE C 0.22
0.08 TYP
0.25 3.0 2.6 2X 0.95 1.9 1.45 0.90 0.15
0.00 TYP
5X 0.5 0.3 0.6
0.3 TYP
0 TYP
1.9 (0.1) (0.15) 4X 0 -15 4X 4 -15 A 3.05 2.75 B1.75 1.45 (1.1) SOT-23 - 1.45 mm max heightDBV0005A SMALL OUTLINE TRANSISTOR 4214839/K 08/2024 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-178. 4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.25 mm per side. 5. Support pin may differ or may not be present.
0.2 C A B
0.1 C SCALE 4.000
www.ti.com EXAMPLE BOARD LAYOUT
0.07 MAX
0.07 MIN
5X (1.1) 5X (0.6) (2.6) (1.9) 2X (0.95) (R0.05) TYP 4214839/K 08/2024 SOT-23 - 1.45 mm max heightDBV0005A SMALL OUTLINE TRANSISTOR NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X PKG 3 4 SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL METALSOLDER MASK OPENING NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DETAILS EXPOSED METAL
www.ti.com EXAMPLE STENCIL DESIGN (2.6) (1.9) 2X(0.95) 5X (1.1) 5X (0.6) (R0.05) TYP SOT-23 - 1.45 mm max heightDBV0005A SMALL OUTLINE TRANSISTOR 4214839/K 08/2024 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X SYMM PKG 3 4
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