LMC6022 Low Power CMOS Dual Operational Amplifier datasheet (Rev. D)

Document overview

  • Manufacturer or author: Texas Instruments, Incorporated [SNOS622,D]
  • PDF pages: 25

Technical content

www.ti.com SNOS622D –NOVEMBER 1994–REVISED MARCH 2013 LMC6022LowPowerCMOS DualOperationalAmplifier Check forSamples: LMC6022 1FEATURES DESCRIPTION The LMC6022 isa CMOS dualoperationalamplifier 2• Specifiedfor100 kΩ and 5 kΩ Loads whichcan operatefromeithera singlesupplyordual• High VoltageGain: 120 dB supplies.Itsperformancefeaturesincludean input

  • Low OffsetVoltageDrift:2.5μV/°C common-mode range thatreachesV−,low inputbias current,and voltagegain(into100k and 5 kΩ loads)• UltraLow InputBias Current: 40 fA thatisequaltoorbetterthanwidelyacceptedbipolar• InputCommon-Mode Range IncludesV− equivalents,whilethe power supplyrequirementis
  • OperatingRange from +5V to+15V Supply lessthan0.5mW.
  • Low Distortion:0.01% at1 kHz This chip is builtwithNational'sadvanced Double-
  • Slew Rate: 0.11V/μs PolySilicon-GateCMOS process.
  • Micropower Operation: 0.5mW See the LMC6024 datasheetfor a CMOS quad operationalamplifierwiththesesame features.

APPLICATIONS

  • High-Impedance Bufferor Preamplifier
  • Current-to-VoltageConverter
  • Long-Term Integrator
  • Sample-and-Hold Circuit
  • Peak Detector
  • MedicalInstrumentation
  • IndustrialControls Connection Diagram Figure1.8-PinSOIC Figure2.LMC6022 CircuitTopology Top View (Each Amplifier) Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2Alltrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 1994–2013,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

SNOS622D –NOVEMBER 1994–REVISED MARCH 2013 www.ti.com These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates. ABSOLUTE MAXIMUM RATINGS (1) DifferentialInputVoltage ±SupplyVoltage SupplyVoltage(V+ − V−) 16V Lead Temperature(Soldering,10 sec.) 260°C StorageTemperatureRange −65°C to+150°C JunctionTemperature 150°C ESD Tolerance(2) 1000V VoltageatOutput/InputPin (V+)+0.3V,(V−)−0.3V CurrentatOutputPin ±18 mA CurrentatPower SupplyPin 35 mA Power Dissipation See (3) CurrentatInputPin ±5 mA OutputShortCircuittoV− See (4) OutputShortCircuittoV+ See (5) (1) AbsoluteMaximum Ratingsindicatelimitsbeyond whichdamage tocomponent may occur.OperatingRatingsindicateconditionsfor whichthedeviceisintendedtobe functional,butdo notguaranteespecificperformancelimits.Forguaranteedspecificationsand test conditions,see theElectricalCharacteristics.The guaranteedspecificationsapplyonlyforthetestconditionslisted. (2) Human body model,100 pF dischargedthrougha 1.5kΩ resistor. (3) The maximum power dissipationisa functionofTJ(max),θJA and TA.The maximum allowablepower dissipationatany ambient temperatureisPD = (TJ(max)− TA)/θJA. (4) Appliestobothsingle-supplyand split-supplyoperation.Continuousshortcircuitoperationatelevatedambienttemperatureand/or multipleOp Amp shortscan resultinexceedingthemaximum allowedjunctiontemperatureof150°C. Outputcurrentsinexcessof±30 mA overlongtermmay adverselyaffectreliability. (5) Do notconnectoutputtoV+ when V+ isgreaterthan13V orreliabilitymay be adverselyaffected. OPERATING RATINGS TemperatureRange −40°C ≤ TJ ≤ +85°C SupplyVoltageRange 4.75Vto15.5V Power Dissipation See (1) ThermalResistance(θJA)(2) 8-PinSOIC 165°C/W (1) Foroperatingatelevatedtemperaturesthedevicemust be deratedbased on thethermalresistanceθJA withPD = (TJ−TA)/θJA. (2) Allnumbers applyforpackagessoldereddirectlyintoa PC board. DC ELECTRICAL CHARACTERISTICS The followingspecificationsapplyforV+ = 5V,V− = 0V,VCM = 1.5V,VO = 2.5V,and R L = 1M unlessotherwisenoted. Boldfacelimitsapplyatthetemperatureextremes;allotherlimitsTJ = 25°C. LMC6022I Symbol Parameter Conditions Typical(1) Units Limit(2) VOS InputOffsetVoltage 1 9 mV 11 max ΔVOS /ΔT InputOffsetVoltage 2.5 μV/°CAverageDrift IB InputBiasCurrent 0.04 pA 200 max IOS InputOffsetCurrent 0.01 pA 100 max R IN InputResistance >1 TeraΩ (1) Typicalvaluesrepresentthemost likelyparametricnorm. (2) Alllimitsareguaranteedby testingorcorrelation.

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www.ti.com SNOS622D –NOVEMBER 1994–REVISED MARCH 2013 DC ELECTRICAL CHARACTERISTICS (continued) The followingspecificationsapplyforV+ = 5V,V− = 0V,VCM = 1.5V,VO = 2.5V,and R L = 1M unlessotherwisenoted. Boldfacelimitsapplyatthetemperatureextremes;allotherlimitsTJ = 25°C. LMC6022I Symbol Parameter Conditions Typical(1) Units Limit(2) CMRR Common Mode Rejection 0V ≤ VCM ≤ 12V 83 63 dB Ratio V+ = 15V 61 min +PSRR PositivePower Supply 5V ≤ V+ ≤ 15V 83 63 dB RejectionRatio 61 min −PSRR NegativePower Supply 0V ≤ V− ≤ −10V 94 74 dB RejectionRatio 73 min VCM InputCommon-Mode V+ = 5V & 15V −0.4 −0.1 V VoltageRange ForCMRR ≥ 50 dB 0 max V+ − 2.5 min AV LargeSignalVoltageGain R L = 100 kΩ(3) 1000 200 V/mV Sinking 100 minSourcing 500 90 V/mV 40 min R L = 5 kΩ(3) 1000 100 V/mV Sourcing 75 minSinking 250 50 V/mV 20 min VO OutputVoltageSwing V+ = 5V 4.987 4.40 V R L = 100 kΩ to2.5V 4.43 min 0.004 0.06 V 0.09 max V+ = 5V 4.940 4.20 V R L = 5 kΩ to2.5V 4.00 min 0.040 0.25 V 0.35 max V+ = 15V 14.970 14.00 V R L = 100 kΩ to7.5V 13.90 min 0.007 0.06 V 0.09 max V+ = 15V 14.840 13.70 V R L = 5 kΩ to7.5V 13.50 min 0.110 0.32 V 0.40 max Copyright© 1994–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:LMC6022

SNOS622D –NOVEMBER 1994–REVISED MARCH 2013 www.ti.com DC ELECTRICAL CHARACTERISTICS (continued) The followingspecificationsapplyforV+ = 5V,V− = 0V,VCM = 1.5V,VO = 2.5V,and R L = 1M unlessotherwisenoted. Boldfacelimitsapplyatthetemperatureextremes;allotherlimitsTJ = 25°C. LMC6022I Symbol Parameter Conditions Typical(1) Units Limit(2) IO OutputCurrent V+ = 5V 22 13 mA Sourcing,VO = 0V 9 minSinking,VO = 5V (4) 21 13 mA 9 min V+ = 15V 40 23 mA Sourcing,VO = 0V 15 minSinking,VO = 13V (5) 39 23 mA 15 min IS SupplyCurrent BothAmplifiers 86 140 μA VO = 1.5V 165 max (4) Appliestobothsingle-supplyand split-supplyoperation.Continuousshortcircuitoperationatelevatedambienttemperatureand/or multipleOp Amp shortscan resultinexceedingthemaximum allowedjunctiontemperatureof150°C. Outputcurrentsinexcessof±30 mA overlongtermmay adverselyaffectreliability. (5) Do notconnectoutputtoV+ when V+ isgreaterthan13V orreliabilitymay be adverselyaffected. AC ELECTRICAL CHARACTERISTICS The followingspecificationsapplyforV+ = 5V,V− = 0V,VCM = 1.5V,VO = 2.5V,and R L = 1M unlessotherotherwisenoted. Boldfacelimitsapplyatthetemperatureextremes;allotherlimitsTJ = 25°C. LMC6022I Symbol Parameter Conditions Typical(1) Units Limit(2) SR Slew Rate See (3) 0.11 0.05 V/μs 0.03 min GBW Gain-BandwidthProduct 0.35 MHz φM Phase Margin 50 Deg G M Gain Margin 17 dB Amp-to-Amp Isolation See (4) 130 dB en Input-ReferredVoltageNoise F = 1 kHz 42 nV/√Hz in Input-ReferredCurrentNoise F = 1 kHz 0.0002 pA/√Hz (1) Typicalvaluesrepresentthemost likelyparametricnorm. (2) Alllimitsareguaranteedby testingorcorrelation. (3) V+ = 15V.Connectedas VoltageFollowerwith10V stepinput.Number specifiedistheslowerofthepositiveand negativeslewrates. (4) Inputreferred.V+ = 15V and R L = 100 kΩ connectedto7.5V.Each amp excitedinturnwith1 kHz toproduceVO = 13 VPP .

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www.ti.com SNOS622D –NOVEMBER 1994–REVISED MARCH 2013 TYPICAL PERFORMANCE CHARACTERISTICS VS = ±7.5V,TA = 25°C unlessotherwisespecified Supply Current InputBias Current vs.Supply Voltage vs.Temperature Figure3. Figure4. InputCommon-ModeVoltage Range vs.Temperature Output CharacteristicsCurrentSinking Figure5. Figure6. InputVoltageNoise Output CharacteristicsCurrentSourcing vs.Frequency Figure7. Figure8. Copyright© 1994–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:LMC6022

SNOS622D –NOVEMBER 1994–REVISED MARCH 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) VS = ±7.5V,TA = 25°C unlessotherwisespecified CrosstalkRejection CMRR vs.Frequency vs.Frequency Figure9. Figure10. CMRR Power Supply RejectionRatio vs.Temperature vs.Frequency Figure11. Figure12. Open-Loop VoltageGain vs.Temperature Open-Loop Frequency Response Figure13. Figure14.

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www.ti.com SNOS622D –NOVEMBER 1994–REVISED MARCH 2013 TYPICAL PERFORMANCE CHARACTERISTICS (continued) VS = ±7.5V,TA = 25°C unlessotherwisespecified Gain and Phase Responses Gain and Phase Responses vs.Load Capacitance vs.Temperature Figure15. Figure16. Gain Error(VOS Non-InvertingSlew Rate vs.VOUT ) vs.Temperature Figure17. Figure18. InvertingSlew Rate Large-SignalPulse Non-InvertingResponse vs.Temperature (AV = +1) Figure19. Figure20. Copyright© 1994–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:LMC6022

SNOS622D –NOVEMBER 1994–REVISED MARCH 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) VS = ±7.5V,TA = 25°C unlessotherwisespecified Non-InvertingSmall SignalPulse Response (AV = +1) InvertingLarge-SignalPulse Response Figure21. Figure22. Stability InvertingSmall-SignalPulse Response vs.CapacitiveLoad Note:Avoidresistiveloadsoflessthan500Ω,as theymay cause instability. Figure23. Figure24. Stability vs.CapacitiveLoad Figure25.

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www.ti.com SNOS622D –NOVEMBER 1994–REVISED MARCH 2013 APPLICATION HINTS AMPLIFIER TOPOLOGY The topologychosen forthe LMC6022 isunconventional(compared to general-purposeop amps) inthatthe traditionalunity-gainbufferoutputstageisnotused;instead,theoutputistakendirectlyfrom theoutputofthe integrator,to allowrail-to-railoutputswing.Since the buffertraditionallydeliversthe power to the load,while maintaininghighop amp gainand stability,and must withstandshortstoeitherrail,thesetasksnow falltothe integrator. As a resultofthesedemands, theintegratorisa compound affairwithan embedded gainstagethatisdoublyfed forward(viaC f and C ff) by a dedicatedunity-gaincompensationdriver.In addition,the outputportionof the integratorisa push-pullconfigurationfordeliveringheavy loads.Whilesinkingcurrentthewhole amplifierpath consistsof threegainstageswithone stagefed forward,whereas whilesourcingthe path containsfourgain stageswithtwo fedforward. Figure26. LMC6022 CircuitTopology (Each Amplifier) The largesignalvoltagegainwhilesourcingiscomparabletotraditionalbipolarop amps forloadresistanceofat least5 kΩ. The gain whilesinkingishigherthan most CMOS op amps, due to the additionalgain stage; however,when drivingloadresistanceof 5 kΩ or less,the gainwillbe reduced as indicatedinthe Electrical Characteristics.The op amp can driveloadresistanceas lowas 500Ω withoutinstability. COMPENSATING INPUT CAPACITANCE RefertotheLMC660 orLMC662 datasheetstodeterminewhetherornota feedbackcapacitorwillbe necessary forcompensationand what thevalueofthatcapacitorwouldbe. CAPACITIVE LOAD TOLERANCE Likemany otherop amps, theLMC6022 may oscillatewhen itsappliedloadappearscapacitive.The thresholdof oscillationvariesboth withloadand circuitgain.The configurationmost sensitiveto oscillationisa unity-gain follower.See theTYPICAL PERFORMANCE CHARACTERISTICS . The load capacitanceinteractswiththe op amp's outputresistanceto createan additionalpole.Ifthispole frequencyissufficientlylow,itwilldegradetheop amp's phase marginso thattheamplifierisno longerstableat low gains.The additionofa smallresistor(50Ω to100Ω)inserieswiththeop amp's output,and a capacitor(5 pF to10 pF) frominvertinginputtooutputpins,returnsthephase margintoa safevaluewithoutinterferingwith lower-frequencycircuitoperation.Thus, largervaluesof capacitancecan be toleratedwithoutoscillation.Note thatinallcases,theoutputwillringheavilywhen theloadcapacitanceisnearthethresholdforoscillation. Figure27. Rx, Cx Improve CapacitiveLoad Tolerance Copyright© 1994–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:LMC6022

SNOS622D –NOVEMBER 1994–REVISED MARCH 2013 www.ti.com Capacitiveloaddrivingcapabilityisenhanced by usinga pullup resistortoV+ (Figure28).Typicallya pullup resistorconducting50 μA or more willsignificantlyimprovecapacitiveloadresponses.The valueofthepullup resistormust be determinedbased on thecurrentsinkingcapabilityoftheamplifierwithrespecttothedesired outputswing.Open loop gain of the amplifiercan also be affectedby the pullup resistor(see Electrical Characteristics). Figure28. Compensating forLarge CapacitiveLoads witha PullUp Resistor PRINTED-CIRCUIT-BOARD LAYOUT FOR HIGH-IMPEDANCE WORK Itisgenerallyrecognizedthatany circuitwhichmust operatewithlessthan1000 pA ofleakagecurrentrequires speciallayoutof the PC board.When one wishes to take advantage of the ultra-lowbias currentof the LMC6022, typicallylessthan0.04pA, itisessentialtohave an excellentlayout.Fortunately,thetechniquesfor obtaininglow leakagesare quitesimple.First,theusermust notignorethesurfaceleakageofthePC board, even though itmay sometimes appear acceptablylow,because under conditionsof highhumidityor dustor contamination,thesurfaceleakagewillbe appreciable. To minimizetheeffectofany surfaceleakage,layouta ringoffoilcompletelysurroundingtheLMC6022's inputs and the terminalsof capacitors,diodes,conductors,resistors,relayterminals,etc.connectedto the op-amp's inputs.See Figure29.To have a significanteffect,guardringsshouldbe placedon boththetopand bottomof thePC board.ThisPC foilmust thenbe connectedtoa voltagewhich isatthesame voltageas theamplifier inputs,sinceno leakagecurrentcan flowbetween two pointsatthesame potential.For example,a PC board trace-to-padresistanceof 1012Ω, which isnormallyconsidereda verylargeresistance,couldleak5 pA ifthe tracewere a 5V bus adjacentto the pad of an input.This would cause a 100 timesdegradationfrom the LMC6022's actualperformance.However, ifa guard ringis held within5 mV of the inputs,then even a resistanceof1011Ω would cause only0.05pA ofleakagecurrent,or perhapsa minor(2:1)degradationofthe amplifier'sperformance.See Figure30a, Figure30b, Figure30c fortypicalconnectionsof guard ringsfor standardop-amp configurations.Ifbothinputsareactiveand athighimpedance,theguardcan be tiedtoground and stillprovidesome protection;see Figure30d. Figure29. Example ofGuard Ring inP.C.Board Layout (UsingtheLMC6024)

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www.ti.com SNOS622D –NOVEMBER 1994–REVISED MARCH 2013 (a)InvertingAmplifierGuard Ring Connections (b)Non-InvertingAmplifierGuard Ring Connections (c)FollowerGuard Ring Connections (d)Howland CurrentPump Guard Ring Connections Figure30. Guard Ring Connections The designershouldbe aware thatwhen itisinappropriateto layout a PC board forthe sake of justa few circuits,thereisanothertechniquewhich iseven betterthan a guard ringon a PC board:Don'tinsertthe amplifier'sinputpinintothe board at all,but bend itup inthe airand use onlyairas an insulator.Airisan excellentinsulator.Inthiscase you may have toforegosome oftheadvantagesofPC board construction,but theadvantagesaresometimeswellworththeeffortofusingpoint-to-pointup-in-the-airwiring.See Figure31. (InputpinsareliftedoutofPC boardand soldereddirectlytocomponents.AllotherpinsconnectedtoPC board.) Figure31. AirWiring BIAS CURRENT TESTING The testmethod of Figure32 is appropriateforbench-testingbias currentwith reasonableaccuracy.To understanditsoperation,firstcloseswitchS2 momentarily.When S2 isopened,then (1) Copyright© 1994–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:LMC6022

SNOS622D –NOVEMBER 1994–REVISED MARCH 2013 www.ti.com Figure32. Simple InputBias CurrentTestCircuit A suitablecapacitorforC2 would be a 5 pF or 10 pF silvermica, NPO ceramic,or air-dielectric.When determiningthemagnitudeofI−,theleakageofthecapacitorand socketmust be takenintoaccount.SwitchS2 shouldbe leftshortedmost ofthetime,orelsethedielectricabsorptionofthecapacitorC2 couldcause errors. Similarly,ifS1 isshortedmomentarily(whileleavingS2 shorted) (2) where C x isthestraycapacitanceatthe+ input. TypicalSingle-SupplyApplications (V+ = 5.0VDC ) Note:A 5V biason thephotodiodecan cutitscapacitanceby a factorof2 or3,leadingtoimprovedresponseand lowernoise.However,thisbiason thephotodiodewillcause photodiodeleakage(alsoknown as itsdarkcurrent). Figure33. Photodiode Current-to-VoltageConverter (Upperlimitofoutputrangedictatedby inputcommon-mode range; lowerlimitdictatedby minimum currentrequirementofLM385.) Figure34.Micropower CurrentSource Figure35.Low-Leakage Sample-and-Hold

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www.ti.com SNOS622D –NOVEMBER 1994–REVISED MARCH 2013 (V+ = 5.0VDC ) IfR1 = R5, R3 = R6, and R4 = R7; Then ∴AV ≈ 100 forcircuitshown Forgood CMRR overtemperature,lowdriftresistorsshouldbe used.MatchingofR3 toR6 and R4 toR7 affects CMRR. Gain may be adjustedthroughR2. CMRR may be adjustedthroughR7. Figure36. InstrumentationAmplifier Oscillatorfrequencyisdeterminedby R1, R2, C1, and C2: fOSC = 1/2πRC where R = R1 = R2 and C = C1 = C2. Thiscircuit,as shown,oscillatesat2.0kHz witha peak-to-peakoutputswingof4.5V. Figure37. Sine-Wave Oscillator Copyright© 1994–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:LMC6022

SNOS622D –NOVEMBER 1994–REVISED MARCH 2013 www.ti.com (V+ = 5.0VDC ) Figure38.1 Hz Square-Wave Oscillator Figure39.Power Amplifier fc = 10 Hz d = 0.895fO = 10 Hz Gain = 1Q = 2.1 Gain = −8.8 Figure40.10 Hz Bandpass Filter Figure41.10 Hz High-Pass Filter(2dB Dip) Figure42. 1 Hz Low-Pass Filter(MaximallyFlat,Dual Supply Only)

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www.ti.com SNOS622D –NOVEMBER 1994–REVISED MARCH 2013 (V+ = 5.0VDC ) Gain = −46.8 Outputoffsetvoltagereducedtotheleveloftheinputoffsetvoltageofthebottomamplifier(typically1 mV), referred toVBIAS. Figure43. High Gain AmplifierwithOffsetVoltageReduction Copyright© 1994–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:LMC6022

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REVISION HISTORY

Changes from RevisionC (March 2013)toRevisionD Page

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www.ti.com 11-Nov-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) LMC6022IM/NOPB Active Production SOIC (D) | 8 95 | TUBE Yes SN Level-1-260C-UNLIM -40 to 85 LMC60 22IM LMC6022IM/NOPB.A Active Production SOIC (D) | 8 95 | TUBE Yes SN Level-1-260C-UNLIM -40 to 85 LMC60 22IM LMC6022IM/NOPB.B Active Production SOIC (D) | 8 95 | TUBE Yes SN Level-1-260C-UNLIM -40 to 85 LMC60 22IM LMC6022IMX/NOPB Active Production SOIC (D) | 8 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 85 LMC60 22IM LMC6022IMX/NOPB.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 85 LMC60 22IM LMC6022IMX/NOPB.B Active Production SOIC (D) | 8 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 85 LMC60 22IM (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Addendum-Page 1

www.ti.com 11-Nov-2025 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 10-Aug-2026 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 10-Aug-2026 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMC6022IMX/NOPB SOIC D 8 2500 367.0 367.0 35.0 Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 10-Aug-2026 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) LMC6022IM/NOPB D SOIC 8 95 495 8 4064 3.05 LMC6022IM/NOPB.A D SOIC 8 95 495 8 4064 3.05 LMC6022IM/NOPB.B D SOIC 8 95 495 8 4064 3.05 Pack Materials-Page 3

www.ti.com PACKAGE OUTLINE C .228-.244 TYP [5.80-6.19] .069 MAX [1.75] 6X .050 [1.27] 8X .012-.020 [0.31-0.51] .150 [3.81] .005-.010 TYP [0.13-0.25] 0 - 8 .004-.010 [0.11-0.25] .010 [0.25].016-.050 [0.41-1.27] 4X (0 -15 ) A .189-.197 [4.81-5.00] NOTE 3 B .150-.157 [3.81-3.98] NOTE 4 4X (0 -15 ) (.041) [1.04] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. 1 8 .010 [0.25] C A B PIN 1 ID AREA SEATING PLANE .004 [0.1] C SEE DETAIL A DETAIL A TYPICAL SCALE 2.800

www.ti.com EXAMPLE BOARD LAYOUT .0028 MAX [0.07] ALL AROUND .0028 MIN [0.07] ALL AROUND (.213) [5.4] 6X (.050 ) [1.27] 8X (.061 ) [1.55] 8X (.024) [0.6] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METAL SOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS EXPOSED METAL OPENING SOLDER MASK METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SYMM 4 5 SEE DETAILS SYMM

www.ti.com EXAMPLE STENCIL DESIGN 8X (.061 ) [1.55] 8X (.024) [0.6] 6X (.050 ) [1.27] (.213) [5.4] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X SYMM SYMM 4 5

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