LMC555 CMOS Timer datasheet (Rev. N)

Document overview

  • Manufacturer or author: Texas Instruments, Incorporated [SNAS558,N]
  • PDF pages: 35

Technical content

1 Features

  • Fast astable frequency of 3MHz
  • Available in industry's smallest 8-bump DSBGA package (1.43mm × 1.41mm)
  • Less than 1mW typical power dissipation at 5V supply
  • 1.5V specified supply operating voltage
  • output fully compatible with TTL and CMOS logic at 5V supply
  • Tested to −10mA, 50mA output current levels
  • Reduced supply current spikes during output transitions
  • Extremely low reset, trigger, and threshold currents
  • Excellent temperature stability
  • Pin-for-pin compatible with 555 series of timers

2 Applications

  • Precision timing
  • Pulse generation
  • Sequential timing
  • Time delay generation
  • Pulse width modulation
  • Pulse position modulation
  • Linear ramp generators

3 Description

The LMC555 device is a CMOS version of the industry standard 555 series general-purpose timers. In addition to the standard SOIC, VSSSOP, and PDIP packages, the LMC555 is also available in a chip- sized, 8-bump DSBGA package using TI's DSBGA package technology. The LMC555 offers the same capability of generating accurate time delays and frequencies as the LM555, but with much lower power dissipation and supply current spikes. When operated as a one-shot, the time delay is precisely controlled by a single external resistor and capacitor. In astable mode, the oscillation frequency and duty cycle are accurately set by two external resistors and one capacitor. TI's LMCMOS process extends both the frequency range and the low supply capability.

Package Information

PART NUMBER PACKAGE(1) PACKAGE SIZE(2) LMC555 D (SOIC, 8) 4.9mm × 6mm DGK (VSSOP, 8) 3mm × 4.9mm P (PDIP, 8) 9.81mm × 9.43mm YBF (DSBGA, 8) 1.75mm × 1.75mm (1) For more information, see Section 11. (2) The package size (length × width) is a nominal value and includes pins, where applicable. Pulse Width Modulator Pulse Width Modulator Waveform: Top Waveform—Modulation Bottom Waveform—Output Voltage LMC555 SNAS558N – JANUARY 2000 – REVISED MARCH 2024 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

11 Mechanical, Packaging, and Orderable

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4 Pin Configuration and Functions

Figure 4-1. D Package, 8-Pin SOIC, and P Package, 8-Pin PDIP (Top View) Figure 4-2. YPB Package, 8-Pin DSBGA (Top View) Table 4-1. Pin Functions PIN TYPE DESCRIPTION NAME NO. D (SOIC), DGK (VSSOP), P (PDIP) YPB (DSBGA) CONTROL VOLTAGE 5 C1 Input Control voltage controls the threshold and trigger levels. This pin determines the pulse duration of the output waveform. An external voltage applied to this pin can also be used to modulate the output waveform. DISCHARGE 7 A1 Input Open collector output that discharges a capacitor between intervals (in phase with output). This pin toggles the output from high to low when voltage reaches 2/3 of the supply voltage (V+). GROUND 1 A3 Power Ground reference voltage OUTPUT 3 C3 Output Output driven waveform RESET 4 C2 Input Negative pulse applied to this pin to disable or reset the timer. When not used for reset purposes, connect this pin to V+ to avoid false triggering. THRESHOLD 6 B1 Input Compares the voltage applied to the pin with a reference voltage of 2/3 V+. The amplitude of voltage applied to this pin is responsible for the set state of the flip-flop. TRIGGER 2 B3 Input Responsible for transition of the flip-flop from set to reset. The output of the timer depends on the amplitude of the external trigger pulse applied to this pin. V+ 8 A2 Power Supply voltage with respect to ground www.ti.com LMC555 SNAS558N – JANUARY 2000 – REVISED MARCH 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: LMC555

5 Specifications

5.1 Absolute Maximum Ratings

over operating free-air temperature range, unless otherwise noted.(1) (2) (3) MIN MAX UNIT Voltage Supply 15 VInput –0.3 (V+) + 0.3 Output 15 Current Output 100 mA Storage temperature, Tstg –65 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Section 5.3. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) See AN-1112 (SNVA009) for DSBGA considerations. (3) If military- or aerospace-specified devices are required, contact the TI Sales Office or Distributors for availability and specifications.

5.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1500 V (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

5.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT Temperature LMC555IM −40 125 LMC555CM, MM, N, TP −40 85 Maximum allowable power dissipation at 25°C PDIP-8 1126 mW SOIC-8 740 VSSOP-8 555 8-bump DSBGA 568

5.4 Thermal Information

THERMAL METRIC(1) LMC555 UNITD (SOIC) DGK (VSSOP) P (PDIP) YPB (DSBGA)

8 PINS 8 PINS 8 PINS 8 PINS

RθJA Junction-to-ambient thermal resistance 138.9 188.3 93.1 102.3 °C/W RθJC(top) Junction-to-case (top) thermal resistance 78.8 78.8 82.5 0.9 °C/W RθJB Junction-to-board thermal resistance 87.9 110.2 69.6 31.2 °C/W ψJT Junction-to-top characterization parameter 23.2 18.5 52.0 0.5 °C/W ψJB Junction-to-board characterization parameter 86.9 108.6 69.2 31.2 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A N/A N/A °C/W (1) For information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. LMC555 SNAS558N – JANUARY 2000 – REVISED MARCH 2024 www.ti.com

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5.5 Electrical Characteristics

Test Circuit, T = 25°C, all switches open, RESET to VS unless otherwise noted(1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IS Supply current VS = 1.5 V 130 200 µAVS = 5 V 180 250 VS = 12 V 220 400 VCTRL Control voltage VS = 1.5 V 0.8 1.0 1.2 VVS = 5 V 2.9 3.3 3.8 VS = 12 V 7.4 8.0 8.6 VDIS Discharge saturation voltage VS = 1.5 V, IDIS = 1 mA 75 150 mV VS = 5 V, IDIS = 10 mA 150 300 VOL Output voltage (low) VS = 1.5 V, IO = 1 mA 0.2 0.4 VVS = 5 V, IO = 8 mA 0.3 0.6 VS = 12 V, IO = 50 mA 1.0 2.0 VOH Output voltage (high) VS = 1.5 V, IO = −0.25 mA 1.0 1.25 VVS = 5 V, IO = −2 mA 4.4 4.7 VS = 12 V, IO = −10 mA 10.5 11.3 VTRIG Trigger voltage VS = 1.5 V 0.4 0.5 0.6 V VS = 12 V 3.7 4.0 4.3 ITRIG Trigger current VS = 5 V 10 pA VRES Reset voltage V VS = 12 V 0.4 0.75 1.1 IRES Reset current VS = 5 V, VRES = VS 10 pA VS = 5 V, VRES = 0 V 5.9 µA ITHRESH Threshold current VS = 5 V 10 pA IDIS Discharge leakage VS = 12 V 1.0 100 nA (1) All voltages are measured with respect to the ground pin, unless otherwise specified. (2) If the RESET pin is to be used at temperatures of −20°C and less, then ensure that VS is 2.0 V or greater.

5.6 Switching Characteristics

Test Circuit, T = 25°C, all switches open, RESET to VS unless otherwise noted.(1) Characteristic values are specified by design, characterization, or both. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT t Timing accuracy SW 2, 4 closed VS = 1.5 V 0.9 1.1 1.25 msVS = 5 V 1.0 1.1 1.20 VS = 12 V 1.0 1.1 1.25 Δt/ΔVS Timing shift with supply VS = 5 V ± 1 V 0.3 %/V Δt/ΔT Timing shift with temperature VS = 5 V 75 ppm/°C fA Astable frequency SW 1, 3 closed, VS = 12 V 4.0 4.8 5.6 kHz fMAX Maximum frequency Maximum frequency test circuit, VS = 5 V 3.0 MHz tR, tF Output rise and fall times Maximum frequency test circuit VS = 5 V, CL = 10 pF 15 ns tPD Trigger propagation delay VS = 5 V, measure delay from trigger to output 100 ns (1) All voltages are measured with respect to the ground pin, unless otherwise specified. www.ti.com LMC555 SNAS558N – JANUARY 2000 – REVISED MARCH 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: LMC555

6 Parameter Measurement Information

For device pinout, see Section 4. Figure 6-1. Test Circuit For device pinout, see Section 4. Figure 6-2. Maximum Frequency Test Circuit LMC555 SNAS558N – JANUARY 2000 – REVISED MARCH 2024 www.ti.com

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7 Detailed Description

7.1 Overview

The LMC555 is a CMOS version of the industry standard 555 series general-purpose timers. In addition to the standard SOIC, VSSSOP, and PDIP packages, the LMC555 is also available in a chip-sized package (8-bump DSBGA) using TI’s DSBGA package technology. The LMC555 offers the same capability of generating accurate time delays and frequencies as the LM555 but with much lower power dissipation and supply current spikes. When operated as a one-shot, the time delay is precisely controlled by a single external resistor and capacitor. In the astable mode, the oscillation frequency and duty cycle are accurately set by two external resistors and one capacitor. The use of TI’s LMCMOS process extends both the frequency range and the low supply capability. Figure 7-1. Simplified Schematic

7.2 Functional Block Diagram

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7.3 Feature Description

7.3.1 Low-Power Dissipation

The LMC555 offers the same capability of generating accurate time delays and frequencies as the LM555 but with much lower power dissipation. A power dissipation of less than 0.2 mW can be achieved with a 1.5-V operating supply voltage and less than 1 mW with a 5-V operating supply voltage. The use of TI’s LMCMOS process allows this low supply current and voltage capability. Reduced supply current spikes during output transitions and extremely low reset, trigger and threshold currents also provide low power dissipation advantages with the LMC555.

7.3.2 Various Packages and Compatibility

There are various packages available for use of the LMC555. In addition to the standard package (8-pin SOIC, VSSOP, and PDIP, the LMC555 is also available in a chip-sized package (8-bump DSBGA). The PDIP, SOIC, and VSSOP packages for the LMC555 are pin-for-pin compatible with the 555 series of timers (NE555/SE555/ LM555) allowing flexibility in design and unnecessary modifications to PCB schematics and layouts.

7.3.3 Operates in Both Astable and Monostable Mode

The LMC555 can operate in both astable and monostable mode depending on the application requirements.

  • Monostable mode: The LMC555 timer acts as a “one-shot” pulse generator. The pulse begins when the LMC555 timer receives a signal at the trigger input that falls below a 1/3 of the voltage supply. The width of the output pulse is determined by the time constant of an RC network. The output pulse ends when the voltage on the capacitor equals 2/3 of the supply voltage. The output pulse width can be extended or shortened depending on the application by adjusting the R and C values.
  • Astable (free-running) mode: The LMC555 timer can operate as an oscillator and puts out a continuous stream of rectangular pulses having a specified frequency. The frequency of the pulse stream depends on the values of RA, RB, and C. LMC555 SNAS558N – JANUARY 2000 – REVISED MARCH 2024 www.ti.com

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7.4 Device Functional Modes

7.4.1 Monostable Operation

In this mode of operation, the timer functions as a one-shot ( Figure 7-2). The external capacitor is initially held discharged by internal circuitry. Upon application of a negative trigger pulse of less than 1/3 V S to the TRIGGER pin, the flip-flop is set, which both releases the short circuit across the capacitor and drives the output high. Figure 7-2. Monostable (One-Shot) The voltage across the capacitor then increases exponentially for a period of t H = 1.1 R AC. This period is also the time that the output stays high, at the end of which time the voltage equals 2/3 V S. The comparator then resets the flip-flop, which in turn discharges the capacitor and drives the output to the low state. Figure 7-3 shows the waveforms generated in this mode of operation. Because the charge and the threshold level of the comparator are both directly proportional to supply voltage, the timing internal is independent of supply. VS = 5 V Top trace: Input 5 V/div RA = 9.1 kΩ TIME = 0.1 ms/div Middle trace: Output 5 V/div C = 0.01 µF Bottom trace: Capacitor voltage 2 V/div Figure 7-3. Monostable Waveforms RESET overrides TRIGGER, which can override THRESHOLD. Therefore, ensure that the trigger pulse is shorter than the desired t H. The minimum pulse duration for TRIGGER is 20 ns, and is 400 ns for RESET. During the timing cycle when the output is high, the further application of a trigger pulse does not effect the circuit as long as the trigger input is returned high at least 10 µs before the end of the timing interval. However the circuit can be reset during this time by the application of a negative pulse to the RESET pin. The output remains in the low state until a trigger pulse is applied again. www.ti.com LMC555 SNAS558N – JANUARY 2000 – REVISED MARCH 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: LMC555

When the reset function is not used, connect the RESET pin to V+ to avoid any possibility of false triggering. Figure 7-4 is a nomograph for easy determination of RC values for various time delays. Note In monostable operation, drive the trigger high before the end of timing cycle. Figure 7-4. Time Delay

7.4.2 Astable Operation

If the circuit is connected as shown in Figure 7-5 (TRIGGER and THRESHOLD pins connected together), the circuit triggers and free runs as a multivibrator. The external capacitor charges through R A + RB and discharges through RB. Thus, the duty cycle can be precisely set by the ratio of these two resistors. Figure 7-5. Astable (Variable Duty Cycle Oscillator) In this mode of operation, the capacitor charges and discharges between 1/3 V S and 2/3 VS. As in the triggered mode, the charge and discharge times, and therefore, the frequency are independent of the supply voltage. Figure 7-6 shows the waveform generated in this mode of operation. LMC555 SNAS558N – JANUARY 2000 – REVISED MARCH 2024 www.ti.com

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8 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

8.1 Application Information

The LMC555 timer can be used a various configurations, but the most commonly used configuration is in monostable mode. A typical application for the LMC555 timer in monostable mode is to turn on an LED for a specific time duration. A pushbutton is used as the trigger to output a high pulse when trigger pin is pulsed low. This simple application can be modified to fit any application requirement.

8.2 Typical Applications

8.2.1 Flash LED in Monostable Mode

Figure 8-1 shows the schematic of an LMC555 that flashes an LED in monostable mode. Figure 8-1. Schematic of Monostable Mode to Flash an LED

8.2.1.1 Design Requirements

The main design requirement for this application requires calculating the duration of time that the output stays high. The duration of time depends on the R and C values (shown in Figure 7-4 ) and is calculated by the following equation: t = 1.1 × R × C seconds (6) LMC555 SNAS558N – JANUARY 2000 – REVISED MARCH 2024 www.ti.com

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8.2.1.2 Detailed Design Procedure

To allow the LED to flash on for a noticeable amount of time, a 5-second time delay was chosen for this application. Using Equation 6, R × C equals 4.545. If R is chosen as 100 kΩ, C = 45.4 µF. The values of R = 100 kΩ and C = 47 µF were chosen based on standard values of resistors and capacitors. A momentary push button switch connected to ground is connected to the trigger input with a 10-k Ω current limiting resistor pull up to the supply voltage. When the push button is pressed, the TRIGGER pin goes to GND. An LED is connected to the OUTPUT pin with a current limiting resistor in series from the output of the LMC555 to GND. The RESET pin is not used and was connected to the supply voltage.

8.2.1.3 Application Curve

The data shown in Figure 8-2 were collected with the circuit used in the typical applications section. The LMC555 was configured in the monostable mode with a time delay of 5.17 s. The waveforms correspond to:

  • Top Waveform (Blue) – Capacitor voltage
  • Middle Waveform (Purple) – TRIGGER
  • Bottom Waveform (Green) – OUTPUT As the TRIGGER pin pulses low, the capacitor voltage starts charging and the output goes high. The output goes low as soon as the capacitor voltage reaches 2/3 of the supply voltage, which is the time delay set by the R and C value. For this example, the time delay is 5.17 seconds. Figure 8-2. TRIGGER, Capacitor Voltage, and OUTPUT Waveforms in Monostable Mode www.ti.com LMC555 SNAS558N – JANUARY 2000 – REVISED MARCH 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: LMC555

8.2.2 Frequency Divider

The monostable circuit of Figure 8-3 can be used as a frequency divider by adjusting the length of the timing cycle. Figure 8-4 shows the waveforms generated in a divide by three circuit. Figure 8-3. Monostable (One-Shot)

8.2.2.1 Design Requirements

Design a frequency divider by adjusting the length of the timing cycle.

8.2.2.2 Application Curve

Figure 8-4. Frequency Divider Waveforms

8.2.3 Pulse Width Modulator

When the timer is connected in the monostable mode and triggered with a continuous pulse train, the output pulse width can be modulated by a signal applied to the control voltage terminal. Figure 8-5 shows the circuit, and in Figure 8-6 are some waveform examples. Figure 8-5. Pulse Width Modulator

8.2.3.1 Design Requirements

Modulator the output pulse width by the signal applied to the control voltage terminal. LMC555 SNAS558N – JANUARY 2000 – REVISED MARCH 2024 www.ti.com

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8.2.3.2 Application Curve

Figure 8-6. Pulse Width Modulator Waveforms

8.2.4 Pulse Position Modulator

This application uses the timer connected for astable operation, as in Figure 8-7, with a modulating signal again applied to the control voltage terminal. The pulse position varies with the modulating signal, since the threshold voltage and hence the time delay is varied. Figure 8-8 shows the waveforms generated for a triangle wave modulation signal. Figure 8-7. Pulse Position Modulator

8.2.4.1 Design Requirements

Using astable operation vary the pulse position with a modulating signal applied to the control voltage terminal.

8.2.4.2 Application Curve

Figure 8-8. Pulse Position Modulator Waveforms www.ti.com LMC555 SNAS558N – JANUARY 2000 – REVISED MARCH 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: LMC555

8.2.5 50% Duty Cycle Oscillator The frequency of oscillation is: Figure 8-9. 50% Duty Cycle Oscillator

8.2.5.1 Design Requirements

An oscillator with a 50% duty cycle output. LMC555 SNAS558N – JANUARY 2000 – REVISED MARCH 2024 www.ti.com

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8.3 Power Supply Recommendations

The LMC555 requires a voltage supply within 1.5 V to 15 V. Adequate power supply bypassing is necessary to protect associated circuitry; the minimum recommended is 0.1 μF in parallel with 1- μF electrolytic. Place the bypass capacitors as close as possible to the LMC555 and minimize the trace length.

8.4 Layout

8.4.1 Layout Guidelines

Standard PCB rules apply to routing the LMC555. Keep the 0.1 µF capacitor in parallel with a 1-µF electrolytic capacitor as close as possible to the LMC555. Place the capacitor used for the time delay as close as possible to the DISCHARGE pin. Use a ground plane on the bottom layer to provide better noise immunity and signal integrity.

8.4.2 Layout Example

The figure below is the basic layout for various applications.

  • C1 – based on time delay calculations
  • C2 – 0.01 µF bypass capacitor for control voltage pin
  • C3 – 0.1 µF bypass ceramic capacitor
  • C4 – 1-µF electrolytic bypass capacitor
  • R1 – based on time delay calculations
  • U1 – LMC555 CONTROL VOLTAGE GND OUTPUT TRIGGER RESET GND If reset feature is not used, connect RESET to V+ GND Figure 8-10. PCB Layout www.ti.com LMC555 SNAS558N – JANUARY 2000 – REVISED MARCH 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: LMC555

9 Device and Documentation Support

9.1 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

9.2 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

9.3 Trademarks

TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.

9.4 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

9.5 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions. NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision M (July 2016) to Revision N (March 2024) Page

  • Moved timing accuracy, timing shift with supply, timing shift with temperature, astable frequency, maximum frequency, output rise and fall times, and trigger propagation delay parameters from Electrical Characteristics
  • Changed supply current (IS) typical values from 50 µA to 130 µA at VS = 1.5 V; from 100 µA to 180 µA at VS = LMC555 SNAS558N – JANUARY 2000 – REVISED MARCH 2024 www.ti.com

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Changes from Revision L (February 2016) to Revision M (July 2016) Page Changes from Revision K (January 2015) to Revision L (February 2016) Page Changes from Revision J (March 2013) to Revision K (October 2014) Page

  • Added Pin Configuration and Functions, ESD Ratings, Feature Description, Device Functional Modes, Application and Implementation, Power Supply Recommendations, Layout, Device and Documentation Changes from Revision I (March 2013) to Revision J (March 2013) Page

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. www.ti.com LMC555 SNAS558N – JANUARY 2000 – REVISED MARCH 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: LMC555

www.ti.com 5-Mar-2026 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) LMC555CM/NOPB Obsolete Production SOIC (D) | 8 - - Call TI Call TI -40 to 85 LMC 555CM LMC555CMM/NOPB Active Production VSSOP (DGK) | 8 1000 | SMALL T&R Yes SN Level-1-260C-UNLIM -40 to 85 ZC5 LMC555CMM/NOPB.A Active Production VSSOP (DGK) | 8 1000 | SMALL T&R Yes SN Level-1-260C-UNLIM -40 to 85 ZC5 LMC555CMMX/NOPB Active Production VSSOP (DGK) | 8 3500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 85 ZC5 LMC555CMMX/NOPB.A Active Production VSSOP (DGK) | 8 3500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 85 ZC5 LMC555CMMX/NOPB.B Active Production VSSOP (DGK) | 8 3500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 85 ZC5 LMC555CMX/NOPB Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU | SN Level-1-260C-UNLIM -40 to 85 (LM555C, LMC) 555CM LMC555CMX/NOPB.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 (LM555C, LMC) 555CM LMC555CMX/NOPB.B Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 (LM555C, LMC) 555CM LMC555CN/NOPB Active Production PDIP (P) | 8 40 | TUBE Yes NIPDAU Level-1-NA-UNLIM -40 to 85 (LMC, LMC555CN) 555CN LMC555CN/NOPB.A Active Production PDIP (P) | 8 40 | TUBE Yes NIPDAU Level-1-NA-UNLIM -40 to 85 (LMC, LMC555CN) 555CN LMC555CN/NOPBG4 Active Production PDIP (P) | 8 40 | TUBE Yes NIPDAU N/A for Pkg Type -40 to 125 LMC555CN LMC555CN/NOPBG4.A Active Production PDIP (P) | 8 40 | TUBE Yes NIPDAU N/A for Pkg Type -40 to 125 LMC555CN LMC555CTP/NOPB Active Production DSBGA (YPB) | 8 250 | SMALL T&R Yes SNAGCU Level-1-260C-UNLIM -40 to 85 F LMC555CTP/NOPB.A Active Production DSBGA (YPB) | 8 250 | SMALL T&R Yes SNAGCU Level-1-260C-UNLIM -40 to 85 F LMC555CTP/NOPB.B Active Production DSBGA (YPB) | 8 250 | SMALL T&R Yes SNAGCU Level-1-260C-UNLIM -40 to 85 F LMC555CTPX/NOPB Active Production DSBGA (YPB) | 8 3000 | LARGE T&R Yes SNAGCU Level-1-260C-UNLIM -40 to 85 F LMC555CTPX/NOPB.A Active Production DSBGA (YPB) | 8 3000 | LARGE T&R Yes SNAGCU Level-1-260C-UNLIM -40 to 85 F LMC555CTPX/NOPB.B Active Production DSBGA (YPB) | 8 3000 | LARGE T&R Yes SNAGCU Level-1-260C-UNLIM -40 to 85 F Addendum-Page 1

www.ti.com 5-Mar-2026 Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) LMC555IM/NOPB Obsolete Production SOIC (D) | 8 - - Call TI Call TI -40 to 125 LMC 555IM LMC555IMX/NOPB Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (LM555I, LMC) 555IM LMC555IMX/NOPB.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 (LM555I, LMC) 555IM LMC555IMX/NOPB.B Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 (LM555I, LMC) 555IM (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 19-Aug-2026 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 19-Aug-2026 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMC555CMM/NOPB VSSOP DGK 8 1000 208.0 191.0 35.0 LMC555CMMX/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0 LMC555CMMX/NOPB VSSOP DGK 8 3500 366.0 364.0 50.0 LMC555CMX/NOPB SOIC D 8 2500 367.0 367.0 35.0 LMC555CTP/NOPB DSBGA YPB 8 250 208.0 191.0 35.0 LMC555CTPX/NOPB DSBGA YPB 8 3000 208.0 191.0 35.0 LMC555IMX/NOPB SOIC D 8 2500 367.0 367.0 35.0 Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 19-Aug-2026 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) LMC555CN/NOPB P PDIP 8 40 506 13.97 11230 4.32 LMC555CN/NOPB P PDIP 8 40 506 13.97 11230 4.32 LMC555CN/NOPB P PDIP 8 40 506 13.97 11230 4.32 LMC555CN/NOPB P PDIP 8 40 502 14 11938 4.32 LMC555CN/NOPB.A P PDIP 8 40 502 14 11938 4.32 LMC555CN/NOPB.A P PDIP 8 40 506 13.97 11230 4.32 LMC555CN/NOPB.A P PDIP 8 40 506 13.97 11230 4.32 LMC555CN/NOPB.A P PDIP 8 40 506 13.97 11230 4.32 LMC555CN/NOPBG4 P PDIP 8 40 506 13.97 11230 4.32 LMC555CN/NOPBG4.A P PDIP 8 40 506 13.97 11230 4.32 Pack Materials-Page 3

www.ti.com PACKAGE OUTLINE C 6X 0.65 1.95 8X 0.38 0.25 5.05

4.75 TYP

0.15 0.05 0.25 GAGE PLANE 0 -8

1.1 MAX

0.23 0.13 B 3.1 2.9 NOTE 4 A 3.1 2.9 NOTE 3 0.7 0.4 VSSOP - 1.1 mm max heightDGK0008A SMALL OUTLINE PACKAGE 4214862/A 04/2023

0.13 C A B

0.1 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-187. PowerPAD is a trademark of Texas Instruments. A 20 DETAIL A TYPICAL SCALE 4.000

www.ti.com EXAMPLE BOARD LAYOUT

0.05 MAX

0.05 MIN

8X (1.4) 8X (0.45) 6X (0.65) (4.4) (R0.05) TYP VSSOP - 1.1 mm max heightDGK0008A SMALL OUTLINE PACKAGE 4214862/A 04/2023 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. 8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. 9. Size of metal pad may vary due to creepage requirement. TM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 15X SYMM SYMM SEE DETAILS 15.000 METALSOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METALEXPOSED METAL SOLDER MASK DETAILS NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN 8X (1.4) 8X (0.45) 6X (0.65) (4.4) (R0.05) TYP VSSOP - 1.1 mm max heightDGK0008A SMALL OUTLINE PACKAGE 4214862/A 04/2023 NOTES: (continued) 11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 12. Board assembly site may have different recommendations for stencil design. TM SOLDER PASTE EXAMPLE SCALE: 15X SYMM SYMM

www.ti.com PACKAGE OUTLINE C .228-.244 TYP [5.80-6.19] .069 MAX [1.75] 6X .050 [1.27] 8X .012-.020 [0.31-0.51] .150 [3.81] .005-.010 TYP [0.13-0.25] 0 - 8 .004-.010 [0.11-0.25] .010 [0.25].016-.050 [0.41-1.27] 4X (0 -15 ) A .189-.197 [4.81-5.00] NOTE 3 B .150-.157 [3.81-3.98] NOTE 4 4X (0 -15 ) (.041) [1.04] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. 1 8 .010 [0.25] C A B PIN 1 ID AREA SEATING PLANE .004 [0.1] C SEE DETAIL A DETAIL A TYPICAL SCALE 2.800

www.ti.com EXAMPLE BOARD LAYOUT .0028 MAX [0.07] ALL AROUND .0028 MIN [0.07] ALL AROUND (.213) [5.4] 6X (.050 ) [1.27] 8X (.061 ) [1.55] 8X (.024) [0.6] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METAL SOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS EXPOSED METAL OPENING SOLDER MASK METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SYMM 4 5 SEE DETAILS SYMM

www.ti.com EXAMPLE STENCIL DESIGN 8X (.061 ) [1.55] 8X (.024) [0.6] 6X (.050 ) [1.27] (.213) [5.4] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X SYMM SYMM 4 5

www.ti.com PACKAGE OUTLINE C0.575 MAX 0.15 0.11 TYP TYP 8X 0.18 0.16 0.5 TYP 0.5 TYP B E A D 4215100/B 07/2016 DSBGA - 0.575 mm max heightYPB0008 DIE SIZE BALL GRID ARRAY NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. SYMM SYMM BALL A1 CORNER SEATING PLANE BALL TYP 0.05 C 1 2

0.015 C A B

A B C SCALE 9.000 D: Max = E: Max = 1.464 mm, Min = 1.438 mm, Min = 1.403 mm 1.377 mm

www.ti.com EXAMPLE BOARD LAYOUT 8X ( 0.16) ( 0.16) METAL ( 0.16) SOLDER MASK OPENING (0.5) TYP (0.5) TYP 4215100/B 07/2016 DSBGA - 0.575 mm max heightYPB0008 DIE SIZE BALL GRID ARRAY NOTES: (continued) 3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. See Texas Instruments Literature No. SNVA009 (www.ti.com/lit/snva009). SOLDER MASK DETAILS NOT TO SCALE 1 2 A B SYMM SYMM LAND PATTERN EXAMPLE SCALE:40X C NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN METAL TYP (0.5) TYP (0.5) TYP 4215100/B 07/2016 DSBGA - 0.575 mm max heightYPB0008 DIE SIZE BALL GRID ARRAY NOTES: (continued) 4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. 1 2 A B C SYMM SYMM SOLDER PASTE EXAMPLE BASED ON 0.125mm THICK STENCIL SCALE:50X

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