LM9036 Ultra-Low Quiescent Current Voltage Regulator datasheet (Rev. E)
Document overview
- Manufacturer or author: Texas Instruments, Incorporated [SNVS140,E]
- PDF pages: 21
Technical content
www.ti.com SNVS140E –AUGUST 2003–REVISED MARCH 2013 LM9036Ultra-LowQuiescentCurrentVoltageRegulator Check forSamples: LM9036 1FEATURES DESCRIPTION The LM9036 ultra-lowquiescentcurrentregulator 2• Ultralow Ground Pin Current(IGND ≤ 25µA for featureslow dropoutvoltageand low currentintheIOUT = 0.1mA) standby mode. With less than 25µA Ground Pin• Fixed5V,3.3V,50mA Output currentata 0.1mA load,theLM9036 isideallysuited
- Output Tolerance±5% Over Line,Load, and forautomotiveand otherbatteryoperatedsystems. The LM9036 retainsallof the featuresthat areTemperature common to low dropoutregulatorsincludinga low• Dropout VoltageTypically200mV @ IOUT = dropoutPNP pass device,shortcircuitprotection,50mA reversebatteryprotection,and thermalshutdown.
- −45V Reverse TransientProtection The LM9036 has a 40V maximum operatingvoltage limit,a −40°C to +125°C operatingtemperature• InternalShortCircuitCurrentLimit range,and ±5% outputvoltagetoleranceover the• InternalThermal Shutdown Protection entireoutputcurrent,inputvoltage,and temperature• 40V OperatingVoltageLimit range. TypicalApplication *Requiredifregulatorislocatedmore than2″ frompower supplyfiltercapacitor. **Requiredforstability.Must be ratedoverintendedoperatingtemperaturerange.Effectiveseriesresistance(ESR) iscritical,see ElectricalCharacteristics.Locatecapacitoras closeas possibletotheregulatoroutputand ground pins.Capacitancemay be increasedwithoutbound. Connection Diagram Figure1. PFM Top View Order Number LM9036DT-5.0,LM9036DTX-5.0, LM9036DT-3.3,LM9036DTX-3.3 See NS Package Number NDP0003B Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2Alltrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2003–2013,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.
SNVS140E –AUGUST 2003–REVISED MARCH 2013 www.ti.com Figure2.8 Lead VSSOP Figure3.8 Lead SOIC Top View Top View LM9036MMX-5.0 LM9036MX-5.0 See NS Package Number DGK See NS Package Number D These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates. AbsoluteMaximum Ratings(1)(2) InputVoltage(Survival) +55V, −45V ESD Susceptibility(3) ±1.9kV Power Dissipation(4) Internallylimited JunctionTemperature(TJmax ) 150°C StorageTemperatureRange −65°C to+150°C Lead Temperature(Soldering,10 sec.) 260°C (1) AbsoluteMaximum Ratingsindicatelimitsbeyond whichdamage tothedevicemay occur.DC and AC electricalspecificationsdo not applywhen operatingthedevicebeyond itsspecifiedoperatingratings. (2) IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheTexas InstrumentsSalesOffice/Distributorsforavailabilityand specifications. (3) Human body model,100pF dischargethrougha 1.5kΩ resistor. (4) The maximum power dissipationisa functionofTJmax ,θJA,and TA.The maximum allowablepower dissipationatany ambient temperatureisPD = (TJmax − TA)/θJA.Ifthisdissipationisexceeded,thedietemperaturewillriseabove 150°C and theLM9036 willgo intothermalshutdown. OperatingRatings OperatingTemperatureRange −40°C to+125°C Maximum InputVoltage(Operational) 40V SOIC-8 (D)θJA (1) 140°C/W PFM (NDP0003B) θJA (1) 125°C/W PFM (NDP0003B) θJA (2) 50°C/W PFM (NDP0003B) θJC (1) 11°C/W MSO-8 (DGK) θJA (1) 200°C/W (1) Worstcase (FreeAir)perEIA /JESD51-3. (2) TypicalθJA with1 squareinchof2oz copperpad areadirectlyunderthegroundtab.
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www.ti.com SNVS140E –AUGUST 2003–REVISED MARCH 2013 VIN = 14V,IOUT = 10 mA, TJ = 25°C, unlessotherwisespecified.Boldfacelimitsapplyoverentireoperatingtemperature range Min Typical MaxParameter Conditions Units(1) (2) (1) 4.80 5.00 5.20 IOUT = 0.1mA,8V ≤ VIN ≤ 24V 20 25 µA IOUT = 1mA, 8V ≤ VIN ≤ 24V 50 100 QuiescentCurrent(IGND ) IOUT = 10mA, 8V ≤ VIN ≤ 24V 0.3 0.5 mA IOUT = 50mA, 8V ≤ VIN ≤ 24V 2.0 2.5 LineRegulation(Δ VOUT ) 6V ≤ VIN ≤ 40V,IOUT = 1mA 10 30 mV Load Regulation(Δ VOUT ) 0.1mA ≤ IOUT ≤ 5mA 10 30 mV 5mA ≤ IOUT ≤ 50mA 10 30 mV DropoutVoltage(Δ VOUT ) IOUT = 0.1mA 0.05 0.10 V IOUT = 50mA 0.20 0.40 V ShortCircuitCurrent(ISC ) VOUT = 0V 65 120 250 mA RippleRejection(PSRR) Vripple= 1Vrms,Fripple= 120Hz −40 −60 dB OutputBypass Capacitance 0.3Ω ≤ ESR ≤ 8Ω 10 22 µF (COUT ) 0.1mA ≤ IOUT ≤ 50mA (1) TestedlimitsarespecifiedtoTI's AOQL (AverageOutgoingQualityLevel)and 100% tested. (2) Typicalsareat25°C (unlessotherwisespecified)and representthemost likelyparametricnorm. (3) To ensureconstantjunctiontemperature,pulsetestingisused. VIN = 14V,IOUT = 10 mA, TJ = 25°C, unlessotherwisespecified.Boldfacelimitsapplyoverentireoperatingtemperature range Min Typical MaxParameter Conditions Units(1) (2) (1) 3.168 3.30 3.432 IOUT = 0.1mA,8V ≤ VIN ≤ 24V 20 25 µA IOUT = 1mA, 8V ≤ VIN ≤ 24V 50 100 QuiescentCurrent(IGND ) IOUT = 10mA, 8V ≤ VIN ≤ 24V 0.3 0.5 mA IOUT = 50mA, 8V ≤ VIN ≤ 24V 2.0 2.5 LineRegulation(Δ VOUT ) 6V ≤ VIN ≤ 40V,IOUT = 1mA 10 30 mV Load Regulation(Δ VOUT ) 0.1mA ≤ IOUT ≤ 5mA 10 30 mV 5mA ≤ IOUT ≤ 50mA 10 30 mV DropoutVoltage(Δ VOUT ) IOUT = 0.1mA 0.05 0.10 V IOUT = 50mA 0.20 0.40 V ShortCircuitCurrent(ISC ) VOUT = 0V 65 120 250 mA RippleRejection(PSRR) Vripple= 1Vrms,Fripple= 120Hz −40 −60 dB OutputBypass Capacitance 0.3Ω ≤ ESR ≤ 8Ω 22 33 µF (COUT ) 0.1mA ≤ IOUT ≤ 50mA (1) TestedlimitsarespecifiedtoTI's AOQL (AverageOutgoingQualityLevel)and 100% tested. (2) Typicalsareat25°C (unlessotherwisespecified)and representthemost likelyparametricnorm. (3) To ensureconstantjunctiontemperature,pulsetestingisused. Copyright© 2003–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:LM9036
SNVS140E –AUGUST 2003–REVISED MARCH 2013 www.ti.com TypicalPerformance Characteristics Dropout Voltage QuiescentCurrent Figure4. Figure5. QuiescentCurrent QuiescentCurrent Figure6. Figure7. Peak Output Current Figure8.
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www.ti.com SNVS140E –AUGUST 2003–REVISED MARCH 2013 APPLICATIONS INFORMATION UnlikeotherPNP low dropoutregulators,the LM9036 remains fullyoperationalto 40V. Owing to power dissipationcharacteristicsofthepackage,fulloutputcurrentcannotbe ensuredforallcombinationsofambient temperatureand inputvoltage. The junctiontoambientthermalresistanceθJA ratinghas two distinctcomponents:thejunctiontocase thermal resistanceratingθJC;and thecase toambientthermalresistanceratingθCA .The relationshipisdefinedas:θJA = θJC + θCA . On thePFM package thegroundtabisthermallyconnectedtothebacksideofthedie.Adding1 squareinchof2 oz.copperpad areadirectlyunderthegroundtabwillimprovetheθJA ratingtoapproximately50°C/W. WhiletheLM9036 has an internallysetthermalshutdown pointoftypically150°C, thisisintendedas a safety featureonly.Continuousoperationnearthethermalshutdown temperatureshouldbe avoidedas itmay have a negativeaffecton thelifeofthedevice. Using the θJA fora LM9036DT mounted on a circuitboard as definedat,see(1), and usingthe formulafor maximum allowabledissipationgivenin,see(2),foran ambienttemperature(TA)of+85°C, we findthatPDMAX = 1.3W. Includingthe smallcontributionof the quiescentcurrentIQ to the totalpower dissipation,the maximum inputvoltage(whilestilldelivering50mA outputcurrent)is29.5V.The LM9036DT willgo intothermalshutdown when attemptingtodeliverthefulloutputcurrentof50mA, withan ambienttemperatureof+85°C, and theinput voltageis greaterthan 29.5V.Similarly,withan ambient temperatureof 25°C the PDMAX = 2.5W, and the LM9036DT can deliverthefulloutputcurrentof50mA withan inputvoltageofup to40V. WhiletheLM9036 maintainsregulationto55V, itwillnotwithstanda shortcircuitabove 40V because ofsafe operatingarea limitationsin the internalPNP pass device.Above 55V the LM9036 willbreak down with catastrophiceffectson theregulatorand possiblytheloadas well.Do notuse thisdeviceina designwhere the inputoperatingvoltagemay exceed 40V,orwhere transientsarelikelytoexceed 55V. (1) TypicalθJA with1 squareinchof2oz copperpad areadirectlyunderthegroundtab. (2) The maximum power dissipationisa functionofTJmax ,θJA,and TA.The maximum allowablepower dissipationatany ambient temperatureisPD = (TJmax − TA)/θJA.Ifthisdissipationisexceeded,thedietemperaturewillriseabove 150°C and theLM9036 willgo intothermalshutdown. Copyright© 2003–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:LM9036
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REVISION HISTORY
Changes from RevisionD (March 2013)toRevisionE Page
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www.ti.com 11-Nov-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) LM9036DT-5.0/NOPB Active Production TO-252 (NDP) | 3 75 | TUBE Yes SN Level-2-260C-1 YEAR -40 to 125 LM9036D T-5.0 LM9036DT-5.0/NOPB.B Active Production TO-252 (NDP) | 3 75 | TUBE Yes SN Level-2-260C-1 YEAR -40 to 125 LM9036D T-5.0 LM9036DTX-5.0/NOPB Active Production TO-252 (NDP) | 3 2500 | LARGE T&R Yes SN Level-2-260C-1 YEAR -40 to 125 LM9036D T-5.0 LM9036DTX-5.0/NOPB.B Active Production TO-252 (NDP) | 3 2500 | LARGE T&R Yes SN Level-2-260C-1 YEAR -40 to 125 LM9036D T-5.0 LM9036M-3.3/NOPB Active Production SOIC (D) | 8 95 | TUBE Yes SN Level-1-260C-UNLIM -40 to 125 LM903 6M-3 LM9036M-3.3/NOPB.B Active Production SOIC (D) | 8 95 | TUBE Yes SN Level-1-260C-UNLIM -40 to 125 LM903 6M-3 LM9036M-5.0/NOPB Active Production SOIC (D) | 8 95 | TUBE Yes SN Level-1-260C-UNLIM -40 to 125 LM903 6M-5 LM9036M-5.0/NOPB.B Active Production SOIC (D) | 8 95 | TUBE Yes SN Level-1-260C-UNLIM -40 to 125 LM903 6M-5 LM9036MM-3.3/NOPB Active Production VSSOP (DGK) | 8 1000 | SMALL T&R Yes SN Level-1-260C-UNLIM -40 to 125 KDB LM9036MM-3.3/NOPB.B Active Production VSSOP (DGK) | 8 1000 | SMALL T&R Yes SN Level-1-260C-UNLIM -40 to 125 KDB LM9036MM-5.0/NOPB Active Production VSSOP (DGK) | 8 1000 | SMALL T&R Yes SN Level-1-260C-UNLIM -40 to 125 KDA LM9036MM-5.0/NOPB.B Active Production VSSOP (DGK) | 8 1000 | SMALL T&R Yes SN Level-1-260C-UNLIM -40 to 125 KDA LM9036MX-3.3/NOPB Active Production SOIC (D) | 8 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 LM903 6M-3 LM9036MX-3.3/NOPB.B Active Production SOIC (D) | 8 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 LM903 6M-3 LM9036MX-5.0/NOPB Active Production SOIC (D) | 8 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 LM903 6M-5 LM9036MX-5.0/NOPB.B Active Production SOIC (D) | 8 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 LM903 6M-5 (1) Status: For more details on status, see our product life cycle. Addendum-Page 1
www.ti.com 11-Nov-2025 (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2
PACKAGE MATERIALS INFORMATION www.ti.com 10-Aug-2026 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION www.ti.com 10-Aug-2026 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM9036DTX-5.0/NOPB TO-252 NDP 3 2500 356.0 356.0 36.0 LM9036MM-3.3/NOPB VSSOP DGK 8 1000 208.0 191.0 35.0 LM9036MM-5.0/NOPB VSSOP DGK 8 1000 208.0 191.0 35.0 LM9036MX-3.3/NOPB SOIC D 8 2500 367.0 367.0 35.0 LM9036MX-5.0/NOPB SOIC D 8 2500 367.0 367.0 35.0 Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION www.ti.com 10-Aug-2026 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) LM9036DT-5.0/NOPB NDP TO-252 3 75 508 20 4165.6 3.1 LM9036DT-5.0/NOPB.B NDP TO-252 3 75 508 20 4165.6 3.1 LM9036M-3.3/NOPB D SOIC 8 95 495 8 4064 3.05 LM9036M-3.3/NOPB.B D SOIC 8 95 495 8 4064 3.05 LM9036M-5.0/NOPB D SOIC 8 95 495 8 4064 3.05 LM9036M-5.0/NOPB.B D SOIC 8 95 495 8 4064 3.05 Pack Materials-Page 3
www.ti.com PACKAGE OUTLINE C 6X 0.65 1.95 8X 0.38 0.25 5.05
4.75 TYP
0.15 0.05 0.25 GAGE PLANE 0 -8
1.1 MAX
0.23 0.13 B 3.1 2.9 NOTE 4 A 3.1 2.9 NOTE 3 0.7 0.4 VSSOP - 1.1 mm max heightDGK0008A SMALL OUTLINE PACKAGE 4214862/A 04/2023
0.13 C A B
0.1 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-187. PowerPAD is a trademark of Texas Instruments. A 20 DETAIL A TYPICAL SCALE 4.000
www.ti.com EXAMPLE BOARD LAYOUT
0.05 MAX
0.05 MIN
8X (1.4) 8X (0.45) 6X (0.65) (4.4) (R0.05) TYP VSSOP - 1.1 mm max heightDGK0008A SMALL OUTLINE PACKAGE 4214862/A 04/2023 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. 8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. 9. Size of metal pad may vary due to creepage requirement. TM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 15X SYMM SYMM SEE DETAILS 15.000 METALSOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METALEXPOSED METAL SOLDER MASK DETAILS NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED
www.ti.com EXAMPLE STENCIL DESIGN 8X (1.4) 8X (0.45) 6X (0.65) (4.4) (R0.05) TYP VSSOP - 1.1 mm max heightDGK0008A SMALL OUTLINE PACKAGE 4214862/A 04/2023 NOTES: (continued) 11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 12. Board assembly site may have different recommendations for stencil design. TM SOLDER PASTE EXAMPLE SCALE: 15X SYMM SYMM
www.ti.com PACKAGE OUTLINE C 10.42 9.40 6.73 6.35 6.22 5.97 1.27 0.88 5.46 4.96 2.285 4.57 1.02 0.64 3X 0.88 0.64
2.55 MAX
0.88 0.46 1.14 0.89 0.60 0.46 0.17
0.51 MIN
4.32 MIN
(2.345) (2.5) TO-252 - 2.55 mm max heightNDP0003B TRANSISTOR OUTLINE 4219870/A 03/2018 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Reference JEDEC registration TO-252.
0.25 C A B
TOP & BOTTOM PKG OPTIONAL SEATING PLANE SCALE 1.500 A B
www.ti.com EXAMPLE BOARD LAYOUT
0.07 MAX
0.07 MIN
(4.57) 2X (1.3) 2X (2.15) (5.7) (5.5) (2.285)(4.38) (R0.05) TYP TO-252 - 2.55 mm max heightNDP0003B TRANSISTOR OUTLINE 4219870/A 03/2018 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature numbers 5. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged or tented. LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 8X SYMM PKG SEE SOLDER MASK DETAIL EXPOSED METAL METAL EDGE SOLDER MASK OPENING NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DETAIL EXPOSED METAL METAL UNDER SOLDER MASK SOLDER MASK OPENING SOLDER MASK DEFINED
www.ti.com EXAMPLE STENCIL DESIGN 2X (2.15) 2X (1.3) (4.57) (4.38) (1.32) TYP (1.35) TYP (0.26) (R0.05) TYP 16X (1.12) 16X (1.15) TO-252 - 2.55 mm max heightNDP0003B TRANSISTOR OUTLINE 4219870/A 03/2018 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 7. Board assembly site may have different recommendations for stencil design. PKG SOLDER PASTE EXAMPLE BASED ON 0.125 MM THICK STENCIL SCALE: 8X
www.ti.com PACKAGE OUTLINE C .228-.244 TYP [5.80-6.19] .069 MAX [1.75] 6X .050 [1.27] 8X .012-.020 [0.31-0.51] .150 [3.81] .005-.010 TYP [0.13-0.25] 0 - 8 .004-.010 [0.11-0.25] .010 [0.25].016-.050 [0.41-1.27] 4X (0 -15 ) A .189-.197 [4.81-5.00] NOTE 3 B .150-.157 [3.81-3.98] NOTE 4 4X (0 -15 ) (.041) [1.04] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. 1 8 .010 [0.25] C A B PIN 1 ID AREA SEATING PLANE .004 [0.1] C SEE DETAIL A DETAIL A TYPICAL SCALE 2.800
www.ti.com EXAMPLE BOARD LAYOUT .0028 MAX [0.07] ALL AROUND .0028 MIN [0.07] ALL AROUND (.213) [5.4] 6X (.050 ) [1.27] 8X (.061 ) [1.55] 8X (.024) [0.6] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METAL SOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS EXPOSED METAL OPENING SOLDER MASK METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SYMM 4 5 SEE DETAILS SYMM
www.ti.com EXAMPLE STENCIL DESIGN 8X (.061 ) [1.55] 8X (.024) [0.6] 6X (.050 ) [1.27] (.213) [5.4] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X SYMM SYMM 4 5
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