LM8342

LM8342 Programmable TFT V COM Calibrator with Non-Volatile Memory datasheet (Rev. B)

Document overview

• Manufacturer or author: Texas Instruments, Incorporated [SNOSAM0,B]
• PDF pages: 23

Technical content

15 k:15 k:15 k: R SET LM8342 LM8342 www.ti.com SNOSAM0B –NOVEMBER 2005–REVISED MARCH 2013 LM8342ProgrammableTFTVCOM CalibratorwithNon-VolatileMemory Check forSamples: LM8342 1FEATURES DESCRIPTION The LM8342 isan integratedcombinationof a non- 2• I2C Compatible Programmable DAC toSet the volatileregister(7 bits EEPROM) and a DACOutput Current controlledcurrentsource.Using the LM8342, the• Ensured Monotonic DAC VCOM calibrationprocedureissimplifiedby elimination

• Non-VolatileMemory toHold theSetting ofthepotentiometeradjustmenttask.Thisadjustment task is currentlyperformed at the factoryusing a• EEPROM inSystem Programmable trimmeradjustmenttooland visualinspection.• No ExternalProgramming VoltageRequired The VCOM adjustmentcan be done electronicallyin• Maximum InterfaceBus Speed is400 kHz production,using the I2C compatibleinterface.The• SON-10 Package factoryoperatorcan physicallyviewthescreenhead- on (frontalviewing)when performingthisstep,easing APPLICATIONS manufacturingespeciallyforlargeTFT panels.
• TFT Panel FactoryCalibration The VCOM levelistypicallyat halfAV DD (determined by R1 and R2) and isbufferedby the actualVCOM• DigitalPotentiometer driver.By controllingthelevelofIOUT ,theVCOM level• Programmable CurrentSink can be tuned.The currentlevelat the outputof the LM8342 is a fraction(1/128 to 128/128) of a maximum currentwhichissetby R SET and an analog reference(AVDD ).The actualfractionisdetermined by the 7-bitDAC. As a result,the outputcurrentof theLM8342 has a good temperaturestabilityyielding a verystableVCOM adjustment.Controllingthe DAC settingoftheLM8342 isdone viaitsI2C compatible interface.The actualDAC settingis stored in a volatileregister.Using a “WritetoEE ” command the data can be storedpermanentlyin the embedded EEPROM. At power on of the device,the EEPROM dataiscopiedtothevolatileregister,settingtheDAC. At any time,the data in the EEPROM can be changed againviatheI2C compatibleinterface. TypicalApplication Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2Alltrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2005–2013,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

SNOSAM0B –NOVEMBER 2005–REVISED MARCH 2013 www.ti.com These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates. AbsoluteMaximum Ratings(1) SCL, SDA Pins 4 kV Human Body Model ESD Tolerance(2) AllOtherPins 2.5kV Machine Model 250V VDD 5V Supplyand ReferenceVoltage AV DD 20V StorageTemperatureRange −65°C to+150°C JunctionTemperature(3) +150°C InfraredorConvection(20sec.) 235°C SolderingInformation Wave Soldering(10sec.) 260°C (1) AbsoluteMaximum Ratingsindicatelimitsbeyond whichdamage tothedevicemay occur.OperatingRatingsindicateconditionsfor whichthedeviceisintendedtobe functional,butspecificperformanceisnotensured.Forspecifiedspecificationsand testconditions, see theElectricalCharacteristicstables. (2) Human Body Model is1.5kΩ inserieswith100 pF.Machine Model is0Ω inserieswith200 pF. (3) The maximum power dissipationisa functionofTJ(MAX),θJA and TA.The maximum allowablepower dissipationatany ambient temperatureisPD = (TJ(MAX) — TA)/θJA.Allnumbers applyforpackagessoldereddirectlyontoa PC board. OperatingRatings(1) OperatingTemperatureRange (2) −40°C to85°C DigitalSupply(VDD )(3) 2.25Vto3.6V DigitalSupply(VDD )@ Programming 2.6Vto3.6V AnalogReference(AVDD )(3) 4.5Vto18V Package ThermalResistanceθJA (4) 52°C/W (1) AbsoluteMaximum Ratingsindicatelimitsbeyond whichdamage tothedevicemay occur.OperatingRatingsindicateconditionsfor whichthedeviceisintendedtobe functional,butspecificperformanceisnotensured.Forspecifiedspecificationsand testconditions, see theElectricalCharacteristicstables. (2) Programming temperaturerange0°C to70°C . (3) When AV DD isinthevoltagerangeof4.5Vto13V,thesupplyvoltageVDD can be in2.25Vto3.6Vrange.When AV DD isinthevoltage rangefrom13V to18V,thesupplyvoltageVDD islimitedtothe2.6Vto3.6Vrange (4) The maximum power dissipationisa functionofTJ(MAX),θJA and TA.The maximum allowablepower dissipationatany ambient temperatureisPD = (TJ(MAX) — TA)/θJA.Allnumbers applyforpackagessoldereddirectlyontoa PC board.

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www.ti.com SNOSAM0B –NOVEMBER 2005–REVISED MARCH 2013 ElectricalCharacteristics Unlessotherwisespecified,alllimitsarespecifiedforTJ = 25°C, VDD = 3V,AV DD = 15V,VOUT = 1/2AV DD and R SET = 10 kΩ. Boldfacelimitsapplyatthetemperatureextremes.(1) Symbol Parameter Conditions Min (2) Typ (3) Max (2) Units Supply and ReferenceCurrent IDD SupplyCurrent 40 62 μA AIDD AnalogReferenceCurrent 8 13 μA Controland Programming Low Voltage 0.3*VDD V HighVoltage 0.7*VDD SCL, SDA InputCurrent 1 μA Frequency 400 kHz WP P/WP N Low Level 0.3*VDD V WP P/WP N HighLevel 0.7*VDD V WP N InputCurrent VIH = 3.0V(4) 100 µA R ON SCL toSCL-S SwitchResistance 150 Ω SDA/SCL InputCapacitance 5 pF SCL-S InputCapacitance 3 pF No Supply,VSDA ,SDA/SCL/SCL-S loadcurrent 1 μAVSCL = 3.6V Programming Time See (5) 200 300 ms IDD @ Programming 10 18 mA Programming Cycles 1000 ReadingCycles 10000 Output OutputSettlingTime 95% ofFinalValue 10 μs Start-UpTime 30 μs VOUT VRSETOutputVoltage AV DD V+ 0.5V IOUT Adjustability 7 Bits DifferentialNon-Linearity −1 1 AV DD = 10V,OutputCurrent ZeroScaleError −1 1.5 LSBVOUT = 5V FullScaleError −4 4 FullScaleRange 5 100 μA VoltageDriftVRSET −1 1 LSB (1) ElectricalTablevaluesapplyonlyforfactorytestingconditionsatthetemperatureindicated.Factorytestingconditionsresultinvery limitedself-heatingofthedevicesuch thatTJ = TA.No assuranceofparametricperformanceisindicatedintheelectricaltablesunder conditionsofinternalself-heatingwhere TJ > TA. (2) Alllimitsareensuredby designorstatisticalanalysis. (3) Typicalvaluesrepresenttheparametricnorm atthetimeofcharacterization. (4) On-ChipPullDown Resistorof30 kΩ. (5) Programming temperaturerange0°C to70°C . Copyright© 2005–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:LM8342

SNOSAM0B –NOVEMBER 2005–REVISED MARCH 2013 www.ti.com CONNECTION DIAGRAM Figure1. 10-PinSON Top View PIN DESCRIPTIONS Pin Name Pin # Function OUT 1 Currentsinkoutput,adjustablein128 steps.See ApplicationSectionfordetails. AV DD 2 Analogreferencevoltageinput WP N 3 Writeprotect(input) READ (I2C) WRITE →Reg WRITE →EE SCL Switch WP N = Low yes yes no open WP N = High yes yes yes closed WP P 4 InvertedWP N (output) GND 5 Ground VDD 6 Supplyvoltage SDA 7 I2C compatibleserialdatainput/output SCL 8 I2C compatibleserialclockinput SCL-S 9 SwitchedSCL connection.Serialclockinputwhen WP N issettohigh SET 10 Maximum outputcurrentadjustmentpin(seeblockdiagram) DAP LeftfloatingorconnecttoGND

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R DAC

7 BITS

www.ti.com SNOSAM0B –NOVEMBER 2005–REVISED MARCH 2013 Block Diagram Copyright© 2005–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:LM8342

0.1 1 10 100 R SET (k:) 100 1000 10000 IOUT (PA) VDD = 2.25V VDD = 3V VDD = 3.6V AV DD = 10V VOUT = 5V 0.1 1 10 100 R SET (k:) 100 1000 10000 IOUT (PA) AV DD = 4.5V AV DD = 10V AV DD = 18V TIME (20Ps/DIV) VOLTAGE (2V/DIV) R SET = 10 k: R L = 40 k: AV DD VOUT VOLTAGE (1 V/DIV) TIME (20 Ps/DIV) R SET = 10 k: R L = 40 k: VOUT VDD INTERMEDIATE STARTUP CODE (MID SCALE) 85° C 25° C -40° C VDD (V) IDD (PA) VDD = 2.25V VDD = 3.6V VDD = 3.0V -15-40 10 35 60 85 TEMPERATURE (° C) IDD (PA) LM8342 SNOSAM0B –NOVEMBER 2005–REVISED MARCH 2013 www.ti.com TypicalPerformance Characteristics AtTJ = 25°C, VDD = 3V,AV DD = 15V,VOUT = 1/2AV DD and R SET = 10 kΩ,unlessotherwisespecified. IDD vs.VDD IDD vs.Temperature Figure2. Figure3. AV DD Startup(FullScale) VDD Startup(FullScale) Figure4. Figure5. IOUT vs.R SET IOUT vs.R SET Figure6. Figure7.

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0 16 32 48 64 80 96 112 128 DAC SETTING -0.20 -0.15 -0.10 -0.05 0.00 0.05 0.10 0.15 0.20 DIFFERENTIAL NON-LINEARITY (LSB) VOUT = 18V VOUT (V) OFFSET CHANGE (LSB) 0.3 0.2 0.1 -0.1 -0.2 -0.3 GAIN CHANGE (%) 2 6 10 14 18 OFFSET CHANGE GAIN CHANGE 0 2 4 6 8 10 12 14 16 18 IOUT (PA) VOUT (V) FULL SCALE MID SCALE ZERO SCALE 1 2 3 4 5 6 7 8 9 10 -0.8 -0.6 -0.4 -0.2 0.2 0.4 0.6 0.8 IOUT ERROR (LSB) VOUT (V) FULL SCALE MID SCALE ZERO SCALE IOUT (25 PA/DIV) TIME (10 Ps/DIV) IOUT (25 PA/DIV) TIME (10 Ps/DIV) LM8342 www.ti.com SNOSAM0B –NOVEMBER 2005–REVISED MARCH 2013 TypicalPerformance Characteristics(continued) AtTJ = 25°C, VDD = 3V,AV DD = 15V,VOUT = 1/2AV DD and R SET = 10 kΩ,unlessotherwisespecified. IOUT CurrentStep Negative(FullScale) IOUT CurrentStep Positive(FullScale) Figure8. Figure9. IOUT vs.VOUT IOUT Errorvs.VOUT Figure10. Figure11. DifferentialNon-LinearityErrorvs.DAC Gain & OffsetChange vs.VOUT (VOUT = 18V) Figure12. Figure13. Copyright© 2005–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:LM8342

0 16 32 48 64 80 96 112 128 DAC SETTING -0.2 -0.15 -0.1 -0.05 0.05 0.1 0.15 0.2 INTEGRAL NON-LINEARITY (LSB) 0 16 32 48 64 80 96 112 128 DAC SETTING -0.2 -0.15 -0.1 -0.05 0.05 0.1 0.15 0.2 TOTAL UNADJUSTED ERROR (LSB) 0 10 20 30 40 50 60 70 80 TEMPERATURE (° C) -0.2 -0.15 -0.1 -0.05 0.05 0.1 0.15 0.2 IOUT ERROR (LSB) 5 7.5 10 12.5 15 17.5 20 AV DD (V) -0.2 -0.15 -0.1 -0.05 0.05 0.1 0.15 0.2 IOUT ERROR (LSB) FULL SCALE MID SCALE ZERO SCALE -0.02 -0.015 -0.01 -0.005 0.01 0.015 0.02 IOUT ERROR (LSB) VDD (V) MID SCALE ZERO SCALE FULL SCALE 0.005 LM8342 SNOSAM0B –NOVEMBER 2005–REVISED MARCH 2013 www.ti.com TypicalPerformance Characteristics(continued) AtTJ = 25°C, VDD = 3V,AV DD = 15V,VOUT = 1/2AV DD and R SET = 10 kΩ,unlessotherwisespecified. IOUT Errorvs.VDD IOUT Errorvs.AV DD Figure14. Figure15. IOUT Errorvs.Temperature TotalUnadjusted Errorvs.DAC Figure16. Figure17. IntegralNon-LinearityErrorvs.DAC Figure18.

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0 16 32 48 64 80 96 112 128 DAC SETTING -0.2 -0.15 -0.1 -0.05 0.05 0.1 0.15 0.2 DIFFERENTIAL NON-LINEARITY (LSB) 100 150 200 250 300 350 400 450 R ON (:) SCL-S VOLTAGE (V) SCL VIA SERIES RESISTOR 1.5 k: CONNECTED TO V DD VDD = 2.25V VDD = 3.0V VDD = 3.6V LM8342 www.ti.com SNOSAM0B –NOVEMBER 2005–REVISED MARCH 2013 TypicalPerformance Characteristics(continued) AtTJ = 25°C, VDD = 3V,AV DD = 15V,VOUT = 1/2AV DD and R SET = 10 kΩ,unlessotherwisespecified. DifferentialNon-LinearityErrorvs.DAC R ON vs.SCL-S Voltage Figure19. Figure20. Copyright© 2005–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:LM8342

± POLARITY LM8342 SNOSAM0B –NOVEMBER 2005–REVISED MARCH 2013 www.ti.com APPLICATION SECTION INTRODUCTION The LM8342 isan integratedcombinationofa digitallycontrolledcurrentsinkand a non-volatileregister(7 bits EEPROM). Programming theregistercan be done usingtheI2C compatibleinterface.The LM8342 replacesthe potentiometeradjustment,and therebysimplifiestheVCOM calibrationprocedure.With theLM8342, thefactory operatorcan physicallyviewthescreenhead-onwhen performingthisstep,easingmanufacturingespeciallyfor largeTFT panelsizes. The followingsectionsdiscusstheprincipleofoperationofa TFT-LCD and,subsequentlygivea descriptionof how touse theLM8342, includingtheI2C compatibleinterfaceand controlinputs.Afterthis,two typicalLM8342 configurationsare presented.Subsequently an evaluationsystem is introduced,includinga μC-board programming using the I2C compatibleinterface.At the end of thisapplicationsectionboard layout recommendationsaregiven. PRINCIPLE OF OPERATION OF A TFT-LCD Thissectionoffersa briefoverviewoftheprincipleofoperationofTFT-LCD ’s.Itgivesa detaileddescriptionof how informationispresentedon thedisplay.Furtheran explanationofhow dataiswrittentothescreenpixels and how thepixelsareselectedisincluded. Figure21. IndividualLCD Pixel Figure21 shows a simplifiedillustrationofan individualLCD pixel.The topand bottomplatesofa pixelconsistof Indium-TinOxide (ITO),which isa transparent,electricallyconductivematerial.ITO isattheinnersurfacesof two glasssubstratesthatare thefrontand back glasspanelsofa TFT display.Sandwiched between two ITO platesisan insulatingmaterial(liquidcrystal).Liquidcrystalsalterthe polarizationof light,dependingon how much voltage(VPIXEL) isappliedacrossthetwo plates.Polarizersare placedon theoutersurfacesofthetwo glasssubstrates.Incombinationwiththeliquidcrystal,thepolarizerscreatean electricallyvariablelightfilterthat modulateslighttransmittedfromtheback tothefrontofa display.A pixel’s bottomplateisatthebacksideofa displaywhere a lightsourceisapplied,and thetopplateisatthefront,facingtheviewer.Formost TFT displays, a pixeltransmitsthe greatestamount of lightwhen VPIXEL ≤ ±0.5V,and itbecomes lesstransparentas the voltageincreaseswitheitherpositiveornegativepolarity.

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& LDO TIMING CONTROL VCOM CALIBRATOR VREF GAMMA CORRECTION CURVE LM8207

18 GAMMA BUFFER VCOM

www.ti.com SNOSAM0B –NOVEMBER 2005–REVISED MARCH 2013 Figure22. TFT Display Figure22 shows a simplifieddiagramofa TFT display,showinghow individualpixelsareconnectedtotherow, column and VCOM driver.Each pixelisrepresentedby a capacitorwithan NMOS transistorconnectedtoitstop plate.Pixelsina TFT panelare arrangedinrows and columns.Row linesare connectedtotheNMOS gates, and column linestotheNMOS sources.The back plateofeverypixelisconnectedtoa common voltagecalled VCOM . The voltageappliedto the top plates(i.e.Gamma Voltage)controlsthe pixelbrightness.The column driverssupplythisgamma voltageviathecolumn lines,and ‘write’thisvoltagetothepixelsone row ata time. Thisisaccomplishedby havingthe row driversselectingan individualrow of pixelswhen the column drivers writethegamma voltagelevels.The row driverssequentiallyapplya largepositivepulse(typically25V to35V) to each row line.Thisturnson the NMOS transistorsconnectedto an individualrow,allowingvoltagefrom the column linestobe writtentothepixels. Figure23. TFT Panel Block Diagram Figure23 shows a blockdiagramofa TFT panel.The VCOM buffersuppliesa common voltage(VCOM )toallthe pixelsina TFT panel.Ingeneral,VCOM isa DC voltagethatisinthemiddleofthegamma voltagerange.Screen performancecan be optimizedby tuningtheVCOM voltageinthecalibrationprocedure.Using theLM8342, the VCOM calibrationprocedureissimplifiedby eliminationofthepotentiometeradjustmenttask.Thistaskiscurrently performedatthefactoryusinga trimmeradjustmenttooland visualinspection,when usinga stablereference voltageand a potentiometeras a voltagedividertogeneratetheVCOM voltage. Copyright© 2005–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:LM8342

IOUT = IOUT_MAX x DAC 10 + 1 128 IOUT_MAX = 1 R SET AV DD x SET LM8342 R SET I2C COMPATIBLE BUS IOUT CONTROLLER DIGITAL/ ANALOG CONVERTER OUT AV DD MEMORY + LM8342 SNOSAM0B –NOVEMBER 2005–REVISED MARCH 2013 www.ti.com PRINCIPLE OF OPERATION OF THE LM8342 The LM8342 isan integratedcombinationofa digitallycontrolledcurrentsinkand a non-volatileregister(7 bits EEPROM). Writingdatacan be done usingtheI2C compatibleinterface.Data can be writtentoa volatileregister and can alsobe storedin the non-volatileEEPROM. A simplifiedblockdiagram of the LM8342 isgivenin Figure24. Figure24. Block Diagram oftheLM8342 The maximum outputcurrentoftheLM8342 can be definedusingan externalresistorR SET incombinationwith an analogreferencevoltageAV DD .Thismaximum currentcan be calculatedusingEquation1. (1) The operatingrangefortheoutputcurrentisgivenintheElectricalCharacteristicstable.Variationsofthevoltage referenceAV DD ortheexternalresistorR SET willaffectthisoutputcurrent.Usinga resistorwitha lowtemperature coefficientisrecommended. The relativevalueofIOUT withrespecttothemaximum currentcan be controlleddigitallyin128 steps,usingthe internalDAC. Thisresultsinan outputcurrentdescribedby Equation2. (2) Using the serialinterfacebus the operatorcan storethe DAC valuein the LM8342s 7-bitsvolatileregister temporarily,orpermanentintheEEPROM. Duringa start-upsequence theLM8342 willcopy thecontentsofthe EEPROM totheregistersettingtheDC value. CONTROLLING THE DEVICE The LM8342s currentsinkcan be programmed usinga serialinterfacebus.Additionalfunctions(e.g.storingdata intheEEPROM) can be controlledincombinationwithexternalinputs.Table1 shows thepinsoftheLM8342 and givesa shortfunctionaldescription. Table1. Pin Descriptions Pin name Function SDA & SCL The LM8342 outputcurrentcan be controlledusingtheserialI2C compatibleinterface.This2- (Serialinterfacebus) Wireinterfaceuses a clockand a datasignal.New valuescan be writtentothememory, orthe currentvaluecan be readback fromthedevice.The I2C compatibleinterfaceisdiscussedin more detailinthenextchapter. AV DD AnalogreferencevoltagefortheDAC. VDD Supplyvoltageforboththeanalogand digitalcircuitry. SET An externalresistorR SET connectedtotheSET pindeterminesthemaximum outputcurrent,see Equation1. OUT The outputoftheprogrammablecurrentsink.

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D4 D3 D21 0 0 1 1 A D6 D5 D1 D0 P A1 1 STOPSTART WR/ SDA SCL LM8342 SLAVE A SLAVE B VDD PULL-UP RESISTORS MASTER LM8342 www.ti.com SNOSAM0B –NOVEMBER 2005–REVISED MARCH 2013 Table1. Pin Descriptions(continued) Pin name Function SCL-S Forin-circuitPCB testing,theLM8342 can use theadditionalSwitchedSCL signal(SCL-S)input forapplyingtheSCL clocksignal. WP N “WriteProtectNot”(Input)has 2 functions: 1.ProhibitsprogrammingtheEEPROM, when loworleftfloating(Internala pull-downresistoris connected)When WP N issettoa lowlevel,onlythevolatileregisterisaccessible.IfWP N isset toa highlevelalsotheEEPROM isaccessible.ActualwritingtotheEEPROM ortheregisteris done usingthe“P-bit”intheserialcommunication. 2.WP N switchestheSCL-S clockline.When WP N issettoa highlevelSCL-S isconnectedto SCL. The operatorshouldturnofftheoriginalSCL clock. WP P WriteProtectSignal(Output).ThisistheinvertedWP N signal. I2C SERIAL INTERFACE BUS The LM8342 supportsan I2C compatiblecommunication protocol,which is a bidirectionalbus oriented communicationprotocol.Any devicethatsends data on the bus isdefinedas a transmitterand the receiving deviceas a receiver.The I2C compatiblecommunicationprotocoluses 2 wires:SDA (SerialData Line)and SCL (SerialClockLine).For bothlinesan externalpull-upresistor,connectedtothesupplyvoltage,isrequired.The devicecontrollingthe bus isknown as the master,and the deviceor devicesbeingcontrolledare the slaves. Each devicehas itsown specificaddress.The address of the LM8342 is 9EHEX . The master initiatesthe communicationand providestheclock.The LM8342 alwaysoperatesas a slave.A typicalsystem usingan I2C compatibleinterfacebus isgiveninFigure25. Figure25. System Using an I2C compatibleBus The LM8342 can be used in an I2C compatiblesystem.Allspecificationsof the LM8342, dealingwiththe interfacebus, are ensured by design.Except for the bus speed, which is specifiedin the Electrical Characteristicstable. KEY ASPECT OF I2C COMPATIBLE COMMUNICATION In thissectiona briefoverviewis presented,discussingthe key aspect of I2C compatiblecommunication. Figure26 shows thetimingaspectsoftheI2C compatibleserialinterface. Figure26. Timing Diagram Copyright© 2005–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:LM8342

SNOSAM0B –NOVEMBER 2005–REVISED MARCH 2013 www.ti.com The timingdiagramshows themajoraspectofthecommunicationprotocoland representsa typicaldatastream. Incase a masterwants tosetupa datatransfer,ittestsif“thebus isbusy.” Ifitisnotbusy,thenthemaster startsthe data transferby creatinga “startdata transfer” situation.Accordinglythe correspondingreceiveris selectedby sendingthe appropriate“slaveaddress.” Thisreceivergivesan “acknowledge” on recognizingits addresson thebus.The mastercontinuesthedatatransferby sendingthedatastream.Againthereceivergives an “acknowledge”afterreceipt.Depending on theamount ofdatathemasterwillcontinueorcreatea “stopdata transfer”situation.Table2 givesa more detaileddescriptionoftheI2C compatiblecommunication. Table2. DetailedDescriptionofI2C compatibleCommunication Definitions Bus notbusy The I2C compatiblebus isnotbusy when bothdata(SDA) and clock(SCL)linesremain HIGH. The controllercan initiatedatatransferonlywhen thebus isnotbusy. StartData Transfer Startingfroman idlestate(busnotbusy)a START conditionconsistsofa HIGH to LOW transitionofSDA whileSCL isHIGH. Allcommands must startwitha START condition. Slaveaddress Aftergeneratinga startcondition,themastertransmitsa 7-bitslaveaddress.(The LM8342 uses the8thbitforselectingtheR/W operation,butthisdoes notaffectthe address.)The addressfortheLM8342 is9EHEX . R/W-bit IfthevalueoftheR/W bitisHIGH, thedataisreadfromtheregisteroftheLM8342. OtherwisethecurrentDAC settingiswrittentotheLM8342. Acknowledge A receivedevice,when addressed,isobligedtogeneratean “acknowledge”afterthe receptionofeach byte.The mastergeneratesan extraclockcyclethatisassociated withthisacknowledgebit.The receiverhas topulldown theSDA lineduringthe acknowledgeclockpulseso thattheSDA lineisstableLOW duringtheHIGH periodof SCL, withrespecttotheSCL timingspecifications. Data byte A databyteconsistsof8 bits.7 bitsareused fortheDAC settingoftheLM8342. The 8thbitisknown as theP-bit. P-bit The functionoftheP-bitdepends on theRead/Writeoperation(R/W-bit).Duringa Read operationoftheLM8342, theP-bitindicatestheprogrammingstateoftheEEPROM. Duringa Writeoperation,theregisterorboththeregisterand theEEPROM ofthe LM8342 can be selectedas destination.A more detaileddescriptionoftheP-bitisgiven inTable3 . StopData Transfer A STOP conditionconsistsofa LOW toHIGH transitionofSDA whileSCL isHIGH. All operationsmust be ended witha STOP condition. Table3. P-bitTruthTable Operation P-bit Description Read 1 Programming Ready Read 0 Programming Busy (don’tturnoffthedevice) Write 1 RegisterWrite Write 0 EEPROM Write The LM8342 can be used inI2C compatiblesystemswithclockspeeds ofup to400 kbps (Fastmode).For low speed applications,an initialresistorvalueforthe pull-upresistorsis15 kΩ issuitable.When increasingthe speed oftheinterfacebus,theusershoulddecreasethevalueofthepull-upresistors. TypicalApplication The followingsectiondiscussestwo typicalapplicationsforthe LM8342. In the firstapplicationthe LM8342 is used as a programmable currentsink,forexample to drivea programmable biasgenerator.In the second applicationtheLM8342 isused toadjustthevoltagelevelofa VCOM driver. PROGRAMMABLE CURRENT SINK As describedin the “Principleof Operationof the LM8342 ” sectionthe LM8342 basicallyoperatesas a programmablecurrentsink.Figure27 shows a generalcurrentsinkapplication.

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VCOM = AVDD x ¨¨ x ¨¨ R1 + R2 (DAC 10 + 1) x R1 128 x RSET x 20 1 - SDA SCL-S SCL WP P 6 2 4 5 OUT SET VCOM GND AV DDVDD AV DD IOUT CONTROLLER VDD I2C INTERFACE WP N 15 k:15 k:15 k: R SET LM8342 IOUT = AV DD x R SET x DAC 10 + 1 128 SDA SCL-S SCL WP P 6 2 4 5 OUT SET GND AV DDVDD CONTROLLER VDD I2C INTERFACE WP N 15 k:15 k:15 k: R SET LM8342 IOUT LM8342 www.ti.com SNOSAM0B –NOVEMBER 2005–REVISED MARCH 2013 Figure27. Programmable CurrentSink The outputcurrentoftheLM8342 can be calculatedusingEquation3. (3) DRIVING A VCOM LEVEL Anothertypicalapplication,giveninFigure28, isusingthe LM8342 to adjustthe “voltagetap” of a resistive voltagedivider.The VCOM driverbuffersthe“voltagetap”inthisapplication. Figure28. TypicalApplicationDrivinga VCOM Level The voltageleveloftheVCOM driver,fora generalsettingof(DAC 10),iscalculatedusingEquation4. (4) For calibratingtheVCOM level(seeFigure28)thetuningrangeofthedesignneeds tobe alignedtotherequired VCOM tuningrange(ΔVCOM ).Figure29 givesa graphicalpresentationofthedesiredvoltagelevels. Copyright© 2005–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:LM8342

'VCOM 'VCOM R2 = 40 x RSET x 'VCOM AV DD - 'VCOM R1 = 40 x RSET x 'VCOM AV DD + 'VCOM x R SET x 20VCOM_LOW = AVDD x 1 - R1R2 R1 + R2© VCOM_HIGH = AVDD x 1 - R1R2 R1 + R2 x 128 x RSET x 20© 'VCOM = VCOM_HIGH ± VCOM_LOW GND VCOM_LOW VCOM_HIGH 'VCOMOPERATING V COM RANGEVMID AV DD LM8342 SNOSAM0B –NOVEMBER 2005–REVISED MARCH 2013 www.ti.com Figure29. VCOM VoltageLevels Assume thecalibratorneeds tocoverthevoltagerangegiveninEquation5. (5) The limitsofVCOM forDAC 10 = 0 (highlimit)and DAC 10 = 127 (lowlimit)aregivenby: (6) (7) Using Equation5,Equation6, and Equation7 the valueforresistorsR1 and R2 can be obtained,resultingin Equation8 and Equation9: (8) and (9) Table4 givesan overviewofresistorvaluesfora typicalvalueofAV DD ,and 2 R SET values.Allsettingsarefora VCOM levelatVMID = ½ AV DD ,and a maximum variationofΔVCOM . (10) Table4. Overview ResistorValues forDifferentR SET SettingsatAV DD = 15V AV DD = 15V (VCOM Level= 7.5V) R SET = 10 kΩ R SET = 45 kΩ ΔVCOM R1 R2 ΔVCOM R1 R2 (V) (Ω) (Ω) (V) (Ω) (Ω) ±0.5 25k 28.6k ±0.5 113k 129k ±1 47.1k 61.5k ±1 212k 277k ±1.5 66.7k 100k ±1.5 300k 450k ±2 84.2k 146k ±2 379k 655k

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www.ti.com SNOSAM0B –NOVEMBER 2005–REVISED MARCH 2013 Table4. Overview ResistorValues forDifferentR SET SettingsatAV DD = 15V (continued) ±2.5 100k 200k ±2.5 450k 900k ±3 114k 267k ±3 514k 1.2M EVALUATION SYSTEM For theLM8342 a completeevaluationsystem isavailable,includingtwo boards.Figure30 givesa schematic representation.

• LM8342 EvaluationBoardThisboarddemonstratesthefunctionalityoftheLM8342 usingtheI2C compatible interfaceforcommunication.The LM8342 can easilybe demonstratedin2 applications: – Programmable currentsink – Programmable VCOM leveldriver
• LM8342 Programmer BoardThistestboardhas dedicatedfunctionalityforcommunicatingwiththeLM8342, usingtheI2C compatibleinterface.Thisboardcan operateintwo differentmodes: – Writemode: The digitizedvalueofa potentiometersettingiswrittentotheLM8342. The usercan select on theprogrammer boardtowritethedatatotheregisterortostorethedataintheEEPROM. – Read mode: The boardreadsthestoredvaluesfromtheLM8342 ’s EEPROM and presentsthisdataonto a 3-digitdisplay. Figure30. LM8342 EvaluationSystem LAYOUT RECOMMENDATIONS A properlayoutisnecessaryforoptimum performanceof the LM8342. A low impedance and properground plane(freeofdisturbances)isrecommended, sincea currentofup to10 mA can flowwithHF contentsduring programming.The tracesfrom the GND pin to the ground plane should be as shortas possible.Itis recommended toplacedecouplingcapacitorsclosetotheVDD and AV DD pins.Connectionsofthesedecoupling capacitorstothegroundplaneshouldbe short. As SET isa sensitiveinput,crosstalktothatpinshouldbe prevented.Specialcareshouldbe takenwhen routing theinterfaceconnections.The signalson theserialinterfacecan be more than60 dB largerthantheequivalent LSB at the SET inputpin.Crosstalkbetween the interfacebus and R SET resultsindisturbanceof the output currentIOUT oftheLM8342. For applicationsrequiringa low outputcurrent(usinghighvaluesforR SET incombinationwithlow DAC settings) specialattentionshouldbe paidtotheparasiticcapacitance(CPAR )paralleltoR SET .For C PAR largerthantensof pF, a small(<1 LSB) unwanted rippleattheoutputcurrentmightbe obtained.Itisrecommended toplacethe R SET resistorclosetotheLM8342, incombinationwitha good boardlayouttoreducethisparasiticcapacitance. Copyright© 2005–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:LM8342

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www.ti.com 31-Oct-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) LM8342SD/NOPB Active Production WSON (DSC) | 10 1000 | SMALL T&R Yes SN Level-1-260C-UNLIM -40 to 85 L8342 LM8342SD/NOPB.A Active Production WSON (DSC) | 10 1000 | SMALL T&R Yes SN Level-1-260C-UNLIM -40 to 85 L8342 LM8342SDX/NOPB Active Production WSON (DSC) | 10 4500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 85 L8342 LM8342SDX/NOPB.A Active Production WSON (DSC) | 10 4500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 85 L8342 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 31-Jul-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 31-Jul-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM8342SD/NOPB WSON DSC 10 1000 208.0 191.0 35.0 LM8342SDX/NOPB WSON DSC 10 4500 367.0 367.0 35.0 Pack Materials-Page 2

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