LM8262

LM8262 Dual RRIO, High Output Current and Unlimited Cap Load Op Amp in VSSOP datasheet (Rev. H)

Document overview

• Manufacturer or author: Texas Instruments, Incorporated [SNOS975,H]
• PDF pages: 21

Technical content

LM8262 Dual RRIO, High Output Current and Unlimited Cap Load Op Amp in VSSOP

1 Features

• GBWP: 24MHz
• Wide supply voltage range: 2.7V to 32V
• Slew rate: 35V/µs
• Supply current: 1.35mA
• Unlimited cap load drive
• Output short circuit current: ±125mA
• Rail-to-rail input and output: 3V
• Input voltage noise: 12nV/ √Hz
• Input current noise: 1pA/ √Hz
• THD+N <0.00022%

2 Applications

• TFT‐LCD flat panel VCOM driver
• A/D converter buffer
• High side/low side sensing
• Headphone amplifier

3 Description

The LM8262 is a rail-to-rail input and output op amp which can operate with a wide supply voltage range. This device has high output current drive, greater than rail-to-rail input common mode voltage range, unlimited capacitive load drive capability, and provides tested high speed and slew rate. The device is designed to handle the requirements of flat panel TFT panel V COM driver applications as well as being designed for other low power and medium speed applications which require ease of use and enhanced performance over existing devices. Greater than rail-to-rail input common mode voltage range with 90dB of common mode rejection allows high side and low side sensing for many applications without concern for exceeding the range and with no compromise in accuracy. In addition, most device parameters are insensitive to power supply variations. This design enhancement is yet another step in simplifying the usage. The output stage has low distortion (0.00022% THD+N) and has a high short- circuit output current of 125mA/channel. The LM8262 is offered in the space-saving VSSOP package.

Package Information

PART NUMBER PACKAGE(1) PACKAGE SIZE(2) LM8262 DGK (VSSOP, 8) 3.00mm × 4.90mm (1) For more information, see Mechanical, Packaging, and Orderable Information. (2) The package size (length × width) is a nominal value and includes pins, where applicable. RIN RG RF VOUT VIN Simplified Schematic LM8262 SNOS975H – MAY 2001 – REVISED JUNE 2026 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

6.2 Output Short Circuit Current and Dissipation

9 Mechanical, Packaging, and Orderable Information..14 LM8262 SNOS975H – MAY 2001 – REVISED JUNE 2026 www.ti.com

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4 Pin Configuration and Functions

Figure 4-1. 8-Pin VSSOP Top View Table 4-1. Pin Functions PIN TYPE(1) DESCRIPTION NO. NAME

1 OUT A O Output A

2 -IN A I Inverting input A 3 +IN A I Non-inverting input A

4 V- I Negative supply

5 +IN B I Non-inverting input B 6 -IN B I Inverting input B

7 OUT B O Output B

8 V+ I Positive supply

(1) I = input and O = output www.ti.com LM8262 SNOS975H – MAY 2001 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: LM8262

5 Specifications

5.1 Absolute Maximum Ratings

over operating ambient temperature range (unless otherwise noted)(1) MIN MAX UNIT Supply voltage, VS = (V+) – (V–) 0 33 V Signal input pins Common-mode voltage(3) (V–) – 0.5 (V+) + 0.5 V Differential voltage(4) ±10 V Current(3) ±10 mA Output short-circuit(2) Continuous Junction temperature, TJ 150 °C Storage temperature, Tstg –65 150 °C Soldering Information: Infrared or Convection (20 sec.) 235 °C Wave Soldering (10 sec.) 260 °C (1) Operating the device beyond the ratings listed under Absolute Maximum Ratings will cause permanent damage to the device. These are stress ratings only, based on process and design limitations, and this device has not been designed to function outside the conditions indicated under Recommended Operating Conditions. Exposure to any condition outside Recommended Operating Conditions for extended periods, including absolute-maximum-rated conditions, may affect device reliability and performance. (2) Short-circuit to ground, one amplifier per package. Extended short-circuit current, especially with higher supply voltage, can cause excessive heating and eventual destruction. (3) Input pins are diode-clamped to the power-supply rails. Input signals that may swing more than 0.5V beyond the supply rails must be current limited to 10mA or less. (4) Input pins are connected by back-to-back diodes for input protection. If the differential input voltage may exceed 0.5V, limit the input current to 10mA or less.

5.2 ESD Ratings

V(ESD) Electrostatic discharge(1) Human Body Model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(2) ±2000 VCharged-device model (CDM), per ANSI/ESDA/JEDEC JS-002 (3) ±1500 Machine Model (MM)(2) ±200 (1) Human Body Model, 1.5kΩ in series with 100pF. Machine Model, 0Ω is series with 200pF. (2) JEDEC document JEP155 states that 2000V HBM allows safe manufacturing with a standard ESD control process. (3) JEDEC document JEP157 states that 250V CDM allows safe manufacturing with a standard ESD control process.

5.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT Supply Voltage (V+ - V−) 2.7 32 V Operating Temperature Range(2) −40 +85 °C

5.4 Thermal Information

THERMAL METRIC(1) DGK UNIT

8 PINS

RθJA Junction-to-ambient thermal resistance(2) 169.6 °C/W (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application note. (2) The maximum power dissipation is a function of TJ(max),RθJA, and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(max) - TA)/RθJA. All numbers apply for packages soldered directly onto a PC board. LM8262 SNOS975H – MAY 2001 – REVISED JUNE 2026 www.ti.com

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5.5 Electrical Characteristics

For VS = (V+) – (V–) = 2.7V to 32V (±1.35V to ±16V) at TA = 25°C, RL = 10kΩ connected to VS / 2, VCM= VS / 2, and VOUT = VS / 2, unless otherwise noted.(1) PARAMETER TEST CONDITIONS MIN TYP(2) MAX(3) UNIT VOS Input Offset Voltage VCM =V– ±0.7 ±7 mV TC VOS Input Offset Average Drift VCM =V– −40°C ≤ TA ≤ +125°C ±2 µV/°C IB Input Bias Current ±0.4 ±2 µA IOS Input Offset Current 30 275 nA VCM Input Common-Mode Voltage Range V− V+ V CMRR Common Mode Rejection Ratio V– < VCM < (V+) – 2V −40°C ≤ TA ≤ +125°C 80 100 dB PSRR Power Supply Rejection Ratio VCM= V–, VS = 5V to 32V −40°C ≤ TA ≤ +125°C ±3.5 ±22 μV/V AOL Open Loop Voltage Gain VS = 32V, VCM = VS / 2, Voltage Output Swing from Rail Positive and negative rail headroom VS = 32V, RL = 10KΩ 15.94 V VS = 32V, RL = 2KΩ 15.8 VS = 32V, RL = 10KΩ −15.94 V VS = 32V, RL = 2KΩ −15.8 ISC Output Short Circuit Current VS = 32V ±62 ±125 mA VS = 5V(4) ±50 ±85 IS Supply Current VCM = V−, IO = 0A 1.30 1.93 mA SR Slew Rate VS = 32V, VSTEP = 10V, G = +1, CL = 20pF 35 V/µs GBW Gain-Bandwidth Product 24 MHz Phim Phase Margin G = +1, RL = 10kΩ, CL = 20pF 50 ° en Input Voltage Noise Density f = 1kHz 12 nV/ √ Hz in Input Current Noise Density f = 1kHz 1 pA/ √ Hz ts Settling Time TO 0.1%, VS = 32V, VSTEP = 10V, G = +1, CL = 50pF 430 ns THD+N Total Harmonic Distortion +Noise VS = 32V, VO = 3VRMS, G = 1, f = 1kHz, RL = 10kΩ 113 dB (1) Electrical Table values apply only for factory testing conditions at the temperature indicated. (2) Typical Values represent the most likely parametric norm. (3) All limits are specified by testing or statistical analysis. (4) Specified by characterization only. www.ti.com LM8262 SNOS975H – MAY 2001 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: LM8262

5.6 Typical Characteristics

TA = 25°C, VS = ±16V, VCM = VS/2, Unless Otherwise Noted Figure 5-1. VOS vs. VCM for 3 Representative Units of the Old Die Figure 5-2. VOS vs. VCM for 3 Representative Units of the Old Die Figure 5-3. VOS vs. VCM for 3 Representative Units of the Old Die Figure 5-4. VOS vs. VS for 3 Representative Units of the Old Die Figure 5-5. VOS vs. VS for 3 Representative Units of the Old Die Figure 5-6. VOS vs. VS for 3 Representative Units of the Old Die LM8262 SNOS975H – MAY 2001 – REVISED JUNE 2026 www.ti.com

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5.6 Typical Characteristics (continued)

TA = 25°C, VS = ±16V, VCM = VS/2, Unless Otherwise Noted Figure 5-7. IB vs. VCM of the Old Die Figure 5-8. IB vs. VS of the Old Die Figure 5-9. IS vs. VCM of the Old Die Figure 5-10. IS vs. VCM of the Old Die Figure 5-11. IS vs. VCM of the Old Die Figure 5-12. IS vs. VS (PNP side) of the Old Die www.ti.com LM8262 SNOS975H – MAY 2001 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: LM8262

TA = 25°C, VS = ±16V, VCM = VS/2, Unless Otherwise Noted Figure 5-13. IS vs. VS (NPN side) of the Old Die Figure 5-14. Gain/Phase vs. Frequency of the Old Die Figure 5-15. Unity Gain Frequency vs. VS of the Old Die Figure 5-16. Phase Margin vs. VS of the Old Die Figure 5-17. Unity Gain Frequency and Phase Margin vs. VS of the Old Die F r e q u e n c y ( H z ) C L = 2 0 p F Gain (dB) Phase (degree) - 2 0 - 1 8 0 0 - 1 5 0 2 0 - 1 2 0 4 0 - 9 0 6 0 - 6 0 8 0 - 3 0 1 0 0 0 1 0 0 1 k 1 0 k 1 0 0 k 1 M 1 0 M G a i n ( d B ) P h a s e ( d e g ) Figure 5-18. Open-Loop Gain and Phase vs Frequency, New Die LM8262 SNOS975H – MAY 2001 – REVISED JUNE 2026 www.ti.com

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TA = 25°C, VS = ±16V, VCM = VS/2, Unless Otherwise Noted F r e q u e n c y ( H z ) Gain (dB) - 4 0 - 2 0 2 0 4 0 6 0 8 0 1 0 0 1 k 1 0 k 1 0 0 k 1 M 1 0 M G = 1 G = - 1 G = 1 0 G = 1 0 0 G = 1 0 0 0 Figure 5-19. Closed-Loop Gain vs Frequency, New Die C o m m o n - M o d e V o l t a g e ( V ) Input Bias Current (nA) - 1 6 - 1 2 - 8 - 4 0 4 8 1 2 1 6 - 4 0 0 - 3 0 0 - 2 0 0 - 1 0 0 1 0 0 2 0 0 3 0 0 4 0 0 5 0 0 6 0 0 I B - I B + I O S Figure 5-20. Input Bias Current and Offset Current vs Common- Mode Voltage, New Die Figure 5-21. Output Voltage Swing vs Output Current (Sourcing), New Die O u t p u t C u r r e n t ( m A ) V S = 3 2 V Output Voltage (V) 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 1 4 0 1 6 0 1 8 0 - 1 6 - 1 5 - 1 4 - 1 3 - 1 2 - 1 1 - 1 0 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 4 0 ° C 2 5 ° C 1 2 5 ° C Figure 5-22. Output Voltage Swing vs Output Current (Sinking), New Die F r e q u e n c y ( H z ) Input Voltage Noise Spectral Density (nV/rtHz) 1 0 1 5 2 0 2 5 3 0 3 5 4 0 4 5 1 0 1 0 0 1 k 1 0 k 1 0 0 k Figure 5-23. Input Voltage Noise Spectral Density vs Frequency, New Die F r e q u e n c y ( H z ) G = + 1 V O U T = 3 V R M S B W = 8 0 k H z THD+N (dB) - 1 3 0 - 1 2 0 - 1 1 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 1 0 0 1 k 1 0 k R L = 1 0 k  R L = 2 k  R L = 6 0 0  R L = 1 2 8  Figure 5-24. THD+N Ratio vs Frequency, New Die www.ti.com LM8262 SNOS975H – MAY 2001 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: LM8262

TA = 25°C, VS = ±16V, VCM = VS/2, Unless Otherwise Noted A m p l i t u d e ( V p p ) f = 1 k H z B W = 8 0 k H z G = + 1 THD+N (dB) - 1 3 0 - 1 2 0 - 1 1 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 1 m 1 0 m 1 0 0 m 1 1 0 R L = 1 0 k  R L = 2 k  R L = 6 0 0  Figure 5-25. THD+N vs Output Amplitude, New Die Figure 5-26. Open-Loop Output Impedance vs Frequency, New Die Figure 5-27. Small-Signal Overshoot vs Capacitive Load, New Die

5.7 Old Versus New Die Comparison

As of the publication of revision H of this datasheet, Texas Instruments has moved manufacturing of the die for LM8262 to a modern fabrication site. The two different die are referred to in this document as “old” (previous fabrication site) and “new” die. The die origin can be separated from the “Chip Source Origin” (CSO) parameter in the shipping information. The old die CSO is “GF6”, for the new die the CSO is “RFB”. The old die information is in the shipping information. The old die CSO is “GF6”, for the new die the CSO is “RFB”. The old die information is maintained in this datasheet for comparison purposes, but all new manufacturing has moved to the new die. LM8262 SNOS975H – MAY 2001 – REVISED JUNE 2026 www.ti.com

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6 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

6.1 Driving Capacitive Loads

The LM8262 is specifically designed to drive unlimited capacitive loads without oscillations. In addition, the output current handling capability of the device allows for good slewing characteristics even with large capacitive loads. The combination of these features is designed for applications such as TFT flat panel buffers, A/D converter input amplifiers, and so forth. However, as in most op amps, addition of a series isolation resistor between the op amp and the capacitive load improves the settling and overshoot performance.

6.2 Output Short Circuit Current and Dissipation Issues

The LM8262 output stage is designed for maximum output current capability. Even though momentary output shorts to ground and either supply can be tolerated at all operating voltages, longer lasting short conditions can cause the junction temperature to rise beyond the absolute maximum rating of the device, especially at higher supply voltage conditions. With the op amp tied to a load, the device power dissipation consists of the quiescent power due to the supply current flow into the device, in addition to power dissipation due to the load current. The load portion of the power can include an average value (due to a DC load current) and an AC component. DC load current flows if there is an output voltage offset, or the output AC average current is non-zero, or if the op amp operates in a single supply application where the output is maintained somewhere in the range of linear operation. Therefore: P TOTAL = P Q + P D C + P AC (1) op amp Quiescent Power Dissipation: P Q = I S × V S (2) DC Load Power: P D C = I O × V R − V O (3) Table 6-1 shows AC Load Power (PAC). where

• IS is the supply current
• VS is the total supply voltage (V+ - V−)
• IO is the average load current
• VO is the average output voltage
• VR is V+ for sourcing and V− for sinking current Table 6-1 shows the maximum AC component of the load power dissipated by the op amp for standard sinusoidal, triangular, and square waveforms. www.ti.com LM8262 SNOS975H – MAY 2001 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: LM8262

Table 6-1. Normalized AC Power Dissipated in the Output Stage for Standard Waveforms PAC (W.Ω/V2) Sinusoidal Triangular Square The table entries are normalized to V S 2 / RL. To calculate the AC load current component of power dissipation, simply multiply the table entry corresponding to the output waveform by the factor V S 2 / RL. For example, with ± 15V supplies, a 600Ω load, and triangular waveform power dissipation in the output stage is calculated as: P AC = 46.9 × 10 − 3 × 30 2 600 = 70.4mW (4)

6.3 Other Application Hints

The use of supply decoupling is mandatory in most applications. As with most relatively high speed/high output current op amps, best results are achieved when each supply line is decoupled with two capacitors; a small value ceramic capacitor (approximately 0.01µF) placed very close to the supply lead in addition to a large value Tantalum or Aluminum (> 4.7µF). The large capacitor can be shared by more than one device if necessary. The small ceramic capacitor maintains low supply impedance at high frequencies while the large capacitor acts as the charge "bucket" for fast load current spikes at the Op Amp output. The combination of these capacitors provides supply decoupling and helps keep the op amp oscillation free under any load.

6.4 Power Supply Recommendations

The LM8262 can operate off a single supply or with dual supplies. The input CM capability of the parts (CMVR) extends covers the entire supply voltage range for maximum flexibility. Decouple supplies with low inductance, often ceramic, capacitors to ground less than 0.5 inches from the device pins. The use of ground plane is recommended, and as in most high speed devices, remove the ground plane close to device sensitive pins such as the inputs.

6.5 Layout

6.5.1 Layout Guidelines

Generally, a good high frequency layout keeps power supply and ground traces away from the inverting input and output pins. Parasitic capacitances on these nodes to ground causes frequency response peaking and possible circuit oscillations. General high-speed, signal-path layout suggestions include:

• Continuous ground planes are preferred for signal routing with matched impedance traces for longer runs. However, open up both ground and power planes around the capacitive sensitive input and output device pins. After the signal is sent into a resistor, parasitic capacitance becomes more of a band-limiting issue and less of a stability issue.
• Use good, high-frequency decoupling capacitors (0.1μF) on the ground plane at the device power pins. For best high-frequency decoupling, consider X2Y supply-decoupling capacitors that offer a much higher self-resonance frequency over standard capacitors.
• When using differential signal routing over any appreciable distance, use microstrip layout techniques with matched impedance traces.
• The input summing junction is very sensitive to parasitic capacitance. Connect any Rf, and Rg elements into the summing junction with minimal trace length to the device pin side of the resistor. The other side of these elements can have more trace length if needed to the source or to ground. LM8262 SNOS975H – MAY 2001 – REVISED JUNE 2026 www.ti.com

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7 Device and Documentation Support

7.1 Device Support

7.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

7.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

7.3 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

7.4 Trademarks

TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.

7.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

7.6 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

8 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision G (August 2015) to Revision H (June 2026) Page

• Changed Recommended Operating Conditions supply voltage minimum value from 2.5V to 2.7V and www.ti.com LM8262 SNOS975H – MAY 2001 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: LM8262

Changes from Revision F (August 2014) to Revision G (August 2015) Page Changes from Revision E (April 2013) to Revision F (August 2014) Page

• Changed datasheet structure and organization. Added, updated, or renamed the following sections: Device

9 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this datasheet, refer to the left-hand navigation. LM8262 SNOS975H – MAY 2001 – REVISED JUNE 2026 www.ti.com

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www.ti.com 24-Mar-2026 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) LM8262MM/NOPB Obsolete Production VSSOP (DGK) | 8 - - Call TI Call TI -40 to 85 A46 LM8262MMX/NOPB Active Production VSSOP (DGK) | 8 3500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 85 A46 LM8262MMX/NOPB.B Active Production VSSOP (DGK) | 8 3500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 85 A46 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 24-Mar-2026 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 24-Mar-2026 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM8262MMX/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0 LM8262MMX/NOPB VSSOP DGK 8 3500 366.0 364.0 50.0 Pack Materials-Page 2

www.ti.com PACKAGE OUTLINE C 6X 0.65 1.95 8X 0.38 0.25 5.05

4.75 TYP

0.15 0.05 0.25 GAGE PLANE 0 -8

1.1 MAX

0.23 0.13 B 3.1 2.9 NOTE 4 A 3.1 2.9 NOTE 3 0.7 0.4 VSSOP - 1.1 mm max heightDGK0008A SMALL OUTLINE PACKAGE 4214862/A 04/2023

0.13 C A B

0.1 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-187. PowerPAD is a trademark of Texas Instruments. A 20 DETAIL A TYPICAL SCALE 4.000

www.ti.com EXAMPLE BOARD LAYOUT

0.05 MAX

0.05 MIN

8X (1.4) 8X (0.45) 6X (0.65) (4.4) (R0.05) TYP VSSOP - 1.1 mm max heightDGK0008A SMALL OUTLINE PACKAGE 4214862/A 04/2023 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. 8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. 9. Size of metal pad may vary due to creepage requirement. TM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 15X SYMM SYMM SEE DETAILS 15.000 METALSOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METALEXPOSED METAL SOLDER MASK DETAILS NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN 8X (1.4) 8X (0.45) 6X (0.65) (4.4) (R0.05) TYP VSSOP - 1.1 mm max heightDGK0008A SMALL OUTLINE PACKAGE 4214862/A 04/2023 NOTES: (continued) 11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 12. Board assembly site may have different recommendations for stencil design. TM SOLDER PASTE EXAMPLE SCALE: 15X SYMM SYMM

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