LM70860RRXR.A

LM70840 TI

Document overview

• Manufacturer or author: Provided By www.digicamel.com(free datasheet download site)
• PDF pages: 55

Technical content

LM708x0 80V, 8A/6A/4A, High-Efficiency Buck Converters Designed for High Power Density

1 Features

• Functional Safety-Capable – Documentation available to aid functional safety system design
• Synchronous DC/DC converter with a versatile buck controller and robust power MOSFETs – Wide input voltage range: 4.5V to 80V – Shutdown mode current: 2.3µA – No-load IQ regulating 48V to 5V: 8.2µA – 1% accurate, fixed 3.3V, 5V, 12V, or adjustable outputs from 0.8V to 55V – Dual-phase operation enabling output currents up to 16A
• Designed for low EMI requirements – Facilitates CISPR 11 Class B compliance – Pin-selectable ±8% dual-random spread spectrum reduces peak emissions – Switching frequency: 200kHz to 2.2MHz – Pin-configurable AUTO or FPWM operation
• Inherent protection features for robust design – Internal hiccup-mode overcurrent protection – Enable, power good, and thermal shutdown – Internal or external loop compensation
• 6mm × 6mm thermally optimized, RoHS compliant, QFN-29 package with Pb-free plating
• Create a custom design using the LM708x0 with the WEBENCH® Power Designer

2 Applications

• Industrial: motor drives (Servo/AC), factory automation, off-highway vehicles and eBikes
• Communications: WLAN, AAS and RRU

3 Description

The LM708x0 is a family of low-IQ, wide-V IN synchronous buck converters designed for an input voltage range of 4.5V to 80V and delivering up to 8A of output current at fixed output voltages of 3.3V, 5V, 12V, or an adjustable output. The LM708x0 uses a peak current-mode control architecture for easy loop compensation, fast transient response, and excellent load and line regulation. A pair of LM708x0 converters can be set up in an interleaved mode (paralleled outputs) with accurate current sharing for applications requiring up to 16A of output current. The LM708x0 features a unique Dual Random Spread Spectrum (DRSS) function that combines low-frequency triangular and high-frequency cycle- by-cycle random modulations for improved EMI performance across a wide range of frequency bands. Device Information PART NUMBER PACKAGE(1) PACKAGE SIZE(2) LM70880 RRX (VQFN, 29) 6mm × 6mmLM70860 LM70840 (1) For more information, see Mechanical, Packaging, and Orderable Information. (2) The package size (length × width) is a nominal value and includes pins, where applicable. VOUT VIN PFM/SYNCIN AGND RT VOUT ISNS+ SW CBOOT EN/UVLO CONFIG VCC PG/SYNCOUT VIN BIAS PGND FB RRT CVDDA CVCC CBOOT CIN COUT RS LO VDDA EXTCOMP RCNFG RC CC Typical Application Circuit L o a d ( A ) Efficiency (%) 0 1 2 3 4 5 6 7 8 8 0 8 2 8 4 8 6 8 8 9 0 9 2 9 4 9 6 9 8 1 0 0 V I N = 2 4 V V I N = 3 6 V V I N = 4 8 V Typical Efficiency VOUT = 12V, fSW = 400kHz LM70840, LM70860, LM70880 SNVSCD3 – SEPTEMBER 2024 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

Additional features of the LM708x0 include user-selectable diode emulation for lower current consumption at light-load conditions, open-drain Power-Good flag for fault reporting and output monitoring, precision enable input, monotonic start-up into prebiased load, integrated VCC bias supply regulator, internal 2.8ms soft-start time, and thermal shutdown protection with automatic recovery. The LM708x0 converter comes in a 6mm × 6mm thermally-optimized, 29-pin QFN package. The three die-attach pads (VIN, SW, and PGND) improve thermal performance and board level reliability (BLR). LM70840, LM70860, LM70880 SNVSCD3 – SEPTEMBER 2024 www.ti.com

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10 Mechanical, Packaging, and Orderable

4 Pin Configuration and Functions

Figure 4-1. RRX Package, 29-Pin VQFN (Top View) Table 4-1. Pin Functions PIN TYPE(1) DESCRIPTION NO. NAME 1 VIN4 P Converter input pins to the drain of the high-side power MOSFET and the VCC regulator (VIN6). Connect to the input supply and the input filter capacitors. The path from the VIN pin to the input capacitors must be as short as possible.

2 VIN5 P

3 VIN6 P

4 CBOOT P

High-side driver supply for the bootstrap gate drive. Connect a 47nF bootstrap capacitor between the CBOOT and SW4 pins. If VCC = 8V is selected, add a 1Ω resistor in series with the bootstrap capacitor. www.ti.com LM70840, LM70860, LM70880 SNVSCD3 – SEPTEMBER 2024 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: LM70840 LM70860 LM70880

Table 4-1. Pin Functions (continued) PIN TYPE(1) DESCRIPTION NO. NAME

5 SW4 P

Switch pin. Connect a 47nF bootstrap capacitor between the CBOOT and SW4 pins. This pin is internally connected to the switch pins SW1, SW2, and SW3. There is no need to route this pin to the other switch pins on a PCB.

6 BIAS P

Optional input for an external bias supply. If configured for 3.3V fixed VOUT, connect the BIAS pin to an external bias supply from 5V to 30V. If configured for 5V fixed VOUT, connect the BIAS pin to the VOUT node or an external bias supply from 5V to 30V. If configured for 12V fixed or an adjustable VOUT, connect the BIAS pin to the VOUT node or an external bias supply from 10V to 30V. If the output voltage is above 30V and no external supply is used, tie the BIAS pin to GND.

7 PG /

Power-Good / Sync Output pin. This pin is an open-collector output that goes low if VOUT is outside of the specified regulation window. PG / SYNCOUT can also be used as a synchronization output to synchronize the internal oscillator of the secondary device to the oscillator of the primary device.

8 PFM /

PFM / FPWM mode selection and synchronization input pin. Connect the PFM / SYNCIN pin to VDDA to enable diode emulation mode. Connect the PFM / SYNCIN pin to AGND to operate in Forced PWM (FPWM) mode with continuous conduction at light loads. The PFM / SYNCIN pin can also be used as a synchronization input to synchronize the internal oscillator to an external clock.

9 EN / UVLO I

Enable / undervoltage lockout pin. Drive this pin high / low to enable / disable the device. If the enable function is not needed, tie this pin to VIN. Connect an external resistor divider network to set UVLO threshold. 10 NC P No connect pin. Leave floating or tie to GND. 11 ISNS+ I Current sense amplifier input. Connect the ISNS+ pin to the inductor side of the external current sense resistor using a low-current Kelvin connection. 12 VOUT I Output voltage sense and the current sense amplifier input. Connect the VOUT pin to the output side of the respective current sense resistor. 13 CONFIG I Configuration pin. Connect a resistor to ground to set primary/secondary, spread spectrum enable/ disable, or interleaved operation. 14 RT I Frequency programming pin. A resistor from RT to AGND sets the oscillator frequency between 200kHz and 2.2MHz.

15 EXTCOMP O

External compensation pin. This pin is the output of the transconductance amplifier. If used, connect the compensation network from the EXTCOMP pin to AGND. Connect a 100kΩ resistor between the EXTCOMP and VDDA pins to use the internal compensation.

16 FB I

Feedback pin. Connect a resistor between FB and VDDA to set the output voltage to 3.3V, 5V or 12V. Connect a resistor divider network from VOUT to FB to set the output voltage level between 0.8V to 55V. The voltage reference setpoint is 0.8V. 17 AGND G Analog ground pin. Ground return for the internal voltage reference and analog circuits. 18 VDDA P Internal analog bias regulator output pin. Connect a 0.1μF ceramic decoupling capacitor from VDDA to AGND as close as possible to the pins. 19 VCC P VCC bias supply pin. Connect a 4.7μF ceramic capacitors between VCC and PGND as close as possible to the pins. 20 SW1 P Switch pins. These pins form a switching node that is internally connected to the source terminal of the buck switch (high-side MOSFET) and the drain terminal of the synchronous rectifier (low-side MOSFET). Connect to the buck inductor.

21 SW2 P

22 SW3 P

23 PGND1 G

Power ground pins. These pins form a power ground node for the low-side MOSFET. Connect to the system ground on a PCB. Path to CIN must be as short as possible.

24 PGND2 G

25 PGND3 G

26 PGND4 G

27 VIN1 P Converter input pins to the drain of the high-side power MOSFET. Connect to the input supply and the input filter capacitors. The path from the VIN pin to the input capacitors must be as short as possible.28 VIN2 P

29 VIN3 P

30 PGND G Controller power ground pin. Connect to the system ground using multiple vias. (1) P = Power, G = Ground, I = Input, O = Output. LM70840, LM70860, LM70880 SNVSCD3 – SEPTEMBER 2024 www.ti.com

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5 Specifications

5.1 Absolute Maximum Ratings

Over the recommended operating junction temperature temperature range (unless otherwise noted) (1) MIN MAX UNIT Pin voltage VIN to PGND –0.3 87.5 V Pin voltage SW to PGND –0.3 87.5 V Pin voltage SW to PGND transient < 20ns –5 90 V Pin voltage CBOOT to SW –0.3 10 V Pin voltage CBOOT to SW, transient < 20ns –2 V Pin voltage EN/UVLO to PGND –0.3 87.5 V Pin voltage VDDA, PG/SYNCOUT, FB, CONFIG, PFM/SYNCIN, RT, EXTCOMP to AGND –0.3 6.5 V Pin voltage VCC to AGND –0.3 10 V Pin voltage BIAS to AGND –0.3 32 V Pin voltage VOUT, ISNS+ to PGND –0.3 60 V Pin voltage VOUT to ISNS+ –0.3 0.3 V Pin voltage PGND to AGND –0.3 0.3 V TJ Operating junction temperature –40 150 °C Tstg Storage temperature –55 150 °C (1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

5.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000 V Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002 (2) ±750 (1) JEDEC document JEP155 states that 500V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250V CDM allows safe manufacturing with a standard ESD control process.

5.3 Recommended Operating Conditions

Over operating junction temperature range (unless otherwise noted) MIN NOM MAX UNIT VIN Input supply voltage range 4.5 80 V VOUT Output voltage range 0.8 55 V Pin voltage VIN, EN/UVLO, SW to PGND –0.3 80 V Pin voltage CBOOT to SW –0.3 8 8.5 V Pin voltage FB, PFM/SYNCIN, PG/SYNCOUT to AGND –0.3 5.25 V Pin voltage VDDA to PGND –0.3 5 5.25 V Pin voltage VCC to PGND (Fixed 3.3V or 5V output) –0.3 5 5.25 V Pin voltage VCC to PGND –0.3 8 8.5 V Pin voltage BIAS to PGND –0.3 30 V Pin voltage VOUT, ISNS+ to PGND –0.3 55 V PGND to AGND –0.3 0.3 V IOUT Output current range, LM70880 0 8 A IOUT Output current range, LM70860 0 6 A IOUT Output current range, LM70840 0 4 A RS Sense resistor, LM70880 5 mΩ www.ti.com LM70840, LM70860, LM70880 SNVSCD3 – SEPTEMBER 2024 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: LM70840 LM70860 LM70880

5.3 Recommended Operating Conditions (continued)

Over operating junction temperature range (unless otherwise noted) MIN NOM MAX UNIT RS Sense resistor, LM70860 6 mΩ RS Sense resistor, LM70840 9 mΩ TJ Operating junction temperature –40 150 °C

5.4 Thermal Information

THERMAL METRIC(1) LM708x0 UNITJESD 51-7 EVM

29 PINS 29 PINS

RθJA Junction-to-ambient thermal resistance 33.5(2) 18.6(3) °C/W RθJC(top) Junction-to-case (top) thermal resistance 31.6 (4) °C/W RθJB Junction-to-board thermal resistance 11.7 (4) °C/W ψJT Junction-to-top characterization parameter (Tcase-center) 11.5 7.2 °C/W ψJT Junction-to-top characterization parameter (Tcase-max) – 0.8 °C/W ψJB Junction-to-board characterization parameter 11.6 6.3 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application note. (2) The value of RΘJA given in this table is only valid for comparison with other packages and cannot be used for design purposes. These values were calculated in accordance with JESD 51-7, and simulated with a 4-layer JEDEC board. They do not represent the performance obtained in an actual application. For thermal design information please see the Maximum Ambient Temperature section. (3) Refer to the EVM User's Guide for board layout and additional information. For thermal design information please see the Maximum Ambient Temperature section. (4) Not applicable to an EVM.

5.5 Electrical Characteristics

TJ = –40°C to +150°C. Typical values are at TJ = 25°C and VIN = 12V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY (VIN) IQ-SD VIN shutdown current Non-switching, VEN = 0V, VFB = VREF + 50mV, TJ = 25°C 2.3 4 µA Non-switching, VEN = 0V, VFB = VREF + 50mV, TJ = 125°C 2.3 8 µA IQ-SBY VIN standby current (1) Non-switching, 0.5V ≤ VEN ≤ 1V, External COMP, RCONFIG = 29.4kΩ 350 µA IQ-SLEEP1-48V VIN sleep current, 3.3V fixed output, no load VEN = 5V, VIN = 48V, VBIAS = 0V, VVOUT = 3.3V, no-load, non-switching, VPFM/SYNCIN = 5V, RFB = 0Ω to VDDA 14.4 µA IQ-SLEEP2-48V VIN sleep current, 5V fixed output, no load VEN = 5V, VIN = 48V, VBIAS = 5V, VVOUT = 5V, no-load, non-switching, VPFM/SYNCIN = 5V, RFB = 24.9kΩ to VDDA 6.9 30 µA IQ-SLEEP3-48V VIN sleep current, 12V fixed output, no load VEN = 5V, VIN = 48V, VBIAS = 12V, VVOUT = 12V, no-load, non-switching, VPFM/SYNCIN = 5V, RFB = 49.9kΩ to VDDA 23 µA ENABLE (EN / UVLO) VSBY-TH Shutdown-to-standby threshold voltage VEN/UVLO rising 0.55 V VEN-TH Enable voltage rising threshold VEN/UVLO rising 0.95 1.0 1.05 V VEN-HYS Enable voltage hysteresis 0.1 V INTERNAL LDO (VCC) VVCC1 VCC regulation voltage IVCC = 50mA, RFB = 0Ω or 24.9kΩ 4.5 5 5.5 V VVCC2 VCC regulation voltage IVCC = 50mA 7 8 8.5 V INTERNAL LDO (VDDA) VVDDA VDDA regulation voltage IVDD = 5mA 4.75 5 5.25 V LM70840, LM70860, LM70880 SNVSCD3 – SEPTEMBER 2024 www.ti.com

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5.5 Electrical Characteristics (continued)

TJ = –40°C to +150°C. Typical values are at TJ = 25°C and VIN = 12V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IVDDA-CL VDDA short-circuit current limit VDDA = 4.5V 10 15 20 mA EXTERNAL BIAS (BIAS) VBIAS-TH1 VIN to VBIAS switchover rising threshold, 12V fixed or adjustable output RFB = 49.9kΩ 8.8 9.1 9.3 V VBIAS-TH2 VIN to VBIAS switchover rising threshold, VBIAS-HYS VIN to VBIAS switchover hysteresis 550 mV REFERENCE VOLTAGE (FB) VFB Regulated FB voltage 794 800 806 mV OUTPUT VOLTAGE (VOUT) VOUT1 3.3V output voltage setpoint RFB = 0Ω 3.267 3.3 3.333 V VOUT2 5V output voltage setpoint RFB = 24.9kΩ 4.95 5.0 5.05 V VOUT3 12V output voltage setpoint RFB = 49.9kΩ 11.88 12 12.12 V ERROR AMPLIFIER (EXTCOMP) gm-EXTERNAL EA transconductance external compensation FB to COMP 970 1200 µS gm-NTERNAL EA transconductance internal compensation (1) FB to COMP, EXTCOMP 100kΩ to VDDA 30 µS IFB Error amplifier input bias current 75 nA VCOMP-CLAMP COMP clamp voltage VFB = 0V 2.1 V ICOMP-SRC EA source current VCOMP = 1V, VFB = 0.65V 170 µA ICOMP-SINK EA sink current VCOMP = 1V, VFB = 0.95V 170 µA PULSE FREQUENCY MODULATION (PFM/SYNCIN) VIL-SYNCIN PFM/SYNCIN input threshold low 0.8 V VIH(SYNCIN) PFM/SYNCIN input threshold high 1.17 V fSYNC1 Synchronization frequency range (220kHz) RRT = 100kΩ, ±20 % of the nominal oscillator frequency 176 264 kHz fSYNC2 Synchronization frequency range (2.2MHz) RRT = 10kΩ, ±20 % of the nominal oscillator frequency 1.76 2.64 MHz tSYNC-TON-MIN Minimum positive pulse width of external synchronization signal RRT = 10kΩ 20 ns tSYNC-TOFF-MIN Minimum negative pulse width of external synchronization signal RRT = 10kΩ 200 ns tSYNCIN-SW Delay from PFM falling edge to SW rising edge (1) 35 ns tPFM-FILTER SYNCIN to PFM mode 15 75 µs DUAL RANDOM SPREAD SPECTRUM (DRSS) ΔfC Distance from the switching frequency 8 % fm Modulation frequency 10 kHz SWITCHING FREQUENCY (SW) fSW1 Switching frequency 1 RRT = 100kΩ to AGND 200 220 240 kHz fSW2 Switching frequency 2 RRT = 49.9kΩ to AGND 400 440 480 kHz fSW3 Switching frequency 3 RRT = 22.1kΩ to AGND 0.85 0.95 1.05 MHz fSW4 Switching frequency 4 RRT = 9.09kΩ to AGND 2 2.2 2.4 MHz tON-MIN Minimum on-time(1) 25 ns tOFF-MIN Minimum off-time 88 126 ns POWER GOOD (PG) VPG-UV Power-Good UV trip level Falling with respect to the regulated voltage 90 % 92 % 94% VPG-OV Power-Good OV trip level Rising with respect to the regulation voltage 108 % 110 % 112 % VPG-UV-HYST Power-Good UV hysteresis Falling with respect to the regulated output 3.4 % www.ti.com LM70840, LM70860, LM70880 SNVSCD3 – SEPTEMBER 2024 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: LM70840 LM70860 LM70880

TJ = –40°C to +150°C. Typical values are at TJ = 25°C and VIN = 12V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VPG-OV-HYST Power-Good OV hysteresis Raising with respect to the regulated output 3.4 % tPG-DEGLITCH Power-Good deglitch filter time VOUT falling or rising 25 µs VOL-PG Power-Good voltage Open collector, IPG = 2mA 0.4 V SYNCHRONIZATION OUTPUT (SYNCOUT) VSYNCOUT-LTH SYNCOUT low state voltage threshold RCONFIG = 54.9kΩ or 71.5kΩ, ISYNCOUT = 2mA 0.4 V VSYNCOUT-HTH SYNCOUT high state voltage threshold RCONFIG = 54.9kΩ or 71.5kΩ, ISYNCOUT = −2mA 2.0 V STARTUP (SOFT START) tSS Internal fixed soft-start time 1.9 2.8 4.4 ms INTERNAL HICCUP MODE tHIC-DLY HICCUP mode activation delay VISNS+ − VVOUT > 60mV 512 CYCLES tHIC-DURATION HICCUP mode fault duration VISNS+ − VVOUT > 60mV 16384 CYCLES OVERCURRENT PROTECTION (OCP) VCS-TH CS voltage threshold Measured from ISNS+ to VOUT 50 56 62 mV tDELAY-CS CS delay to output 75 ns GCS CS amplifier gain (1) 10 V/V IBIAS-CS CS amplifier input bias current (1) 0.35 µA VCS-TH-NEG CS negative voltage threshold 30 mV THERMAL SHUTDOWN (TSD) TJ-SD Thermal shutdown threshold (1) Temperature rising 175 °C TJ-HYS Thermal shutdown hysteresis (1) 15 °C (1) Specified by design. Not production tested. LM70840, LM70860, LM70880 SNVSCD3 – SEPTEMBER 2024 www.ti.com

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5.6 Typical Characteristics

VIN = 12V, TJ = 25°C, unless otherwise stated. Load (A) Efficiency (%) 0 1 2 3 4 5 6 7 8 100 VIN = 8V VIN = 12V VIN = 24V VIN = 48V VIN = 60V 5V output Figure 5-1. Efficiency vs IOUT Load (A) Efficiency (%) 0.001 0.01 0.1 1 8 100 VIN = 8V VIN = 12V VIN = 24V VIN = 48V VIN = 60V 5V output Figure 5-2. Efficiency vs IOUT, Log Scale Load (A) Efficiency (%) 0 1 2 3 4 5 6 7 8 100 VIN = 15V VIN = 24V VIN = 36V VIN = 48V VIN = 60V 12V output Figure 5-3. Efficiency vs IOUT Load (A) Efficiency (%) 0.001 0.01 0.1 1 8 100 VIN = 15V VIN = 24V VIN = 36V VIN = 48V VIN = 60V 12V output Figure 5-4. Efficiency vs IOUT, Log Scale VOUT 500 mV/DIV IOUT 2 A/DIV 200 µs/DIV VIN = 48V, VOUT = 12V FPWM Figure 5-5. Load Transient, 0A to 4A VOUT 500 mV/DIV IOUT 2 A/DIV 200 µs/DIV VIN = 48V, VOUT = 12V FPWM Figure 5-6. Load Transient, 4A to 8A www.ti.com LM70840, LM70860, LM70880 SNVSCD3 – SEPTEMBER 2024 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: LM70840 LM70860 LM70880

5.6 Typical Characteristics (continued)

VIN = 12V, TJ = 25°C, unless otherwise stated. V I N - I n p u t V o l t a g e ( V ) ISTD- Shutdown Current (A) 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 1 0 1 5 2 0 2 5 3 0 T A = 2 5  C T A = 1 5 0  C VEN = 0V Figure 5-7. Shutdown Current vs Input Voltage V I N - I n p u t V o l t a g e IQ- No Load Input Current (A) 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 2 0 2 5 3 0 3 5 4 0 4 5 5 0 5 5 6 0 1 2 V F i x e d , 4 0 0 k H z , V B I A S = V O U T VEN = VIN Figure 5-8. 12V Fixed Output No-Load Active Current vs Temperature V I N - I n p u t V o l t a g e IQ- No Load Input Current (A) 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 1 0 1 5 2 0 2 5 3 0 3 5 4 0 4 5

5 V F i x e d , 4 0 0 k H z , V B I A S = V V O U T

Figure 5-9. 5V Fixed Output No-Load Active Current vs Temperature Temperature (C) Minimum tON (ns) -40 -20 0 20 40 60 80 100 120 140 160 40 Figure 5-10. Minimum On-Time vs Temperature LM70840, LM70860, LM70880 SNVSCD3 – SEPTEMBER 2024 www.ti.com

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6 Detailed Description

6.1 Overview

The LM708x0 is a family of multi-die, DC/DC converters that features high-side and low-side power MOSFETs and a versatile buck controller with all functions necessary to implement a high-efficiency synchronous buck regulator operating over a wide input voltage range from 4.5V to 80V. The LM708x0 is configured to provide a fixed 3.3V, 5V, or a 12V output, or an adjustable output between 0.8V and 55V. Current-mode control using a shunt resistor provides inherent line feedforward, cycle-by-cycle peak current limiting, and easy loop compensation. The device also supports a wide duty cycle range for high input voltage and low dropout applications as well as when a high-voltage conversion ratio (for example, 10-to-1) is required. The oscillator frequency is user-programmable between 200kHz to 2.2MHz. The LM708x0 can be synchronized to an external clock applied on the PFM / SYNC pin. An external bias supply can be connected to the BIAS pin to maximize efficiency in high input voltage applications. A user-selectable diode emulation feature enables discontinuous conduction mode (DCM) operation to further improve efficiency and reduce power dissipation during light-load conditions. Fault protection features include current limiting, thermal shutdown, UVLO and remote shutdown capability. The LM708x0 incorporates features to simplify the compliance with various EMI standards including CISPR 11 Class B that defines industrial EMI requirements. Dual Random Spread Spectrum (DRSS) technique reduces the peak harmonic EMI signature. LM708x0 is provided in a 29-pin QFN package with the exposed VIN, SW, and PGND pads to maximize thermal dissipation. www.ti.com LM70840, LM70860, LM70880 SNVSCD3 – SEPTEMBER 2024 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: LM70840 LM70860 LM70880

6.2 Functional Block Diagram

512 CYCLES

• CBOOT UVLO PG DELAY 25s FB DECODER/ MUX 150mV Q Q R S CBOOT CONFIG PFM/SYNCIN RT SW SW VCCPG/SYNCOUT EXTCOMP FB VOUT ISNS+ EN/UVLO AGND VDDA VCC BIAS VIN DEM/FPWM VCC SOFT-START DUAL RANDOM SPREAD SPECTURM (DRSS) PGO PGUV 0.735V DRSS ENABLE MODE GAIN = 10 VCC (5V or 8V) ILIMHICCUP 3.3V 12V LEVEL SHIFT ADAPTIVE DEADTIME SYNCOUT CLK FUNCTION SECONDARY INTERLEAVE COMP/ENABLE EXTERNAL EA gm 1200µS VREF INTERNAL EA gm 30µS 0.880V STANDBY DEM/FPWM HICCUP PWM CLK 56mV CURRENT LIMIT ILIM SLOPE COMP RAMP VIN PGND ZCD -5mV CONFIG DECODER VDDA LDO VDDA (5V) SYNCOUT FUNCTION LM70840, LM70860, LM70880 SNVSCD3 – SEPTEMBER 2024 www.ti.com

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6.3 Feature Description

6.3.1 Input Voltage Range (VIN)

The LM708x0 operational input voltage range is from 4.5V to 80V. The device is intended for step-down conversions from 12V, 24V and 48V supply rails. The LM708x0 uses internal LDOs to provide an 8V or 5V VCC bias rail and a 5V VDDA rail for the gate drive and control circuits. In high input voltage applications, make sure that the VIN and SW pins do not exceed the absolute maximum voltage rating of 87.5V during line or load transient events. Voltage excursions that exceed the absolute maximum ratings of these pins can damage the IC. Follow PCB board layout recommendations and use high-quality input bypass capacitors to minimize voltage overshoot and ringing. As VIN approaches V OUT, the LM708x0 skips t OFF cycles to allow the controller to extend the duty cycle up to approximately 99%. Refer to Figure 6-1. When in dropout, the output voltage tracks the input voltage and the peak current mode control is open loop. As a result, larger output voltage perturbations due to line and load transients are possible. Additional output capacitance and more aggressive external compensation can improve the output response. Use Equation 1 to calculate when the LM708x0 enters dropout mode. V IN = V O UT × t P t P − t O F F (1)

• tP is the oscillator period
• tOFF is the minimum off time, typical 88ns VOUT SW Low Drop-out ModePWM Mode Approximately 99% Duty Cycle VIN one tOFF skip two tOFF skip three tOFF skip up to fifteen tOFF skip up to fifteen tOFF skip Figure 6-1. Dropout Mode Operation

6.3.2 High-Voltage Bias Supply Regulator (VCC, BIAS, VDDA)

The LM708x0 contains an internal high-voltage VCC bias regulator that provides the bias supply for the gate drivers for the power MOSFETs. The input voltage pin (VIN) can be connected directly to an input voltage source up to 80V. However, when the input voltage is below the VCC setpoint level, the VCC voltage tracks VIN minus a small voltage drop. If configured for a 3.3V fixed output, the VCC bias regulator output voltage is 5V to allow connecting the BIAS pin to an external supply from 5V to 30V. Similarly, if configured for a 5V fixed output, the VCC bias regulator output voltage is 5V to allow connecting the BIAS pin to the VOUT node or an external supply from 5V to 30V. For a 12V fixed output or an adjustable output, the VCC bias regulator output voltage is 8V to allow connecting the BIAS pin to the VOUT node or an external supply from 10V to 30V. At power up, the VCC regulator sources current into the capacitor connected to the VCC pin (if EN pin is connected to a voltage greater than 2V). When the VCC voltage exceeds 4.3V, the output is enabled and the www.ti.com LM70840, LM70860, LM70880 SNVSCD3 – SEPTEMBER 2024 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: LM70840 LM70860 LM70880

soft-start sequence begins. The output remains active unless the VCC voltage falls below the VCC falling UVLO threshold of 4V (typical) or the EN is driven below 900mV (typical). TI recommends that a 4.7µF capacitor is connected from the VCC pin to PGND and placed as close as possible to the device pins. Internal power dissipation of the VCC regulator can be minimized by connecting the BIAS pin to VOUT or an external supply. If the BIAS voltage is above 9.1V (typical), the input to the VCC regulator switches over from VIN to BIAS. If configured for a 3.3V fixed or a 5V fixed output, the switchover happens at 4.6V (typical). Tie the BIAS pin to AGND if unused. Never connect the BIAS pin to a voltage greater than 32V. If an external supply is connected to the BIAS pin to power the LM708x0, VIN must be greater than the external bias voltage under all conditions to avoid damage to the device. An internal 5V linear regulator generates the VDDA bias supply from the VCC bias supply. Bypass VDDA with a 100nF ceramic capacitor to achieve a low-noise internal bias rail. Normally VDDA is 5V, however when configured for a fixed 3.3V or a fixed 5V VOUT, the VDDA regulator is disabled in sleep mode while the circuitry, normally powered by the VDDA, is switched over to VOUT as the power source.

6.3.3 Enable (EN)

The EN/UVLO pin can be connected to a voltage as high as 80V. The LM708x0 has a precision enable. When the EN pin is greater than 1V, the output is enabled. If the EN pin is pulled below 0.55V (typical), the LM708x0 is in shutdown with an I Q of 2.3 μA (typical) current draw from V IN. When the enable voltage is between 0.55V (typical) and 1V (typical), the LM708x0 is in standby mode. When in standby mode, the VCC regulator is enabled, the device is not switching, and the I Q current is 350 μA (typical). Users can also enable the LM708x0 with standard CMOS logic drivers. A voltage greater than 2.0V enables the LM708x0, and a voltage less than 0.4V disables the LM708x0. However, many applications benefit from using a resistor divider R UV1 and RUV2 as shown in Figure 6-2 to establish a precision UVLO threshold. TI recommends setting the input voltage turn-on threshold at 4.5V or higher when the rise time of the input supply to the LM708x0 is significantly slower than the internal soft-start time. TI does not recommend leaving the EN pin floating. Use Equation 2 to calculate the UVLO resistors given the required input turn-on voltage. The EN voltage hysteresis, V EN-HYS, is 100mV or 10% of the EN voltage rising threshold, V EN-TH, therefore the input turn-off voltage is 90% of the input turn-on voltage. R UV1 = V IN on V EN − TH – 1 × R UV2 (2) LM708X0 EN/UVLO 1VRUV2 RUV1 1910 Enable Comparator Remote Shutdown VIN Figure 6-2. Programmable Input Voltage UVLO Turn-on and Turn-off

6.3.4 Power-Good Monitor (PG)

The LM708x0 includes an output voltage monitoring signal for V OUT to simplify sequencing and supervision. The power-good function can be used to enable circuits that are supplied by the corresponding voltage rail or to turn on sequenced supplies. The power-good output (PG) switches to a high impedance open-drain state when the LM70840, LM70860, LM70880 SNVSCD3 – SEPTEMBER 2024 www.ti.com

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output voltage is in regulation. The PG output switches low when the corresponding output voltage drops below the lower power-good threshold (92% typical) or rises above the upper power-good threshold (110% typical). If the upper PG threshold is exceeded when operating in standalone configuration mode, the high-side switch is turned off immediately and the low-side switch is turn on to prevent overvoltage and discharge the output. A 25µs deglitch filter prevents false tripping of the power-good signal during transients. TI recommends a pull-up resistor of 100kΩ (typical) from PG to the relevant logic rail. PG is asserted low during soft-start and when the buck regulator is disabled via the EN input. When the LM708x0 is configured as a primary device, the PG pin is converted to a synchronization clock output for the secondary device. The synchronization signal has logic levels and is 180° out of phase (lagging) with the internal high-side gate driver output of the primary device.

6.3.5 Switching Frequency (RT)

The LM708x0 oscillator is programmed by a resistor between RT and AGND to set an oscillator frequency between 200kHz and 2.2MHz. Calculate the RT resistance for a given switching frequency using Equation 3. R RT k Ω = 10 6 F SW k Hz − 53 45 (3) Under low V IN conditions when the high-side MOSFET on-time exceeds the programmed oscillator period, the LM708x0 extends the switching period of that channel until the PWM latch is reset by the current sense ramp exceeding the controller compensation voltage. In such an event, the oscillators operate independently and asynchronously until the channel can maintain output regulation at the programmed frequency. The approximate input voltage level where this occurs is given by Equation 4, where tSW is the switching period and tOFF(min) is the minimum off-time of 88ns. V IN min = V OUT × t SW t SW − t O F F min (4)

6.3.6 Dual Random Spread Spectrum (DRSS)

The LM708x0 provides a Dual Random Spread Spectrum (DRSS) function which reduces the EMI of the power supply over a wide frequency range. The DRSS function combines a low-frequency triangular modulation profile with a high frequency cycle-by-cycle random modulation profile. The low frequency triangular modulation improves performance in the lower radio frequency bands, while the high frequency random modulation improves performance in the higher radio frequency bands. Spread spectrum works by converting a narrowband signal into a wideband signal which spreads the energy over multiple frequencies. Industry standards require different spectrum analyzer resolution bandwidth (RBW) settings for different frequency bands. The RBW has an impact on the spread spectrum performance. For example, the CISPR-25 requires 9kHz RBW for the 150kHz to 30MHz frequency band. For frequencies greater than 30MHz, the required RBW is 120kHz. DRSS is able to simultaneously improve the EMI performance in the high and low RBWs with the low-frequency triangular modulation and high-frequency cycle-by-cycle random modulation as shown in Figure 6-3. In the low-frequency band (150kHz -30MHz), the DRSS function can reduce the conducted emissions by as much as 15dB μV, and in the high-frequency band (30MHz - 108MHz) by as much as 5dBμV. The DRSS function can be enabled by connecting either a 41.2k Ω or 71.5k Ω resistor from the CONFIG pin to AGND. The DRSS function is disabled when an external clock is applied to the PFM / SYNCIN pin. www.ti.com LM70840, LM70860, LM70880 SNVSCD3 – SEPTEMBER 2024 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: LM70840 LM70860 LM70880

Figure 6-3. Dual Random Spread Spectrum Implementation

6.3.7 Soft Start

The LM708x0 has an internal 2.8ms soft-start timer (typical). The soft-start feature allows the regulator to gradually reach the steady-state operating point, thus reducing start-up stresses and surges.

6.3.8 Output Voltage Setpoint (FB)

The LM708x0 outputs can be independently configured for one of the three fixed output voltages with no external feedback resistors, or adjusted to the desired voltage using an external resistor divider network. The output can be configured as a 3.3V output by connecting the FB pin to VDDA, a 5V output by connecting FB through a 24.9k Ω resistor to VDDA, or 12V by connecting the FB pin through a 49.9k Ω resistor to VDDA. With the output voltage selection, the VCC bias regulator output level is selected as well as shown in Table 6-1. The configuration settings are latched and cannot be changed until the input voltage to the LM708x0 is recycled. Table 6-1. Output Voltage and VCC Voltage Selection FB Pin Output Voltage VCC Voltage Short to VDDA 3.3V 5V 24.9kΩ to VDDA 5.0V 5V 49.9kΩ to VDDA 12V 8V Resistor divider to VOUT 0.8V to 55V 8V Alternatively, the output voltage can be set using external resistive dividers from the output to the FB pin. The output voltage adjustment range is between 0.8V and 55V. The voltage reference setpoint is 0.8V (V REF). Use Equation 5 to calculate the upper and lower feedback resistors, designated RFB1 and RFB2 respectively. R FB1 = V OUT V REF − 1 × R F B 2 (5) The recommended starting value for RFB2 is between 10kΩ and 20kΩ. If a low I Q mode is required, be careful when selecting the external resistors. The extra current drawn from the external divider is added to the LM708x0 IQ-SLEEP current. The divider current reflected to VIN is divided down by the ratio of VOUT/VIN.

6.3.9 Minimum Controllable On-Time

There are two limitations to the minimum output voltage adjustment range: the LM708x0 voltage reference of 0.8V and the minimum controllable switch-node pulse width, tON(min). tON(min) effectively limits the voltage step-down conversion ratio V OUT/VIN at a given switching frequency. For fixed-frequency PWM operation, the voltage conversion ratio must satisfy Equation 6. V OUT V IN > t ON min × F SW (6) LM70840, LM70860, LM70880 SNVSCD3 – SEPTEMBER 2024 www.ti.com

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• tON(min) is 25ns (typical).
• FSW is the switching frequency. If the desired voltage conversion ratio does not meet the above condition, the LM708x0 transitions from a fixed switching frequency operation mode to a pulse-skipping mode to maintain output voltage regulation. For wide VIN applications and low output voltages, an alternative is to reduce the LM708x0 switching frequency to meet the requirement of Equation 6.

6.3.10 Error Amplifier and PWM Comparator (FB, EXTCOMP)

The LM708x0 has a high-gain transconductance amplifier that generates an error current proportional to the difference between the feedback voltage and an internal precision reference (0.8V). The control loop compensation can be configured in two ways. The first is using the internal compensation amplifier, which has a gain of 30µS. To use the internal compensation network connect the EXTCOMP through a 100k Ω resistor to the VDDA pin. If a 100kΩ resistor is not detected, the LM708x0 defaults to the external loop compensation network. The external loop compensation network is latched and cannot be re-configured easily. When using the external compensation network, the gain of the transconductance amplifier is 1200µS. Typically if higher performance is required to meet a stringent transient response requirement, TI advises to use external compensation configuration. To re-configure the compensation (internal or external) power must be recycled and VCC must be allowed to drop below the VCCUVLO threshold. TI generally recommends a type-II compensation network for peak current-mode control. If no external compensation impedance is detected on power up, the fixed internal compensation network is used.

6.3.11 Slope Compensation

The LM708x0 provides internal slope compensation for stable operation with peak current-mode control and a duty cycle greater than 50%. Calculate the buck inductance to provide a slope compensation contribution equal to one times the inductor downslope using Equation 7. L O sc = V OUT V × R S mΩ 24 × F SW MHz (7)

• A lower inductance value increases the peak-to-peak inductor current, which typically minimizes size and cost, and improves transient response at the cost of reduced light-load efficiency due to higher cores losses and peak currents.
• A higher inductance value decreases the peak-to-peak inductor current, which typically increases the full-load efficiency by reducing switch peak and RMS currents at the cost of requiring larger output capacitors to meet load-transient specifications.

6.3.12 Shunt Current Sensing

Figure 6-4 illustrates inductor current sensing using a shunt resistor. This configuration continuously monitors the inductor current to provide accurate overcurrent protection across the operating temperature range. For excellent current sense accuracy and overcurrent protection, use a low inductance ±1% tolerance shunt resistor between the inductor and the output, with a Kelvin connection to the LM708x0 current sense amplifier. If the peak differential current signal sensed from ISNS+ to VOUT exceeds the current limit threshold of 56mV, the current limit comparator immediately terminates the high-side gate driver output for cycle-by-cycle current limiting. Calculate the shunt resistance using Equation 8. R S = V C S TH I OUT C L + ∆ I L (8) where

• VCS(TH) is current sense threshold of 56mV. www.ti.com LM70840, LM70860, LM70880 SNVSCD3 – SEPTEMBER 2024 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: LM70840 LM70860 LM70880

• IOUT(CL) is the overcurrent setpoint that is set higher than the maximum load current to avoid tripping the overcurrent comparator during load transients.
• ΔILis the peak-to-peak inductor ripple current. VOUT VOUT Current sense amplifier CO ISNS+ LO RS LM708X0 VIN CS gain = 10 Figure 6-4. Shunt Current Sensing Implementation The typical current sense delay (tDELAY(CS)) is 75ns. Calculate the resultant inductor current overshoot above the overcurrent threshold using Equation 9. I L ov er s ℎ oo t = V I N − V O U T × t DEL A Y C S L O (9) The respective SS voltage is clamped 150mV above FB during an overcurrent condition. 16 overcurrent events must occur before the SS clamp is enabled. This requirement make sure that SS can be pulled low during brief overcurrent events, preventing output voltage overshoot during recovery.

6.3.13 Hiccup Mode Current Limiting

The LM708x0 includes an internal hiccup mode protection function. When an overload condition occurs, a 512-cycle counter starts counting consecutive cycle-by-cycle current limit incidents after the internal soft-start sequence is completed. The 512-cycle counter is reset if four consecutive switching cycles occur without exceeding the current limit threshold. If V FB > 400mV after 512-cycle counts are completed, the counter is restarted. When V FB < 400mV and 512-cycle counts are completed, the internal soft-start output is pulled low and the internal high-side and low-side drivers are disabled. Then, a 16384 counter is enabled. After the counter reaches 16384, the internal soft-start circuit is enabled, and the output re-starts. Note: the Hiccup mode current limit is not enabled during the soft-start time and until the feedback voltage exceeds 0.4V. LM70840, LM70860, LM70880 SNVSCD3 – SEPTEMBER 2024 www.ti.com

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6.3.14 Device Configuration (CONFIG)

The LM708x0 can be configured for operation in Standalone Mode (single device) or for operation in single output interleaved mode (two devices) for paralleling the outputs of two devices for high-current applications. When operating in interleaved mode, one of the two devices has to be configured as a primary device while the other device has to be configured as a secondary device. There is also the option to enable or disable the DRSS function as detailed in Table 6-2. During device startup, the CONFIG pin is sampled and latched. The configuration cannot be changed "on the fly". The LM708x0 input voltage must be recycled or EN pin toggled before the device can be reconfigured. Figure 6-5 shows the configuration timing diagram. When the DRSS function is enabled, the LM708x0 cannot be synchronized to an external clock. Table 6-2. Configuration Modes RCONFIG Mode Function DRSS 29.4kΩ Standalone N/A Disabled 41.2kΩ Standalone N/A Enabled 54.9kΩ Interleaved Primary Disabled 71.5kΩ Interleaved Primary Enabled 90.9kΩ Interleaved Secondary N/A EN / UVLO VCC VDDA CONFIG_START CONFIG_DONE VDDAUV 50µs SS(internal) CONFIGURATION TIME Figure 6-5. Configuration Timing www.ti.com LM70840, LM70860, LM70880 SNVSCD3 – SEPTEMBER 2024 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: LM70840 LM70860 LM70880

6.3.15 Single-Output Dual-Phase Operation

For single-output, dual-phase operation, two LM708x0 devices are required. Additional phases cannot be added. Configure the first device as a primary and the second device as a secondary per Table 6-2. This action disables the feedback error amplifier of the secondary device and places feedback error amplifier into a high-impedance state. Connect EXTCOMP pins of the primary and secondary devices together with minimal trace length. Add an external compensation network near the primary device. Internal compensation feature is not supported when operating in dual-phase configuration. The PG / SYNCOUT pin of the primary device must be connected to the PFM / SYNCIN pin of the secondary device. The SYNCOUT of the primary device is 180° out-of-phase and facilitates the interleaved operation. RT pin is not used for the oscillator when the LM708x0 is configured as a secondary device but instead is used for the slope compensation. RT resistance on the secondary device needs to be the same value as RT resistance on the primary device to make sure of correct operation. The oscillator frequency is derived from the primary device. When operating in Interleaved mode, both devices need to be enabled at the exact same time for start-up. After the regulator has started, pull the secondary EN pin low (< 0.8V) for phase shedding if needed at light load to increase the efficiency. Configure PFM mode by connecting both the PFM/SYNC pin of the primary and the FB pin of the secondary to the VDDA pin as shown in Figure 6-6. Primary SYNCOUT EN CH2EN CH1 Secondary PFM / SYNCIN EXTCOMP CONFIG FB EN PG / SYNCOUT VOUT System PGOOD VOUT VDDA VDDA PFM / SYNCIN EXTCOMP CONFIG FB EN PG / SYNCOUT 100k 90.9k54.9k RCOMP CCOMP Figure 6-6. Simplified Schematic for Single-Output Dual-Phase Operation in PFM Mode Configure FPWM mode by applying an external synchronization signal to the PFM/SYNCIN pin of the primary or connecting the pin to the AGND and connecting the FB pin of the secondary to the AGND pin as shown in Figure 6-7. LM70840, LM70860, LM70880 SNVSCD3 – SEPTEMBER 2024 www.ti.com

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90.9k54.9k RCOMP CCOMP SYNCIN Figure 6-7. Simplified Schematic for Single-Output Dual-Phase Operation in FPWM Mode Note While in interleaved mode, if an external SYNCIN signal is applied after the start-up, there is a 2 clock cycle delay before the LM708x0 locks onto the external sync signal. In PFM mode, while the primary device is pulse skipping to reduce the I Q-SLEEP current, the primary device disables the synchronization clock output, therefore the phase shedding is not supported. Phase shedding is only supported in FPWM. When operating in PFM mode under light load conditions, either primary device or secondary device or both devices can switch. In FPWM mode, the secondary device can be disabled to reduce the I Q-SLEEP current, and then the device can be enabled to support higher load currents when needed. When the secondary device enable is recycled the internal soft-start is pulled low, and then the LM708x0 goes through a normal soft-start turn-on. During the secondary soft-start time (2.8ms typical) there is a phase current imbalance until the soft-start is done. The phase current imbalance is also possible when in dropout as there is no control over the current. Matching the impedance of the outputs of the primary and secondary devices minimizes the phase current imbalance. For more information, see Benefits of a Multiphase Buck Converter and Multiphase Buck Design From Start to Finish.

6.3.16 Pulse Frequency Modulation (PFM) / Synchronization

The LM708x0 provides a diode emulation feature that can be enabled to prevent reverse (drain-to-source) current flow in the low-side MOSFET. When configured for diode emulation (DEM), the low-side MOSFET is switched off when reverse current flow is detected by sensing of the SW voltage using a zero-cross comparator. The benefit of this configuration is lower power loss during light load operation. Note: configuring the device for DEM has an effect of slower response to load transients during light load operation. The diode emulation feature is configured with the PFM / SYNCIN pin. To enable diode emulation and thus achieve discontinuous conduction mode (DCM) operation at light loads, connect PFM / SYNCIN to VDDA. Note that diode emulation is automatically engaged to prevent reverse current flow during a prebias start-up in PFM. During start up, when the output voltage approaches the regulation set point a gradual change from DCM to CCM occurs, preventing the output voltage overshoot. If forced pulse-width modulation (FPWM) or continuous conduction mode (CCM) operation is desired, tie PFM / SYNCIN to AGND. Note that the LM708x0 transitions from PFM to FPWM mode whenever LM708x0 is reset. The time to transition to FPWM operation is dependent on the output load current. In a typical application, the transition from PFM to FPWM operation occurs in less than 1ms if the output current is greater than 100mA. Similarly, for the output currents of around 1mA, the transition generally occurs in tens of milliseconds. www.ti.com LM70840, LM70860, LM70880 SNVSCD3 – SEPTEMBER 2024 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: LM70840 LM70860 LM70880

To synchronize the LM708x0 to an external source, apply a logic-level clock (greater than 1.17V) to the PFM / SYNCIN pin. The LM708x0 can be synchronized to ±20% of the programmed frequency up to a maximum of 2.2MHz. If there is an RT resistor and a synchronization signal, the LM708x0 ignores the RT resistor and synchronizes to the external clock. Under low V IN conditions when the minimum off-time is reached, the synchronization signal is ignored, allowing the switching frequency to be reduced to maintain output voltage regulation. When in FPWM mode, the time for the LM708x0 to be synchronized to an external clock frequency is approximately 100 μs. If an external clock is applied after startup while operating in PFM mode, the time to synchronize the switching frequency is dependent on the load. In a typical application, switch synchronization and FPWM operation occurs in less than 1ms if the output current exceeds 100mA. Similarly, for the output currents of around 1mA, the synchronization generally occurs in tens of milliseconds.

6.3.17 Thermal Shutdown (TSD)

The LM708x0 includes an internal junction temperature monitor that operates while the device is in active mode. If the temperature exceeds 175°C (typical), thermal shutdown occurs. When entering thermal shutdown, the device: 1. Turns off the high-side and low-side MOSFETs. 2. Pulls SS and PG pins low. 3. Turns off the VCC regulator. 4. Initiates a soft-start sequence when the die temperature decreases by the thermal shutdown hysteresis of 15°C (typical). This protection is a non-latching protection, therefore, the device cycles into and out of thermal shutdown if the fault persists. LM70840, LM70860, LM70880 SNVSCD3 – SEPTEMBER 2024 www.ti.com

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6.4 Device Functional Modes

6.4.1 Shutdown Mode

The EN / UVLO pin provides ON / OFF control for the LM708x0. When VEN is below 0.55V (typical), the device is in shutdown mode. Both the internal LDO and the switching regulator are off. The quiescent current in shutdown mode drops to 2.3 μA (typical). The LM708x0 also includes undervoltage (UV) protection of the internal bias LDO. If the internal bias supply voltage is below the UV threshold level, the switching regulator remains off.

6.4.2 Standby Mode

The internal bias LDO has a lower enable threshold than the switching regulator. When V EN is above 0.55V (typical) and below the precision enable threshold of 1V (typical), the internal LDO is on and regulating. The precision enable circuitry is turned on if the LDO output is above the bias rail UV threshold. The switching and output voltage regulation are disabled in standby mode.

6.4.3 Active Mode

The LM708x0 is in active mode when V EN is above the precision enable threshold and the internal bias rail is above the UV threshold level. In active mode, the device operates in one of two modes depending on the load current, input voltage, output voltage, and PFM / SYNCIN pin configuration: 1. Forced pulse width modulation (FPWM) mode. This mode of operation is configured by tying the PFM / SYNCIN pin to GND or driving with an external clock source. The device operates in continuous conduction mode (CCM) with fixed switching frequency regardless of the load current. 2. Pulse frequency modulation (PFM) mode. This mode of operation is configured by tying the PFM / SYNCIN pin to VDDA. The device operates in discontinuous conduction mode (DCM) if the load current is less than half of the peak-to-peak inductor current, otherwise the device operates in continuous conduction mode (CCM). The transition between CCM and DCM is automatic.

6.4.4 Sleep Mode

The LM708x0 operates with peak current-mode control such that the compensation voltage is proportional to the peak inductor current. During no-load or light-load conditions, the output capacitor discharges very slowly. As a result, the compensation voltage goes low and the switching is stopped. When the LM708x0 controller detects 16 missed switching cycles, the LM708x0 controller enters sleep mode and switches to a low I Q-SLEEP state to reduce the current drawn from the input. For the LM708x0 to go into sleep mode, the device must be programmed for PFM mode. www.ti.com LM70840, LM70860, LM70880 SNVSCD3 – SEPTEMBER 2024 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: LM70840 LM70860 LM70880

7 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

7.1 Application Information

7.1.1 Power Train Components

A comprehensive understanding of the buck regulator power train components is critical to successfully completing a synchronous buck regulator design. The following section discuss the output inductor, input and output capacitors, and EMI input filter.

7.1.1.1 Buck Inductor

For most applications, choose a buck inductance such that the inductor ripple current, ΔIL, is between 30% to 50% of the maximum DC output current at nominal input voltage. Choose the inductance using Equation 10 based on a peak inductor current given by Equation 11. L O = V OUT ΔI L × F SW × 1 − V OUT V I N (10) I L PK = I O UT + ∆ I L 2 (11) Check the inductor data sheet to make sure that the saturation current of the inductor is well above the peak inductor current of a particular design. Ferrite designs have very low core loss and are preferred at high switching frequencies, so design goals can then concentrate on copper loss and preventing saturation. Low inductor core loss is evidenced by reduced no-load input current and higher light-load efficiency. However, ferrite core materials exhibit a hard saturation characteristic and the inductance collapses abruptly when the saturation current is exceeded. This results in an abrupt increase in inductor ripple current, higher output voltage ripple, not to mention reduced efficiency and compromised reliability. Note that the saturation current of an inductor generally decreases as the core temperature increases. Of course, accurate overcurrent protection is key to avoiding inductor saturation.

7.1.1.2 Output Capacitors

Ordinarily, the output capacitor energy store of the regulator combined with the control loop response are prescribed to maintain the integrity of the output voltage within the dynamic (transient) tolerance specifications. The usual boundaries restricting the output capacitor in power management applications are driven by finite available PCB area, component footprint and profile, and cost. The capacitor parasitics—equivalent series resistance (ESR) and equivalent series inductance (ESL)—take greater precedence in shaping the load transient response of the regulator as the load step amplitude and slew rate increase. The output capacitor, C OUT, filters the inductor ripple current and provides a reservoir of charge for step-load transient events. Typically, ceramic capacitors provide extremely low ESR to reduce the output voltage ripple and noise spikes, while tantalum and electrolytic capacitors provide a large bulk capacitance in a relatively compact footprint for transient loading events. Based on the static specification of peak-to-peak output voltage ripple denoted by ΔVOUT, choose an output capacitance that is larger than that given by Equation 12. C O UT ≥ ΔI L 8 × F SW ΔV OUT 2 + R ESR × ΔI L 2 (12) LM70840, LM70860, LM70880 SNVSCD3 – SEPTEMBER 2024 www.ti.com

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common choice for a 5V output. Use Equation 13 to determine if additional capacitance is necessary to meet the load-off transient overshoot specification. A composite implementation of ceramic and electrolytic capacitors highlights the rationale for paralleling capacitors of dissimilar chemistries yet complementary performance. The frequency response of each capacitor is accretive in that each capacitor provides desirable performance over a certain portion of the frequency range. While the ceramic provides excellent mid- and high-frequency decoupling characteristics with the low ESR and ESL to minimize the switching frequency output ripple, the electrolytic device with the large bulk capacitance provides low-frequency energy storage to cope with load transient demands.

7.1.1.3 Input Capacitors

Input capacitors are necessary to limit the input ripple voltage to the buck power stage due to switching- frequency AC currents. TI recommends using X7S or X7R dielectric ceramic capacitors to provide low impedance and high RMS current rating over a wide temperature range. To minimize the parasitic inductance in the switching loop, position the input capacitors as close as possible to the drain of the high-side MOSFET and the source of the low-side MOSFET. The input capacitor RMS current for a single-channel buck regulator is given by Equation 14. I CIN r ms = D × I OUT 2 × 1 − D + ΔI L 2 12 (14) The highest input capacitor RMS current occurs at D = 0.5, at which point the RMS current rating of the input capacitors must be greater than half the output current. Ideally, the DC component of input current is provided by the input voltage source and the AC component by the input filter capacitors. Neglecting inductor ripple current, the input capacitors source current of amplitude (I OUT − IIN) during the D interval and sinks I IN during the 1−D interval. Thus, the input capacitors conduct a square-wave current of peak-to-peak amplitude equal to the output current. It follows that the resultant capacitive component of AC ripple voltage is a triangular waveform. Together with the ESR-related ripple component, the peak-to-peak ripple voltage amplitude is given by Equation 15. ΔV IN = I OUT × D × 1 − D F SW × C I N + I OUT × R ESR (15) The input capacitance required for a particular load current, based on an input voltage ripple specification of ΔVIN, is given by Equation 16. C I N ≥ D × 1 − D × I OUT F SW × ΔV IN − R ESR × I O UT (16) Low-ESR ceramic capacitors can be placed in parallel with higher valued bulk capacitance to provide optimized input filtering for the regulator and damping to mitigate the effects of input parasitic inductance resonating with high-Q ceramics. One bulk capacitor of sufficiently high current rating and two 4.7 μF X7R ceramic decoupling capacitors are usually sufficient for most applications. Select the input bulk capacitor based on the ripple current rating and operating temperature range. Of course, a two-channel buck regulator with 180° out-of-phase interleaved switching provides input ripple current cancellation and reduced input capacitor current stress. The above equations represent valid calculations when one output is disabled and the other output is fully loaded.

7.1.1.4 EMI Filter

Switching regulators exhibit negative input impedance, which is lowest at the minimum input voltage. An underdamped LC filter exhibits a high output impedance at the resonant frequency of the filter. For stability, the filter output impedance must be less than the absolute value of the converter input impedance. LM70840, LM70860, LM70880 SNVSCD3 – SEPTEMBER 2024 www.ti.com

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Z IN = − V I N min P I N (17) The EMI filter design steps are as follows:

• Calculate the required attenuation of the EMI filter at the switching frequency, where CIN represents the existing capacitance at the input of the switching converter.
• Input filter inductor LIN is usually selected between 1μH and 10μH, but can be lower to reduce losses in a high-current design.
• Calculate input filter capacitor CF. VIN GND LIN CINCF CD RD VOUT LF COUT GND Figure 7-2. Buck Regulator With π-Stage EMI Filter By calculating the first harmonic current from the fourier series of the input current waveform and multiplying the result by the input impedance (the impedance is defined by the existing input capacitor C IN), a formula is derived to obtain the required attenuation as shown by Equation 18. At t n = 20log I L PEAK π 2 × F SW × C IN × sin π × D M AX × 1 1 µ V − V M AX (18) where
• VMAX is the allowed dBμV noise level for the applicable conducted EMI specification, for example CISPR 25 Class 5.
• CIN is the existing input capacitance of the buck regulator.
• DMAX is the maximum duty cycle.
• IPEAK is the peak inductor current. For filter design purposes, the current at the input can be modeled as a square-wave. Determine the EMI filter capacitance CF from Equation 19. C F = 1 L IN At t n 2π × F SW (19) Adding an input filter to a switching regulator modifies the control-to-output transfer function. The output impedance of the filter must be sufficiently small such that the input filter does not significantly affect the loop gain of the buck converter. The impedance peaks at the filter resonant frequency. The resonant frequency of the filter is given by Equation 20. f res = 1 2 π × L IN × C F (20) www.ti.com LM70840, LM70860, LM70880 SNVSCD3 – SEPTEMBER 2024 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 27 Product Folder Links: LM70840 LM70860 LM70880

The purpose of R D is to reduce the peak output impedance of the filter at the resonant frequency. Capacitor C D blocks the DC component of the input voltage to avoid excessive power dissipation in R D. Capacitor C D must have lower impedance than RD at the resonant frequency with a capacitance value greater than that of the input capacitor CIN. This prevents C IN from interfering with the cutoff frequency of the main filter. Added damping is needed when the output impedance of the filter is high at the resonant frequency (Q of filter formed by L IN and CIN is too high). An electrolytic capacitor CD can be used for damping with a value given by Equation 21. C D ≥ 4 × C IN (21) Select the damping resistor RD using Equation 22. R D = L I N C IN (22)

7.1.2 Error Amplifier and Compensation

A Type-ll compensator using a transconductance error amplifier (EA) is shown in Figure 7-3. The dominant pole of the EA open-loop gain is set by the EA output resistance, R OEA, and effective bandwidth-limiting capacitance, CBW as shown by Equation 23. O-EA EA(open loop) O-EA BW g R G (s) 1 s R C ˜ ˜ ˜ m (23) G EA openloop s = − g m × R O EA 1 + s × R O EA × C B W (24) The EA high-frequency pole is neglected in the above expression. The compensator transfer function from output voltage to COMP node, including the gain contribution from the (internal or external) feedback resistor network, is calculated in Equation 25. G c s = v c s v out s = − V REF V OUT × g m × R OEA × 1 + s ω z1 1 + s ω p1 × 1 + s ω p2 (25) where

• VREF is the feedback voltage reference of 0.8V
• gm is the EA gain transconductance of 1200µS
• RO-EA is the error amplifier output impedance of 64MΩ ω z1 = 1 R C O MP × C COMP (26) ω p1 = 1 R O EA × C COMP + C HF + C B W ≅ 1 R O EA × C COM P (27) ω p2 = 1 R COM P × C C O MP C HF + C B W ≅ 1 R COM P × C H F (28) The EA compensation components create a pole close to the origin, a zero, and a high-frequency pole. Typically, RCOMP << RO-EA and CCOMP >> CBW and CHF, so the approximations are valid.Figure 7-3 circles the poles in red and the zero in blue. LM70840, LM70860, LM70880 SNVSCD3 – SEPTEMBER 2024 www.ti.com

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Figure 7-3. Error Amplifier and Compensation Network

7.1.3 Maximum Ambient Temperature

As with any power conversion device, the LM708x0 dissipates internal power while operating. The effect of this power dissipation is to raise the internal temperature of the converter above ambient temperature. The internal die temperature (TJ) is a function of the following:

• Ambient temperature
• Power loss
• Effective thermal resistance, RθJA, of the device
• PCB layout The maximum internal die temperature for the LM708x0 must be limited to 150°C. This limit establishes a limit on the maximum device power dissipation and, therefore, the load current. Equation 29 shows the relationships between the important parameters. Larger ambient temperatures (T A) and larger values of R θJA reduce the maximum available output current. The converter efficiency can be estimated by using the LM708x0 Quickstart Calculator tool. Alternatively, the EVM can be adjusted to match the desired application requirements and the efficiency can be measured directly. I O UT M AX = T J − T A R θJ A × η 1 − η × 1 V OUT (29) where
• η = efficiency
• TA = ambient temperature
• TJ = junction temperature
• RθJA = the effective thermal resistance of the IC junction to the air, mainly through the PCB The correct value of R θJA is more difficult to estimate. As stated in the Semiconductor and IC Package Thermal Metrics application report, the JESD 51-7 value of R θJA given in Thermal Information is not valid for design purposes and must not be used to estimate the thermal performance of the device in a real application. The JESD 51-7 values reported in Thermal Information were measured under a specific set of conditions that are rarely obtained in an actual application. The effective R θJA is a critical parameter and depends on many factors. The following are the most critical parameters:
• Power dissipation
• Air temperature
• Airflow
• PCB area
• Copper heat-sink area www.ti.com LM70840, LM70860, LM70880 SNVSCD3 – SEPTEMBER 2024 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 29 Product Folder Links: LM70840 LM70860 LM70880

• Number of thermal vias under or near the package
• Adjacent component placement Typical curves of maximum output current versus ambient temperature are shown in Derating Curves for a good thermal layout. Use Thermal Design Resources as a guide for thermal PCB design and estimating R θJA for a given application environment.

7.1.3.1 Derating Curves

The data in this section was taken on the LM70880QEVM evaluation board with a device and PCB combination, giving an R θJA of about 19°C/W. Note that the data given in these graphs are for illustration purposes only and the actual performance in any given application depends on all of the previously mentioned factors. A m b i e n t T e m p e r a t u r e ( ° C ) Maximum Output Current (A) 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 1 4 0 1 6 0 1 0 O u t p u t C o n f i g u r a t i o n 3 . 3 V - A D J 3 . 3 V - F i x e d VIN = 48V VOUT = 3.3V ƒSW = 400kHz RθJA = 18.6°C/W Figure 7-4. Maximum Output Current versus Ambient Temperature A m b i e n t T e m p e r a t u r e ( ° C ) Maximum Output Current (A) 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 1 4 0 1 6 0 1 0 O u t p u t C o n f i g u r a t i o n

5 V - A D J

5 V - F i x e d

VIN = 48V VOUT = 5V ƒSW = 400kHz RθJA = 18.6°C/W Figure 7-5. Maximum Output Current versus Ambient Temperature LM70840, LM70860, LM70880 SNVSCD3 – SEPTEMBER 2024 www.ti.com

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A m b i e n t T e m p e r a t u r e ( ° C ) Maximum Output Current (A) 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 1 4 0 1 6 0 1 0 O u t p u t C o n f i g u r a t i o n VIN = 12V VOUT = 5V ƒSW = 2.1MHz RθJA = 18.6°C/W Figure 7-6. Maximum Output Current versus Ambient Temperature A m b i e n t T e m p e r a t u r e ( ° C ) Maximum Output Current (A) 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 1 4 0 1 6 0 1 0 O u t p u t C o n f i g u r a t i o n 1 2 V - A D J o r 1 2 V - F i x e d VIN = 48V VOUT = 12V ƒSW = 400kHz RθJA = 18.6°C/W Figure 7-7. Maximum Output Current versus Ambient Temperature www.ti.com LM70840, LM70860, LM70880 SNVSCD3 – SEPTEMBER 2024 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 31 Product Folder Links: LM70840 LM70860 LM70880

7.2 Typical Applications

For step-by-step design procedure, circuit schematics, bill of materials, PCB files, simulation and test results of an LM708x0-powered implementation, see TI Designs reference design library.

7.2.1 Design 1 – High Efficiency, Wide Input, 400kHz Synchronous Buck Regulator

Figure 7-8 shows the schematic diagram of a single-output synchronous buck regulator with the output voltage of 5V and a rated load current of 8A. In this example, the target half-load and full-load efficiencies are 89.9% and 90.5%, respectively, based on a nominal input voltage of 48V that ranges from 8V to 60V. The switching frequency is set at 400kHz by resistor RRT. An output voltage of 3.3V is also feasible simply by connecting FB to VDDA. LM70880 PFM/SYNCIN VOUT ISNS+ SW CBOOT EN/UVLO EXTCOMP VCC PG/SYNCOUT VIN BIAS PGND FB VDDA CONFIG AGNDRT VOUT CIN 4 4.7 F RRT 54.9 k RCNFG 29.4k CVDDA 0.1 F CBOOT 47nF LO 3.3 H CVCC 4.7 F RFB1 100k RFB2 19.1k REN1 100k REN2 20.5k CHF 47pF RS COUT 4 47 F 5.76k RCOMPCCOMP 6.8nF Tie to VDDA or GND VIN = 5.5V...80V VOUT = 5V / 8A CIN-HF 0.1 F RBOOT Tie to VOUT, external power supply or GND Figure 7-8. Application Circuit 1 With LM70880 Buck Regulator at 400kHz Note This and subsequent design examples are provided herein to showcase the LM70880 converter in several different applications. Depending on the source impedance of the input supply bus, an electrolytic capacitor can be required at the input to make sure of stability, particularly at low input voltage and high output current operating conditions. See Section 7.3 for more detail. LM70840, LM70860, LM70880 SNVSCD3 – SEPTEMBER 2024 www.ti.com

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7.2.1.1 Design Requirements

Table 7-1 shows the intended input, output, and performance parameters for this design example. Table 7-1. Design Parameters DESIGN PARAMETER VALUE Input voltage range (steady-state) 8V to 60V Min transient input voltage (cold crank) 5.5V Max transient input voltage (load dump) 72V Output voltage 5V Output current 8A Switching frequency 400kHz Output voltage regulation ±1% Active current, no load 10µA Shutdown current 2.2µA Soft-start time 3ms The switching frequency is set at 400kHz by resistor R RT. In terms of control loop performance, the target loop crossover frequency is 30kHz with a phase margin greater than 50°. The selected buck regulator powertrain components are cited in Table 7-2, and many of the components are available from multiple vendors. This design uses a low-DCR, metal-powder composite inductor, and ceramic output capacitor implementation. Table 7-2. List of Materials for Application Circuit 1 REFERENCE DESIGNATOR QTY SPECIFICATION MANUFACTURER PART NUMBER CIN 4 4.7μF, 100V, X7S, 1210, ceramic Murata GCM32DC72A475KE02L TDK CGA6M3X7S2A475K200 CO 4 47µF, 6.3V, X7R, 1210, ceramic Murata GCM32ER70J476KE19L Taiyo Yuden JMK325B7476KMHTR 47µF, 10V, X7S, 1210, ceramic TDK CGA6P1X7S1A476M250AC LO 1 RS 1 Shunt, 5mΩ, 0508, 1W Susumu KRL3216T4A-M-R005 U1 1 LM708x0 80V buck converter Texas Instruments LM70880RRXR www.ti.com LM70840, LM70860, LM70880 SNVSCD3 – SEPTEMBER 2024 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 33 Product Folder Links: LM70840 LM70860 LM70880

7.2.1.2 Detailed Design Procedure

7.2.1.2.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the LM708x0 device with the WEBENCH Power Designer. 1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements. 2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial. 3. Compare the generated design with other possible solutions from Texas Instruments. The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time pricing and component availability. In most cases, these actions are available:

• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues Get more information about WEBENCH tools at www.ti.com/WEBENCH.

7.2.1.2.2 Custom Design With Excel Quickstart Tool

Select components based on the regulator specifications using the LM708x0 Quickstart Calculator tool available for download from the LM708x0 product folder.

7.2.1.2.3 Buck Inductor

1. Use Equation 30 to calculate the required buck inductance based on a 40% inductor ripple current at nominal input voltages. L O = V OUT ΔI L O × F SW × 1 − V OUT V IN nom = 5V 3.2A × 400 k Hz × 1 − 5V 48 V = 3.5µH (30) 2. Select a standard inductor value of 3.3µH. Use Equation 31 to calculate the peak inductor currents at maximum steady-state input voltage. Subharmonic oscillation occurs with a duty cycle greater than 50% for peak current-mode control. For design simplification, the LM708x0 has an internal slope compensation ramp proportional to the switching frequency that is added to the current sense signal to damp any tendency toward subharmonic oscillation. I LO PK = I OUT + ∆ I L O 2 = I O UT + V OUT 2 × L O × F SW × 1 − V OUT V IN max = 8 A + 5V 2 × 3.3µH × 400 k H z × 1 − 5V 60V = 9.74 A (31) 3. Based on Equation 7,use Equation 32 to cross-check the inductance to set a slope compensation close to the ideal one times the inductor current downslope. The selected 3.3µH has less downslope and be adequate. L O sc = V OUT × R S 24 × F SW = 5 V × 5mΩ 24 × 0.4 M H z = 2.6 µ H (32)

7.2.1.2.4 Current-Sense Resistance

1. Calculate the current-sense resistance based on a maximum peak current capability of at least 25% higher than the peak inductor current at full load to provide sufficient margin during start-up and load-on transients. Calculate the current sense resistances using Equation 33. R S = V C S T H 1.25 × I L O PK = 56mV where

• VCS(TH) is the 56mV current limit threshold. 2. Select a standard resistance value of 5mΩ for the shunt. A 0508 footprint component with wide aspect ratio termination design provides 1-W power rating, low parasitic series inductance, and compact PCB layout. LM70840, LM70860, LM70880 SNVSCD3 – SEPTEMBER 2024 www.ti.com

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Carefully observe the Layout Guidelines to make sure that noise and DC errors do not corrupt the differential current-sense voltages measured at the ISNS+ and VOUT pins. 3. Place the shunt resistor close to the inductor. 4. Use Kelvin-sense connections, and route the sense lines differentially from the shunt to the LM708x0. 5. The ISNS-to-output propagation delay (related to the current limit comparator, internal logic and power MOSFET gate drivers) causes the peak current to increase above the calculated current limit threshold. For a total propagation delay tISNS(delay) of 40ns, use Equation 34 to calculate the worst-case peak inductor current with the output shorted. I LOPK S C = V CS TH R S + V IN max × t I SN S dela y L O = 56 mV 5mΩ + 60V × 45ns 3.3µH = 11 . 9A (34) 6. Based on this result, select an inductor with saturation current greater than 12A across the full operating temperature range.

7.2.1.2.5 Output Capacitors

1. Use Equation 35 to estimate the output capacitance required to manage the output voltage overshoot during a load-off transient (from full load to no load) assuming a load transient deviation specification of 5% (250mV for a 5V output). C O UT ≥ L O × ΔI O UT 2 V OUT + ΔV O VERSH O OT 2 − V OUT 2 = 3.3 µ H × 8A 2

5 V + 250 mV 2 − 5V 2 = 82 µ F (35)

1. Noting the voltage coefficient of ceramic capacitors where the effective capacitance decreases significantly with applied voltage, select four 47µF, 10V, X7S, 1210 ceramic output capacitors. Generally, when sufficient capacitance is used to satisfy the load-off transient response requirement, the voltage undershoot during a no-load to full-load transient is also satisfactory. 3. Use Equation 36 to estimate the peak-peak output voltage ripple at nominal input voltage. ΔV OUT = ΔI LO 8 × F SW × C OUT + R ESR × Δ I L O 2 = 3.2A 8 × 400 k Hz × 82µF + 1 mΩ × 3.2A 2 = 12.6 mV (36) where

• RESR is the effective equivalent series resistance (ESR) of the output capacitors.
• 82µF is the total effective (derated) ceramic output capacitance at 5V. 4. Use Equation 37 to calculate the output capacitor RMS ripple current using and verify that the ripple current is within the capacitor ripple current rating. I CO RM S = Δ I L O 12 = 3.2A 12 = 0.92A (37)

7.2.1.2.6 Input Capacitors

A power supply input typically has a relatively high source impedance at the switching frequency. Good-quality input capacitors are necessary to limit the input ripple voltage. As mentioned earlier, dual-channel interleaved operation significantly reduces the input ripple amplitude. In general, the ripple current splits between the input capacitors based on the relative impedance of the capacitors at the switching frequency. 1. Select the input capacitors with sufficient voltage and RMS ripple current ratings. 2. Use Equation 38 to calculate the input capacitor RMS ripple current assuming a worst-case duty-cycle operating point of 50%. I CIN r ms = I O U T × D × 1 − D = 8 A × 0.5 × 1 − 0.5 = 4A (38) 3. Use Equation 39 to find the required input capacitance. C I N ≥ D × 1 − D × I OUT F SW × ΔV IN − R ESR × I O UT 400 k Hz × 480 mV − 2mΩ × 8A = 10.8 µ F (39) www.ti.com LM70840, LM70860, LM70880 SNVSCD3 – SEPTEMBER 2024 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 35 Product Folder Links: LM70840 LM70860 LM70880

• ΔVIN is the input peak-to-peak ripple voltage specification.
• RESR is the input capacitor ESR. 4. Recognizing the voltage coefficient of ceramic capacitors, select two 4.7µF, 100V, X7R, 1210 ceramic input capacitors. Place these capacitors adjacent to the VIN and PGND pins. 5. Use a 10nF, 100V, X7R, 0603 ceramic capacitor near the VIN and PGND pins to supply the high di/dt current during MOSFET switching transitions. Such capacitors offer high self-resonant frequency (SRF) and low effective impedance above 100MHz. The result is lower power loop parasitic inductance, thus minimizing switch-node voltage overshoot and ringing for lower conducted and radiated EMI signature. Refer to Section 7.4.1 for more detail.

7.2.1.2.7 Frequency Set Resistor

Calculate the RT resistance for a switching frequency of 400kHz using Equation 40 . Choose the nearest standard E96 value of 54.9kΩ. R RT k Ω = 10 6 F SW k Hz − 53 45 = 10 6 400 − 53 45 = 5 4.4k Ω (40)

7.2.1.2.8 Feedback Resistors

If an output voltage setpoint other than 3.3V or 5V is required (or to measure a bode plot when using either of the fixed output voltage options), determine the feedback resistances using Equation 41. R FB2 = R F B 1 V O UT V REF − 1 = 100 k Ω 5 V 0.8V − 1 = 19.05 k Ω (41)

7.2.1.2.9 Compensation Components

Choose compensation components for a stable control loop using the procedure outlined as follows. 1. Based on a specified loop gain crossover frequency, fC, of 40kHz, use Equation 42 to calculate RCOMP, assuming an effective output capacitance of 82µF. Choose a standard value for RCOMP of 5.36kΩ. R COMP = 2 × π × f C × V OUT V REF × R S × G CS gm × C OUT = 2 × π × 40 k Hz × 5 V 0.8V × 5mΩ × 10 1200 µ S × 82 µ F = 5.37 k Ω (42) 2. To provide adequate phase boost at crossover while also allowing a fast settling time during a load or line transient, select CCOMP to place a zero at the higher of (1) one tenth of the crossover frequency, or (2) the load pole. Choose a standard value for CCOMP of 6.8nF. C COM P = 10 2 × π × f C × R C OM P = 10 2 × π × 40k Hz × 5.36 k Ω = 7.42 nF (43) Such a low capacitance value also helps to avoid output voltage overshoot when recovering from dropout (when the input voltage is less than the output voltage setpoint and VCOMP is railed high). 3. Calculate CHF to create a pole at the ESR zero and to attenuate high-frequency noise at COMP. CBW is the bandwidth-limiting capacitance of the error amplifier. Select a standard value for CHF of 47pF. C HF = 1 2 × π × f ESR × R COM P − C BW = 1 2 × π × 500k H z × 5.36 k Ω − 38pF = 21 pF (44) Note Set a fast loop with high RCOMP and low CCOMP values to improve the response when recovering from operation in dropout. LM70840, LM70860, LM70880 SNVSCD3 – SEPTEMBER 2024 www.ti.com

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7.2.1.3 Application Curves

Load (A) Efficiency (%) 0 1 2 3 4 5 6 7 8 100 VIN = 8V VIN = 12V VIN = 24V VIN = 48V VIN = 60V 5V output Figure 7-9. Efficiency versus IOUT Load (A) Efficiency (%) 0.001 0.01 0.1 1 8 100 VIN = 8V VIN = 12V VIN = 24V VIN = 48V VIN = 60V 5V output Figure 7-10. Efficiency versus IOUT, Log Scale VOUT 20 mV/DIV SW 20 V/DIV 1 µs/DIV 8A resistive load Figure 7-11. Full load Switching VOUT 50 mV/DIV SW 20 V/DIV 20 ms/DIV No load Figure 7-12. PFM Switching PG 5 V/DIV VOUT 2 V/DIV IOUT 5 A/DIV VIN 10 V/DIV 1 ms/DIV VIN step to 48V 8A resistive load Figure 7-13. Start-Up Characteristic VOUT 20 mV/DIV VIN 20 V/DIV 10 ms/DIV VIN ramps from 8 to 72V 4A resistive load Figure 7-14. Line Transient Response to VIN = 72V www.ti.com LM70840, LM70860, LM70880 SNVSCD3 – SEPTEMBER 2024 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 37 Product Folder Links: LM70840 LM70860 LM70880

VIN = 48V 8A resistive load Figure 7-15. EN Start-Up Characteristic PG 5 V/DIV VOUT 1 V/DIV EN 2 V/DIV 1 ms/DIV VOUT Pre-biased to 5V Figure 7-16. EN Start-Up Prebias Characteristic VOUT 200 mV/DIV IOUT 2 A/DIV 100 µs/DIV VIN = 48V FPWM Figure 7-17. Load Transient, 2A to 6A F r e q u e n c y ( H z ) Gain (dB) Phase (°) 1 0 1 0 1 0 1 0 - 2 0 - 6 0 - 1 0 - 3 0 0 0 1 0 3 0 2 0 6 0 3 0 9 0 4 0 1 2 0 5 0 1 5 0 6 0 1 8 0 f c = 4 6 k H z P M = 4 8 . 2 ° G a i n P h a s e VIN = 48V 8A resistive load Figure 7-18. Bode Plot, 5V Output LM70840, LM70860, LM70880 SNVSCD3 – SEPTEMBER 2024 www.ti.com

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7.2.2 Design 2 – High Efficiency 48V to 12V 400kHz Synchronous Buck Regulator

Figure 7-19 shows the schematic diagram of a single-output synchronous buck regulator with the output voltage of 12V and a rated load current of 8A. In this example, the target half-load and full-load efficiencies are 95.2% and 95.6%, respectively, based on a nominal input voltage of 48V that ranges from 24V to 60V. The switching frequency is set at 400kHz by resistor RRT. LM70880 PFM/SYNCIN VOUT ISNS+ SW CBOOT EN/UVLO EXTCOMP VCC PG/SYNCOUT VIN BIAS PGND FB VDDA CONFIG AGNDRT VDDA CIN 4 4.7 F RRT 54.9k RCNFG 29.4k CVDDA 0.1 F CBOOT 47nF LO 6.8 H CVCC 4.7 F RFB 49.9k CHF 100pF RS COUT 4 22 F 6.34k RCOMPCCOMP 4.7nF Tie to VDDA or GND VIN = 15V...72V VOUT = 12V / 8A Tie to VOUT, External Bias, or GND RBOOT Figure 7-19. Application Circuit 2 With LM70880 Buck Regulator at 400kHz www.ti.com LM70840, LM70860, LM70880 SNVSCD3 – SEPTEMBER 2024 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 39 Product Folder Links: LM70840 LM70860 LM70880

7.2.2.1 Design Requirements

Table 7-3 shows the intended input, output, and performance parameters for this design example. Table 7-3. Design Parameters DESIGN PARAMETER VALUE Input voltage range (steady-state) 24V to 60V Min transient input voltage (cold crank) 15V Max transient input voltage (load dump) 72V Output voltage 12V Output current 8A Switching frequency 400kHz Output voltage regulation ±1% Active current, no load 12µA Shutdown current 2.2µA Soft-start time 3ms The switching frequency is set at 400kHz by resistor R RT The selected buck regulator powertrain components are cited in Table 7-4, and many of the components are available from multiple vendors. This design uses a low-DCR, metal-powder composite inductor, and ceramic output capacitor implementation. Table 7-4. List of Materials for Application Circuit 2 REFERENCE DESIGNATOR QTY SPECIFICATION MANUFACTURER PART NUMBER CIN 4 4.7μF, 100V, X7S, 1210, ceramic Murata GCM32DC72A475KE02L TDK CGA6M3X7S2A475K200 CO 4 22µF, 25V, X7R, 1210, ceramic Murata GCM32EC71E226KE36 TDK CGA6P3X7R1E226M LO 1 6.8µH, 6.2mΩ, 16A, 11.3 × 10 × 10mm Coilcraft XGL1010-682MEC RS 1 Shunt, 5mΩ, 0508, 1W Susumu KRL3216T4A-M-R005 U1 1 LM708x0 80V buck converter Texas Instruments LM70880RRXR

7.2.2.2 Detailed Design Procedure

See Section 7.2.1.2. LM70840, LM70860, LM70880 SNVSCD3 – SEPTEMBER 2024 www.ti.com

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7.2.2.3 Application Curves

Load (A) Efficiency (%) 0 1 2 3 4 5 6 7 8 100 VIN = 15V VIN = 24V VIN = 36V VIN = 48V VIN = 60V 12V output Figure 7-20. Efficiency versus IOUT Load (A) Efficiency (%) 0.001 0.01 0.1 1 8 100 VIN = 15V VIN = 24V VIN = 36V VIN = 48V VIN = 60V 12V output Figure 7-21. Efficiency versus IOUT, Log Scale VOUT 50 mV/DIV SW 20 V/DIV 2 µs/DIV 8A resistive load Figure 7-22. Full load Switching VOUT 100 mV/DIV SW 20 V/DIV 10 ms/DIV No load Figure 7-23. PFM Switching PG 5 V/DIV VOUT 5 V/DIV IOUT 2 A/DIV VIN 20 V/DIV 1 ms/DIV VIN step to 48V 8A resistive load Figure 7-24. Start-Up Characteristic PG 5 V/DIV VOUT 5 V/DIV IOUT 2 A/DIV EN 2 V/DIV 1 ms/DIV VIN = 48V 8A resistive load Figure 7-25. EN Start-Up Characteristic www.ti.com LM70840, LM70860, LM70880 SNVSCD3 – SEPTEMBER 2024 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 41 Product Folder Links: LM70840 LM70860 LM70880

200 µs/DIV VIN = 48V FPWM Figure 7-26. Load Transient, 0A to 4A VOUT 500 mV/DIV IOUT 2 A/DIV 200 µs/DIV VIN = 48V FPWM Figure 7-27. Load Transient, 4A to 8A LM70840, LM70860, LM70880 SNVSCD3 – SEPTEMBER 2024 www.ti.com

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7.3 Power Supply Recommendations

The LM708x0 is designed to operate from a wide input voltage range of 4.5V to 80V. The input supply must be capable of delivering the required input current to the fully-loaded regulator. Estimate the average input current with the following equation. I IN = P OUT V I N × η (45) where

• η is the efficiency If the device is connected to an input supply through long wires or PCB traces with a large impedance, take special care to achieve stable performance. The parasitic inductance and resistance of the input cables can have an adverse affect on converter operation. The parasitic inductance in combination with the low-ESR ceramic input capacitors form an underdamped resonant circuit. This circuit can cause overvoltage transients at VIN each time the input supply is cycled ON and OFF. The parasitic resistance causes the input voltage to dip during a load transient. The best way to solve such issues is to reduce the distance from the input supply to the regulator and use an aluminum or tantalum input capacitor in parallel with the ceramics. The moderate ESR of the electrolytic capacitors helps to damp the input resonant circuit and reduce any voltage overshoots. A capacitance in the range of 10µF to 47µF is usually sufficient to provide parallel input damping and helps to hold the input voltage steady during large load transients. An EMI input filter is often used in front of the regulator that, unless carefully designed, can lead to instability as well as some of the effects mentioned above. The Simple Success with Conducted EMI for DC-DC Converters application report provides helpful suggestions when designing an input filter for any switching regulator.

7.4 Layout

7.4.1 Layout Guidelines

Proper PCB design and layout is important in high-current, fast-switching converter circuits (with high current and voltage slew rates) to achieve reliable device operation and design robustness. Furthermore, the EMI performance of the converter depends to a large extent on PCB layout. The high-frequency power loop of a buck regulator power stage is denoted in red in Figure 7-28. The topological architecture of a buck regulator means that particularly high di/dt current flows in the components of the shaded loop, and reducing the parasitic inductance of this loop by minimizing the effective loop area becomes mandatory. CIN High-side MOSFET SW VIN PGND Low-side MOSFET high di/dt loop Figure 7-28. Input Current Loop The following list summarizes the essential guidelines for PCB layout and component placement to optimze DC/DC converter performance, including thermals and EMI signature. Figure 7-29 shows a recommended layout of the LM708x0 with optimized placement and routing of the power-stage and small-signal components. www.ti.com LM70840, LM70860, LM70880 SNVSCD3 – SEPTEMBER 2024 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 43 Product Folder Links: LM70840 LM70860 LM70880

• Place the input capacitors as close as possible to the input power pins: The VIN and PGND pins are close together (with a gap in between to increase clearance), thus simplifying input capacitor placement. – Use low-ESR ceramic capacitors with X7R or X7S dielectric from VIN to PGND. Place an 0402 capacitor close to VIN for high-frequency bypass as shown in Figure 7-29. Use additional 1206 or 1210 capacitors for bulk capacitance. – Ground return paths for both the input and output capacitors must consist of localized top-side planes that connect to the PGND pins.
• Use a solid ground plane on the PCB layer beneath the top layer with the IC: This plane acts as a noise shield and a heat dissipation path. Using the PCB layer directly below the IC minimizes the magnetic field associated with the currents in the switching loops, thus reducing parasitic inductance and switch voltage overshoot and ringing. Use numerous thermal vias near PGND for heatsinking to the inner ground planes.
• Make the VIN, VOUT, and GND bus connections as wide as possible: These paths must be wide and direct as possible to reduce any voltage drops on the input or output paths of the converter, thus maximizing efficiency.
• Locate the buck inductor close to the SW1, SW2, and SW3 pins: Use a short, wide connection trace from the converter SW pins to the inductor. At the same time, minimize the length (and area) of this high-dv/dt surface to help reduce capacitive coupling and radiated EMI. Connect the dotted terminal of the inductor to the SW pins.
• Place the VCC and BOOT capacitors close to the respective pins: The VCC and BOOT capacitors represent the supplies for the internal low-side and high-side MOSFET gate drivers, respectively, and thus carry high-frequency currents. Locate CVCC close to the VCC pin and place a GND via at the return terminal to connect to the GND plane and thus back to IC GND at the exposed pad. Connect CBOOT close to the CBOOT and SW4 pins.
• Place the feedback divider as close as possible to the FB pin: Reduce noise sensitivity of the output voltage feedback path by placing the resistor divider close to the FB pin, rather than close to the load. This reduces the FB trace length and related noise coupling. The FB pin is the input to the voltage-loop error amplifier and represents a high-impedance node sensitive to noise. The connection to VOUT can be somewhat longer. However, this latter trace must not be routed near any noise source (such as the switch node) that can capacitively couple into the feedback path of the converter.
• Provide enough PCB area for proper heatsinking: Use sufficient copper area to achieve a low thermal impedance commensurate with the maximum load current and ambient temperature conditions. Provide adequate heatsinking for the LM708x0 to keep the junction temperature below 150°C. For operation at full rated load, the top-side ground plane is an important heat-dissipating area. Use an array of heat-sinking vias to connect the exposed pad (GND) of the package to the PCB ground plane. If the PCB has multiple copper layers, connect these thermal vias to inner-layer ground planes. Make the top and bottom PCB layers preferably with two-ounce copper thickness (and no less than one ounce).

7.4.1.1 Thermal Design and Layout

For a DC/DC converter to be useful over a particular temperature range, the package must allow for the efficient removal of the heat produced while keeping the junction temperature within rated limits. The LM708x0 is available in a small 6mm × 6mm 29-pin QFN integrated circuit package to cover a range of application requirements. Numerous vias with a 0.3mm diameter connected from the thermal pads to the internal and solder-side plane or planes are vital to help dissipation. In a multi-layer PCB design, a solid GND plane is typically placed on the PCB layer below the power components. Not only does this action provide a plane for the power stage currents to flow but this action also represents a thermally conductive path away from the heat generating devices. LM70840, LM70860, LM70880 SNVSCD3 – SEPTEMBER 2024 www.ti.com

44 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

Product Folder Links: LM70840 LM70860 LM70880

7.4.2 Layout Example

and PGND pins. Place inductor close to the SW pins SW VIN PGNDCIN COUT COUT RSENSELF Figure 7-29. PCB Top Layer – High Density, Single-sided Design www.ti.com LM70840, LM70860, LM70880 SNVSCD3 – SEPTEMBER 2024 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 45 Product Folder Links: LM70840 LM70860 LM70880

8 Device and Documentation Support

8.1 Device Support

8.1.1 Development Support

For development support see the following:

• LM708x0 Quickstart Calculator tool
• LM708x0 Simulation Models
• For TI's reference design library, visit TI Designs
• For TI's WEBENCH Design Environment, visit the WEBENCH® Design Center
• TI Designs: – 137W Holdup Converter for Storage Server Reference Design – Wide Input Synchronous Buck Converter Reference Design With Frequency Spread Spectrum
• Technical articles: – High-Density PCB Layout of DC/DC Converters – Synchronous Buck Controller Solutions Support Wide VIN Performance and Flexibility – How to Use Slew Rate for EMI Control

8.1.1.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the LM708x0 device with the WEBENCH Power Designer. 1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements. 2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial. 3. Compare the generated design with other possible solutions from Texas Instruments. The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time pricing and component availability. In most cases, these actions are available:

• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues Get more information about WEBENCH tools at www.ti.com/WEBENCH.

8.2 Documentation Support

8.2.1 Related Documentation

For related documentation see the following:

• Application notes: – Texas Instruments, Improve High-current DC/DC Regulator Performance for Free with Optimized Power Stage Layout – Texas Instruments, AN-2162 Simple Success with Conducted EMI from DC-DC Converters
• Analog design journal: – Texas Instruments, Reduce Buck Converter EMI and Voltage Stress by Minimizing Inductive Parasitics
• White papers: – Texas Instruments, An Overview of Conducted EMI Specifications for Power Supplies – Texas Instruments, An Overview of Radiated EMI Specifications for Power Supplies – Texas Instruments, Valuing Wide VIN, Low EMI Synchronous Buck Circuits for Cost-driven, Demanding

Applications

8.2.1.1 PCB Layout Resources

• Application notes: – Texas Instruments, Improve High-current DC/DC Regulator Performance for Free with Optimized Power Stage Layout LM70840, LM70860, LM70880 SNVSCD3 – SEPTEMBER 2024 www.ti.com

46 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

Product Folder Links: LM70840 LM70860 LM70880

– Texas Instruments, AN-1149 Layout Guidelines for Switching Power Supplies – Texas Instruments, AN-1229 Simple Switcher PCB Layout Guidelines – Texas Instruments, Low Radiated EMI Layout Made SIMPLE with LM4360x and LM4600x

• Seminars: – Texas Instruments, Constructing Your Power Supply – Layout Considerations

8.2.1.2 Thermal Design Resources

• Application notes: – Texas Instruments, AN-2020 Thermal Design by Insight, Not Hindsight – AN-1520 A Guide to Board Layout for Best Thermal Resistance for Exposed Pad Packages – Texas Instruments, Semiconductor and IC Package Thermal Metrics – Texas Instruments, Thermal Design Made Simple with LM43603 and LM43602 – Texas Instruments, PowerPAD™Thermally Enhanced Package – Texas Instruments, PowerPAD Made Easy – Texas Instruments, Using New Thermal Metrics

8.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

8.4 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

8.5 Trademarks

PowerPAD™ and TI E2E™ are trademarks of Texas Instruments. WEBENCH® is a registered trademark of Texas Instruments. All trademarks are the property of their respective owners.

8.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

8.7 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

9 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. DATE REVISION NOTES September 2024 * Initial release

10 Mechanical, Packaging, and Orderable Information

The following pages show mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. www.ti.com LM70840, LM70860, LM70880 SNVSCD3 – SEPTEMBER 2024 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 47 Product Folder Links: LM70840 LM70860 LM70880

www.ti.com 8-Nov-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) LM70840RRXR Active Production VQFN (RRX) | 29 3000 | LARGE T&R ROHS Exempt NIPDAU Level-2-260C-1 YEAR -40 to 150 70840 LM70840RRXR.A Active Production VQFN (RRX) | 29 3000 | LARGE T&R ROHS Exempt NIPDAU Level-2-260C-1 YEAR -40 to 150 70840 LM70840RRXR.B Active Production VQFN (RRX) | 29 3000 | LARGE T&R - Call TI Call TI -40 to 150 LM70860RRXR Active Production VQFN (RRX) | 29 3000 | LARGE T&R ROHS Exempt NIPDAU Level-2-260C-1 YEAR -40 to 150 70860 LM70860RRXR.A Active Production VQFN (RRX) | 29 3000 | LARGE T&R ROHS Exempt NIPDAU Level-2-260C-1 YEAR -40 to 150 70860 LM70860RRXR.B Active Production VQFN (RRX) | 29 3000 | LARGE T&R - Call TI Call TI -40 to 150 LM70880RRXR Active Production VQFN (RRX) | 29 3000 | LARGE T&R ROHS Exempt NIPDAU Level-2-260C-1 YEAR -40 to 150 70880 LM70880RRXR.A Active Production VQFN (RRX) | 29 3000 | LARGE T&R ROHS Exempt NIPDAU Level-2-260C-1 YEAR -40 to 150 70880 LM70880RRXR.B Active Production VQFN (RRX) | 29 3000 | LARGE T&R - Call TI Call TI -40 to 150 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative Addendum-Page 1

www.ti.com 8-Nov-2025 and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF LM70840, LM70860, LM70880 :

• Automotive : LM70840-Q1 , LM70860-Q1 , LM70880-Q1 NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM70840RRXR VQFN RRX 29 3000 367.0 367.0 38.0 LM70860RRXR VQFN RRX 29 3000 367.0 367.0 38.0 LM70880RRXR VQFN RRX 29 3000 367.0 367.0 38.0 Pack Materials-Page 2

www.ti.com PACKAGE OUTLINE 6.1 5.9 6.1 5.9 3.125 0.1 1.0 0.8 0.05 0.00 2.25 .000 PKG 0 1.75 1.25 0.25 0.25 2X 1.25 2X 1.75 2.25 1.308 2.8 2.316 0.1 .000 PKG 0 1.5 1.584 0.1 1.5 2X 0.5 2X 1 2X 1.5 2X 2 1.337 2.925 0.1 1.96 0.1 1.75 1.25 0.75 0.75 0.037 1.725 0.1 29X 0.3 0.2 2.35 1.12 21X 0.5 0.3 (0.277) (0.266) (0.2) TYP (0.1) TYP (0.2) (0.25) VQFN - 1.0 mm max heightRRX0029B PLASTIC QUAD FLATPACK - NO LEAD 4228757/D 04/2024 0.08 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. PIN 1 INDEX AREA SEATING PLANE

0.1 C A B

0.05 C 9 16 SCALE 2.000 AB C

www.ti.com EXAMPLE BOARD LAYOUT ( ) 3.2 .000 PKG 0 ( ) 3.2 .000 PKG 1.834

0.07 MAX

ALL AROUND 0.07 MIN ALL AROUND (3.125) (1.584) 21X (0.25) 21X (0.6) (0.25) ( ) 3.2 ( ) 2.8 ( ) 2.6 ( ) 2.25 ( ) 1.75 ( ) 1.25 ( ) 0.761 ( ) 0.484 ( ) 0.25 ( ) 0.25 ( ) 1.25 ( ) 1.75 ( ) 2.25 ( ) 1.308 ( ) 2.9 2X ( ) 2.55 2X ( ) 1.642 ( ) 3.2 ( ) 2.8 ( ) 2.55 2X ( ) 2.1 ( ) 2 ( ) 1.5 ( ) 1 3X ( ) 0.875 ( ) 0.125 2X ( ) 0.5 2X ( ) 1 2X ( ) 1.5 2X ( ) 2 ( ) 2.8 ( ) 3.2 ( ) 2.35 ( ) 2.084 ( ) 0.625 ( ) 2.9 ( ) 2.1 ( ) 1.75 ( ) 1.25 ( ) 0.75 5X ( ) 0.14 3X ( ) 0.766 ( ) 0.75 ( ) 1.25 ( ) 1.75 3X ( ) 1.85 ( ) 1.308 ( ) 2.9 2X ( ) 1.35 ( ) 0.037 ( ) 1 ( ) 1.5 ( ) 2 ( ) 2.9 2X ( ) 1.275 (R0.05) TYP 2X ( ) 0.734 VQFN - 1.0 mm max heightRRX0029B PLASTIC QUAD FLATPACK - NO LEAD 4228757/D 04/2024 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. SOLDER MASK DETAILS LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 15X 9 16 2329 METAL EDGE SOLDER MASK OPENING EXPOSED METAL NON SOLDER MASK DEFINED (PREFERRED) METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METAL SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN ( ) 2.9 .000 PKG 0 ( ) 2.9 .000 PKG 0 3X (0.258) 2X (1.35) (1.27) 2X (1.75) (0.9) 21X (0.6) 21X (0.25) 2X (1) 3X (0.293) 8X (0.25) ( ) 2.9 ( ) 2.25 2X ( ) 1.75 2X ( ) 1.25 2X ( ) 1.308 ( ) 0.25 ( ) 0.25 ( ) 1.042 ( ) 1.25 ( ) 3.071 ( ) 2.192 ( ) 2.242 ( ) 2.25 ( ) 2.9 ( ) 2 ( ) 1.5 ( ) 1 ( ) 0.738 ( ) 0.812 ( ) 2.9 2X (1.42) ( ) 2 ( ) 3.066 ( ) 1.5 2X ( ) 1.463 ( ) 1 ( ) 0.602 2X ( ) 0.5 2X ( ) 1 2X ( ) 1.5 2X ( ) 2 ( ) 2.072 ( ) 0.75 ( ) 0.75 ( ) 1.25 ( ) 1.75 2X (1.5) (0.32) 2X ( ) 1.095 ( ) 2.573 VQFN - 1.0 mm max heightRRX0029B PLASTIC QUAD FLATPACK - NO LEAD 4228757/D 04/2024 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 15X 9 16 2329 (45 X 0.3)

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