LM6L3N10 LEIDITECH
Document overview
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Technical content
APPLICATIONS
The LM6L3N10 is the N-Channel logic enhancement mode power field effect transistor which is produced using super high cell density DMOS trench technology. The LM6L3N10 has been designed specifically to improve the overall efficiency of DC/DC converters using either synchronous or conventional switching PWM controllers. It has been optimized for low gate charge, low R DS(ON) and fast switching speed. Powered System DC/DC Converter Load Switch
FEATURES
100V/3A,R DS(ON) = 310mΩ@V GS = 10V High density cell design for extremely low RDS (ON) Exceptional on-resistance and maximum DC current capability SOT-23-6L package design PIN CONFIGURATION(SOT-23-6L) LM6L3N10 100V N-Channel Enhancement Mode MOSFET Rev : www.leiditech.com 01.06.2018 1/4
DESCRIPTION
Package Marking and Ordering Information Device Marking Device Device Package Reel Size Tape width Quantity WANLM6L3N10 SOT-23-6L 3000 units - - ABSOULTE MAXIMUM RATINGS (T A =25 Unless otherwise℃ noted) Parameter Symbol Typical Unit Drain-Source Voltage V DSS 100 V Gate –Source V oltage V GSS ±20 V Continuous Drain Current(T J =150 )℃ T A =25℃ I D 3.0 A T A =70℃ 2.0 Pulsed Drain Current I DM 10 A Power Dissipation T A =25℃ P D 1.25 W T A =70℃ 0.8 Operating Junction Temperature T J -55/150 ℃ Storage Temperature Range T STG -55/150 ℃ Thermal Resistance-Junction to Ambient R θJA 100 ℃/W
Rev : www.leiditech.com 01.06.2018 2/4 ELECTRICAL CHARACTERISTICS (T A =25 Unless otherwise noted)℃ Parameter Symbol Conditions Min. Typ Max. Unit Static Drain-Source Breakdown V oltage V (BR)DSS V GS =0V ,I D =250uA 100 V Gate Threshold Voltage V GS(th) V DS GS D =250uA 1 2.0 2.5 Gate Leakage Current I GSS V DS =0V ,V GS =±20V ±100 nA Zero Gate V oltage Drain Current I DSS V DS =80V,V GS =0V 1 uA V DS =80V,V GS =0V T J =125℃ 5 On-State Drain Current I D(on) V DS ≥5V,V GS =10V 3.0 A Drain-Source On-Resistance R DS(on) V GS = 10V,I D =3A 0.26 0.31 Ω Forward Transconductance gfs V DS =10V,I D =3A 2.4 S Diode Forward V oltage V SD I S =1A,V GS =0V 1.2 V Dynamic Total Gate Charge Q g V DS =80V,V GS =10V I D = 5A 9 13 nC Gate-Source Charge Q gs Gate-Drain Charge Q gd 1.4 Input Capacitance C iss V DS =25,V GS =0V f=1MHz 508 pF Output Capacitance C oss Reverse Transfer Capacitance C rss 16.5 Turn-On Time t d(on) V DD =50V,R L =10Ω I D =3A,V GEN =10V R G =3.3Ω nS t r 21.5 Turn-Off Time t d(off) 11.2 t f 18.8 LM6L3N10
Rev : www.leiditech.com 01.06.2018 3/4 Figure1. Output Characteristics Figure2. Transfer Characteristics Figure3. Capacitance Characteristics Figure4. Gate Charge Figure5. Drain-Source on Resistance Figure6. Drain-Source on Resistance Typical Performance Characteristics LM6L3N10
Shanghai Leiditech Electronic Co.,Ltd Email: sale1@leiditech.com Tel : +86- 021 50828806 Fax : +86- 021 50477059 Rev : www.leiditech.com 01.06.2018 4/4 Suggested Land Pattern X C P G Y Z SYM DIMENSIONS MILLIMETERS INCHES C 2.50 0.098 G 1.40 0.055 P 0.95 0.037 X 0.60 0.024 Y 1.10 0.043 Z 3.60 0.141 LM6L3N10