LM613x Dual and Quad, Low-Power, 10MHz, Rail-to-Rail I/O Operational Amplifiers datasheet (Rev. F)
Document overview
- Manufacturer or author: Texas Instruments, Incorporated [SNOS751,F]
- PDF pages: 33
Technical content
LM613x Dual and Quad, Low-Power, 10MHz, Rail-to-Rail I/O Operational Amplifiers
1 Features
- (For 5V supply, typical unless noted)
- Rail-to-rail input CMVR: −0.25V to 5.25V
- Rail-to-rail output
- High gain-bandwidth: 10MHz at 20kHz
- Slew rate: 12V/μs
- Low supply current: 360μA/amp
- Wide supply range: 2.7V to over 24V
- CMRR: 100dB
- Gain: 100dB with RL = 10kΩ
- PSRR: 82dB
2 Applications
- Battery-operated instrumentation
- Instrumentation amplifiers
- Portable scanners
- Wireless communications
- Flat-panel display driver
3 Description
The LM6132 and LM6134 (LM613x) provide new levels of speed versus power performance in applications where low-voltage supplies or power limitations previously made compromise necessary. With only 360 μA/amp supply current, the 10MHz gain-bandwidth of this device supports new portable applications where higher power devices unacceptably drain battery life. The LM613x can be driven by voltages that exceed both power supply rails, thus eliminating concerns over exceeding the common-mode voltage range. The rail-to-rail output swing capability provides the maximum possible dynamic range at the output. This feature is particularly important when operating on low supply voltages. The LM613x also drives large capacitive loads without oscillating. Operating on supplies from 2.7V to over 24V, the LM6132x are excellent for a very wide range of applications, from battery-operated systems with large bandwidth requirements to high-speed instrumentation. Device Information PART NUMBER CHANNE L COUNT PACKAGE(1) BODY SIZE LM6132 Dual D (SOIC, 8) 4.90mm × 3.91mm P (PDIP, 8) 9.81mm × 6.35mm LM6134 Quad D (SOIC, 14) 8.65mm × 3.91mm NFF (PDIP, 14) 19.177mm × 6.35mm (1) For more information, see Section 9. Slew Boost IN+ IN- OUT NPN Input Stage PNP Input Stage Output Stage Functional Block Diagram LM6132, LM6134 SNOS751F – APRIL 2000 – REVISED JUNE 2026 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.
9 Mechanical, Packaging, and Orderable Information..19 LM6132, LM6134 SNOS751F – APRIL 2000 – REVISED JUNE 2026 www.ti.com
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4 Pin Configuration and Functions
Figure 4-1. D Package, 8-Pin SOIC,and P Package, 8-Pin PDIP (Top View) Figure 4-2. D Package, 14-Pin SOIC, and NFF Package, 14-Pin PDIP (Top View) Pin Functions PIN TYPE DESCRIPTION NAME LM6132 LM6134 D (SOIC), P (PDIP) D (SOIC), NFF (PDIP) –IN A 2 2 Input ChA inverting input +IN A 3 3 Input ChA noninverting input –IN B 6 6 Input ChB inverting input +IN B 5 5 Input ChB noninverting input –IN C 9 Input ChC inverting input +IN C 10 Input ChC noninverting input –IN D 13 Input ChD inverting input +IN D 12 Input ChD noninverting input OUT A 1 1 Output ChA output OUT B 7 7 Output ChB output OUT C 8 Output ChC output OUT D 14 Output ChD output V– 4 11 Input Negative supply V+ 8 4 Input Positive supply www.ti.com LM6132, LM6134 SNOS751F – APRIL 2000 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: LM6132 LM6134
5 Specifications
5.1 Absolute Maximum Ratings
over operating ambient temperature range (unless otherwise noted)(1) MIN MAX UNIT Supply voltage, VS = (V+) – (V–) 0 33 V Signal input pins Common-mode voltage(3) (V–) – 0.5 (V+) + 0.5 V Differential voltage(4) ±15 V Current(3) ±10 mA Output short-circuit(2) Continuous Operating ambient temperature, TA –55 150 °C Junction temperature, TJ 150 °C Storage temperature, Tstg –65 150 °C (1) Operating the device beyond the ratings listed under Absolute Maximum Ratings will cause permanent damage to the device. These are stress ratings only, based on process and design limitations, and this device has not been designed to function outside the conditions indicated under Recommended Operating Conditions. Exposure to any condition outside Recommended Operating Conditions for extended periods, including absolute-maximum-rated conditions, may affect device reliability and performance. (2) Short-circuit to ground, one amplifier per package. Extended short-circuit current, especially with higher supply voltage, can cause excessive heating and eventual destruction. (3) Input pins are diode-clamped to the power-supply rails. Input signals that may swing more than 0.5V beyond the supply rails must be current limited to 10mA or less. (4) Input pins are connected by back-to-back diodes for input protection. If the differential input voltage may exceed 0.5V, limit the input current to 10mA or less.
5.2 ESD Ratings
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±4000 V Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002(2) ±1500 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
5.3 Recommended Operating Conditions
over operating ambient temperature range (unless otherwise noted) MIN MAX UNIT VS Supply voltage, (V+) – (V–) 2.7 24 V VI Common mode voltage range (V–) – 0.1 (V+) + 0.1 V TA Specified temperature –40 85 °C LM6132, LM6134 SNOS751F – APRIL 2000 – REVISED JUNE 2026 www.ti.com
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5.4 Thermal Information LM6132
THERMAL METRIC(1) LM6132 UNITD (SOIC) P (PDIP)
8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 127.10 84.45 °C/W RθJC(top) Junction-to-case (top) thermal resistance 63.27 58.07 °C/W RθJB Junction-to-board thermal resistance 71.20 50.90 °C/W ψJT Junction-to-top characterization parameter 13.91 30.43 °C/W ψJB Junction-to-board characterization parameter 70.54 50.44 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.
5.5 Thermal Information LM6134
THERMAL METRIC(1) LM6134 UnitD (SOIC) NFF (PDIP)
14 PINS 14 PINS
RθJA Junction-to-ambient thermal resistance 82.48 81 °C/W RθJC(top) Junction-to-case (top) thermal resistance 38.77 N/A °C/W RθJB Junction-to-board thermal resistance 37.86 N/A °C/W ψJT Junction-to-top characterization parameter 8.66 N/A °C/W ψJB Junction-to-board characterization parameter 37.51 N/A °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. www.ti.com LM6132, LM6134 SNOS751F – APRIL 2000 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: LM6132 LM6134
5.6 Electrical Characteristics: VS = 5V
For V+ = 5.0V, V– = 0V, RL > 1MΩ connected to VS / 2, VCM = V+ / 2, and VO = V+ / 2, at TA = 25°C, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OFFSET VOLTAGE VOS Input offset voltage LM6132AI, LM6134AI 0.25 2 mV TA = –40°C to 85°C 4 LM6132BI, LM6134BI 0.25 6 TA = –40°C to 85°C 8 dVOS/dT Input offset voltage drift TA = –40°C to 85°C 5 µV/℃ PSRR Input offset voltage versus power supply 2.5V ≤ |VS| ≤ 12V, LM6132AI, LM6134AI 78 82 dB TA = –40°C to 85°C 75 2.5V ≤ |VS| ≤ 12V, LM6132BI, LM6134BI 78 82 TA = –40°C to 85°C 75 INPUT BIAS CURRENT IB Input bias current 0V ≤ VCM ≤ 5V, LM6132AI, LM6134AI 110 140 nA TA = –40°C to 85°C 300 0V ≤ VCM ≤ 5V, LM6132BI, LM6134BI 110 180 TA = –40°C to 85°C 350 IOS Input offset current LM6132AI, LM6134AI 3.4 30 nA TA = –40°C to 85°C 50 LM6132BI, LM6134BI 3.4 30 TA = –40°C to 85°C 50 INPUT VOLTAGE VCM Common-mode input voltage range – 0.25 5.25 V TA = –40°C to 85°C 0 5 V CMRR Common-mode rejection ratio 0V ≤ VCM ≤ 4V, LM6132AI, LM6134AI 75 100 dB TA = –40°C to 85°C 70 0V ≤ VCM ≤ 4V, LM6132BI, LM6134BI 75 100 TA = –40°C to 85°C 70 0V ≤ VCM ≤ 5V, LM6132AI, LM6134AI 60 100 TA = –40°C to 85°C 55 0V ≤ VCM ≤ 5V, LM6132BI, LM6134BI 60 100 TA = –40°C to 85°C 55 INPUT IMPEDANCE RIN Common-mode input resistance 104 MΩ OPEN-LOOP GAIN AOL Open-loop voltage gain RL = 10kΩ, LM6132AI, LM6134AI 25 100 V/mV TA = –40°C to 85°C 8 RL = 10kΩ, LM6132BI, LM6134BI 15 100 TA = –40°C to 85°C 6 NOISE eN Input voltage noise density f = 1kHz 27 nV/√Hz iN Input current noise density f = 1kHz 0.18 pA/√Hz FREQUENCY RESPONSE GBW Gain-bandwidth product f = 20kHz 7.4 10 MHz TA = –40°C to 85°C 7 SR Slew rate VS = 12V, VSTEP = 8V, RS < 1kΩ 8 14 V/μs TA = –40°C to 85°C 7 PM Phase margin RL = 10 kΩ 33 ° GM Gain margin RL = 10 kΩ 10 dB LM6132, LM6134 SNOS751F – APRIL 2000 – REVISED JUNE 2026 www.ti.com
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For V+ = 5.0V, V– = 0V, RL > 1MΩ connected to VS / 2, VCM = V+ / 2, and VO = V+ / 2, at TA = 25°C, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OUTPUT VO Voltage output swing RL = 100kΩ, From positive rail 30 40 mV TA = –40°C to 85°C 70 RL = 100kΩ, From negative rail 30 35 TA = –40°C to 85°C 50 RL = 10kΩ, From positive rail 48 60 TA = –40°C to 85°C 150 RL = 10kΩ, From negative rail 32 70 TA = –40°C to 85°C 90 RL = 5kΩ, From positive rail 77 100 TA = –40°C to 85°C 150 RL = 5kΩ, From negative rail 51 95 TA = –40°C to 85°C 120 ISC Short-circuit current Sourcing, LM6132A 2 4 mA TA = –40°C to 85°C 2 Sourcing, LM6132B 2 4 TA = –40°C to 85°C 1 Sinking, LM6132A 1.8 3.5 TA = –40°C to 85°C 1.8 Sinking, LM6132B 1.8 3.5 TA = –40°C to 85°C 1 Sourcing, LM6134A 2 3 TA = –40°C to 85°C 1.6 Sourcing, LM6134B 2 3 TA = –40°C to 85°C 1 Sinking, LM6134A 1.8 3.5 TA = –40°C to 85°C 1.3 Sinking, LM6134B 1.8 3.5 TA = –40°C to 85°C 1 POWER SUPPLY IQ Quiescent current per amplifier LM6132AI, LM6134AI 360 400 µA TA = –40°C to 85°C 450 LM6132BI, LM6134BI 360 400 µA TA = –40°C to 85°C 450 µA www.ti.com LM6132, LM6134 SNOS751F – APRIL 2000 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: LM6132 LM6134
5.7 Electrical Characteristics: VS = 2.7V For V+ = 2.7V, V– = 0V, RL > 1MΩ connected to VS / 2, VCM = V+ / 2, and VO = V+ / 2, at TA = 25°C, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OFFSET VOLTAGE VOS Input offset voltage LM6132AI, LM6134AI 0.12 2 mV TA = –40°C to 85°C 8 LM6132BI, LM6134BI 0.12 6 TA = –40°C to 85°C 12 PSRR Input offset voltage versus power supply 1.35V ≤ |VS| ≤ 12V, 80 dB INPUT BIAS CURRENT IB Input bias current 0V ≤ VCM ≤ 2.7V 90 nA IOS Input offset current 2.8 nA INPUT VOLTAGE VCM Common-mode input voltage range 0 2.7 V CMRR Common-mode rejection ratio 0V ≤ VCM ≤ 2.7V 82 dB INPUT IMPEDANCE RIN Common-mode input resistance 134 MΩ OPEN-LOOP GAIN AOL Open-loop voltage gain RL = 10kΩ 100 V/mV NOISE FREQUENCY RESPONSE GBW Gain-bandwidth product f = 20kHz, RL = 10 kΩ 7 MHz PM Phase margin RL = 10 kΩ 23 ° GM Gain margin 12 dB OUTPUT VO Voltage output swing RL = 100kΩ, From positive rail 40 50 mV TA = –40°C to 85°C 450 RL = 100kΩ, From negative rail 30 80 TA = –40°C to 85°C 112 POWER SUPPLY IQ Quiescent current per amplifier 330 µA LM6132, LM6134 SNOS751F – APRIL 2000 – REVISED JUNE 2026 www.ti.com
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5.8 Electrical Characteristics: VS = 24V
For V+ = 24V, V– = 0V, RL > 1MΩ connected to VS / 2, VCM = V+ / 2, and VO = V+ / 2, at TA = 25°C, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OFFSET VOLTAGE VOS Input offset voltage LM6132AI, LM6134AI 1.7 3 mV TA = –40°C to 85°C 5 LM6132BI, LM6134BI 1.7 7 TA = –40°C to 85°C 9 PSRR Input offset voltage versus power supply 1.35V ≤ |VS| ≤ 12V, 82 dB INPUT BIAS CURRENT IB Input bias current 0V ≤ VCM ≤ 24V 125 nA IOS Input offset current 4.8 nA INPUT VOLTAGE VCM Common-mode input voltage range 0 24 V CMRR Common-mode rejection ratio 0V ≤ VCM ≤ 24V 82 dB INPUT IMPEDANCE RIN Common-mode input resistance 210 MΩ OPEN-LOOP GAIN AOL Open-loop voltage gain RL = 10kΩ 102 V/mV NOISE FREQUENCY RESPONSE GBW Gain-bandwidth product f = 20kHz, RL = 10 kΩ 11 MHz PM Phase margin RL = 10 kΩ 23 ° GM Gain margin RL = 10 kΩ 12 dB THD+N Total harmonic distortion + noise VO = 20VPP, G = 1, f = 10kHz 0.0015 % OUTPUT VO Voltage output swing RL = 10kΩ, From positive rail 140 200 mV RL = 10kΩ, From negative rail 75 150 POWER SUPPLY IQ Quiescent current per amplifier 390 450 µA TA = –40°C to 85°C 490 www.ti.com LM6132, LM6134 SNOS751F – APRIL 2000 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: LM6132 LM6134
5.9 Typical Characteristics
at TA = 25°C and RL = 10 kΩ (unless otherwise specified) Figure 5-1. Supply Current vs Supply Voltage Figure 5-2. Offset Voltage vs Supply Voltage Figure 5-3. dVOS vs VCM Figure 5-4. dVOS vs VCM Figure 5-5. dVOS vs VCM Figure 5-6. dVOS vs Output Voltage LM6132, LM6134 SNOS751F – APRIL 2000 – REVISED JUNE 2026 www.ti.com
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5.9 Typical Characteristics (continued)
at TA = 25°C and RL = 10 kΩ (unless otherwise specified) Figure 5-7. dVOS vs Output Voltage Figure 5-8. dVOS vs Output Voltage Figure 5-9. IBIAS vs VCM Figure 5-10. IBIAS vs VCM Figure 5-11. IBIAS vs VCM Figure 5-12. Input Bias Current vs Supply Voltage www.ti.com LM6132, LM6134 SNOS751F – APRIL 2000 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: LM6132 LM6134
at TA = 25°C and RL = 10 kΩ (unless otherwise specified) Figure 5-13. Negative PSRR vs Frequency, Old Die Figure 5-14. Positive PSSR vs Frequency, Old Die Figure 5-15. CMRR vs Frequency, Old Die F r e q u e n c y ( H z ) Rejection Ratio (dB) 2 0 4 0 6 0 8 0 1 0 0 1 2 0 1 4 0 1 6 0 1 0 m 1 0 0 m 1 1 0 1 0 0 1 k 1 0 k 1 0 0 k 1 M 1 0 M C M R R P S R R − P S R R + Figure 5-16. CMRR and PSRR vs Frequency, New Die Figure 5-17. Output Voltage vs Sinking Current Figure 5-18. Output Voltage vs Sinking Current LM6132, LM6134 SNOS751F – APRIL 2000 – REVISED JUNE 2026 www.ti.com
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at TA = 25°C and RL = 10 kΩ (unless otherwise specified) Figure 5-19. Output Voltage vs Sinking Current Figure 5-20. Output Voltage vs Sourcing Current Figure 5-21. Output Voltage vs Sourcing Current Figure 5-22. Output Voltage vs Sourcing Current Figure 5-23. Noise Voltage vs Frequency Figure 5-24. Noise Current vs Frequency www.ti.com LM6132, LM6134 SNOS751F – APRIL 2000 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: LM6132 LM6134
at TA = 25°C and RL = 10 kΩ (unless otherwise specified) Figure 5-25. NF vs Source Resistance Figure 5-26. Gain and Phase vs Frequency, Old Die Figure 5-27. Gain and Phase vs Frequency, Old Die Figure 5-28. Gain and Phase vs Frequency, Old Die F r e q u e n c y ( H z ) Gain (dB) P h a s e ( ) - 2 0 3 0 0 4 5 2 0 6 0 4 0 7 5 6 0 9 0 8 0 1 0 5 1 0 0 1 2 0 1 2 0 1 3 5 1 4 0 1 5 0 1 6 0 1 6 5 1 8 0 1 8 0 1 0 m 1 0 0 m 1 1 0 1 0 0 1 k 1 0 k 1 0 0 k 1 M 1 0 M G a i n P h a s e Figure 5-29. Gain and Phase vs Frequency, New Die Figure 5-30. GBW vs Supply Voltage at 20 kHz LM6132, LM6134 SNOS751F – APRIL 2000 – REVISED JUNE 2026 www.ti.com
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5.10 Old Versus New Die Comparison
As of the publication of revision F of this data sheet, Texas Instruments has moved manufacturing of the die for LM6132 and LM6134 to a modern fabrication site. The two different die are referred to in this document as “old” (previous fabrication site) and “new” die. The die origin can be separated from the “Chip Source Origin” (CSO) parameter in the shipping information. The old die CSO is “GF6”, for the new die CSO is “RFB”. The old die information is maintained in this data sheet for comparison purposes, but all new manufacturing has moved to the new die. Table 5-1. Old Versus New Die Comparison Description Old Die New Die Minimum supply voltage 1.8V 2.7V Typical output voltage range for 100kΩ load (VS = 5V) 0.007V - 4.992V 0.03V - 4.97V Minimum output voltage range for 100kΩ load (VS = 5V) 0.017V - 4.98V 0.04V - 4.965V Output voltage slew architecture Standard slew architecture Slew-boosted architecture www.ti.com LM6132, LM6134 SNOS751F – APRIL 2000 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: LM6132 LM6134
6 Application and Implementation
6.1 Application Information
The LM6132 brings a new level of ease of use to op amp system design. Greater than rail-to-rail input voltage eliminates concern over exceeding the common-mode voltage range. Rail-to-rail output swing provides the maximum possible dynamic range at the output. This is particularly important when operating on low supply voltages. The high gain-bandwidth with low supply current opens new battery powered applications, where high power consumption previously reduced battery life to unacceptable levels. To take advantage of these features, keep some ideas in mind, which are outlined in subsequent sections. LM6132, LM6134 SNOS751F – APRIL 2000 – REVISED JUNE 2026 www.ti.com
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6.2 Typical Applications
6.2.1 Three Op Amp Instrumentation Amp with Rail-to-Rail Input and Output
Using the LM6134, a 3 op amp instrumentation amplifier with rail-to-rail inputs and rail to rail output can be made. These features make these instrumentation amplifiers an excellent choice for single supply systems. Some manufacturers use a precision voltage divider array of 5 resistors to divide the common-mode voltage to get an input range of rail-to-rail or greater. The problem with this method is that the method also divides the signal, so to even get unity gain, the amplifier must be run at high closed loop gains. This raises the noise and drift by the internal gain factor and lowers the input impedance. Any mismatch in these precision resistors reduces the CMR as well. Using the LM6134, all of these problems are eliminated. In this example, amplifiers A and B act as buffers to the differential stage ( Figure 6-1). These buffers assure that the input impedance is over 100M Ω and they eliminate the requirement for precision matched resistors in the input stage. The buffers also assure that the difference amp is driven from a voltage source. This is necessary to maintain the CMR set by the matching of R1–R2 with R3–R4. Figure 6-1. Instrumentation Amplifier
6.2.2 Flat Panel Display Buffering
Three features of the LM6132/34 make the device a superb choice for TFT LCD applications. First, the low current draw (360μA per amplifier at 5V) makes the device an excellent choice for battery powered applications such as in laptop computers. Second, since the device operates down to 2.7V, the device is a natural choice for next generation 3V TFT panels. Last, but not least, the large capacitive drive capability of the LM6132 comes in very handy in driving highly capacitive loads that are characteristic of LCD display drivers. The large capacitive drive capability of the LM6132/34 allows the device to be used as buffers for the gamma correction reference voltage inputs of resistor-DAC type column (Source) drivers in TFT LCD panels. This amplifier is also useful for buffering only the center reference voltage input of Capacitor-DAC type column (Source) drivers such as the LMC750X series. Since for VGA and SVGA displays, the buffered voltages must settle within approximately 4 μs, the well known technique of using a small isolation resistor in series with the amplifier's output very effectively dampens the ringing at the output. With the wide supply voltage range of 2.7V to 24V, the LM6132/34 can be used for a diverse range of applications. The system designer is thus able to select a single device type that serves many sub-circuits in the system, eliminating the need to specify multiple devices in the bill of materials. Along with the sister parts, the LM6142 and LM6152 that have the same wide supply voltage capability, choice of the LM6132 in a design eliminates the need to search for multiple sources for new designs. www.ti.com LM6132, LM6134 SNOS751F – APRIL 2000 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: LM6132 LM6134
7 Device and Documentation Support
7.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.
7.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.
7.3 Trademarks
TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.
7.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
7.5 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
8 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision E (September 2014) to Revision F (June 2026) Page LM6132, LM6134 SNOS751F – APRIL 2000 – REVISED JUNE 2026 www.ti.com
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- Changed maximum voltage output swing for 100kΩ load over temperature from 0.019V to 50mV from Changes from Revision D (February 2013) to Revision E (September 2014) Page Changes from Revision C (February 2013) to Revision D (February 2013) Page
9 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. www.ti.com LM6132, LM6134 SNOS751F – APRIL 2000 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: LM6132 LM6134
www.ti.com 6-Feb-2026 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) LM6132AIM/NOPB Obsolete Production SOIC (D) | 8 - - Call TI Call TI -40 to 85 LM61 32AIM LM6132AIMX/NOPB Active Production SOIC (D) | 8 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 85 LM61 32AIM LM6132AIMX/NOPB.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 85 LM61 32AIM LM6132AIMX/NOPB.B Active Production SOIC (D) | 8 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 85 LM61 32AIM LM6132BIMX/NOPB Active Production SOIC (D) | 8 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 85 LM61 32BIM LM6132BIMX/NOPB.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 85 LM61 32BIM LM6132BIMX/NOPB.B Active Production SOIC (D) | 8 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 85 LM61 32BIM LM6132BIN/NOPB Active Production PDIP (P) | 8 40 | TUBE Yes NIPDAU Level-1-NA-UNLIM -40 to 85 LM6132 BIN LM6132BIN/NOPB.A Active Production PDIP (P) | 8 40 | TUBE Yes NIPDAU Level-1-NA-UNLIM -40 to 85 LM6132 BIN LM6132BIN/NOPB.B Active Production PDIP (P) | 8 40 | TUBE Yes NIPDAU Level-1-NA-UNLIM -40 to 85 LM6132 BIN LM6134AIM/NOPB Obsolete Production SOIC (D) | 14 - - Call TI Call TI -40 to 85 LM6134AIM LM6134AIMX/NOPB Active Production SOIC (D) | 14 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 85 LM6134AIM LM6134AIMX/NOPB.A Active Production SOIC (D) | 14 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 85 LM6134AIM LM6134BIM/NOPB Obsolete Production SOIC (D) | 14 - - Call TI Call TI -40 to 85 LM6134BIM LM6134BIMX/NOPB Active Production SOIC (D) | 14 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 85 LM6134BIM LM6134BIMX/NOPB.A Active Production SOIC (D) | 14 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 85 LM6134BIM LM6134BIN/NOPB Active Production PDIP (N) | 14 25 | TUBE Yes NIPDAU Level-1-NA-UNLIM -40 to 85 LM6134BIN LM6134BIN/NOPB.A Active Production PDIP (N) | 14 25 | TUBE Yes NIPDAU Level-1-NA-UNLIM -40 to 85 LM6134BIN (1) Status: For more details on status, see our product life cycle. Addendum-Page 1
www.ti.com 6-Feb-2026 (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2
PACKAGE MATERIALS INFORMATION www.ti.com 10-Aug-2026 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION www.ti.com 10-Aug-2026 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM6132AIMX/NOPB SOIC D 8 2500 367.0 367.0 35.0 LM6132BIMX/NOPB SOIC D 8 2500 367.0 367.0 35.0 LM6134AIMX/NOPB SOIC D 14 2500 367.0 367.0 35.0 LM6134BIMX/NOPB SOIC D 14 2500 367.0 367.0 35.0 Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION www.ti.com 10-Aug-2026 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) LM6132BIN/NOPB P PDIP 8 40 502 14 11938 4.32 LM6132BIN/NOPB.A P PDIP 8 40 502 14 11938 4.32 LM6132BIN/NOPB.B P PDIP 8 40 502 14 11938 4.32 LM6134BIN/NOPB N PDIP 14 25 502 14 11938 4.32 LM6134BIN/NOPB.A N PDIP 14 25 502 14 11938 4.32 Pack Materials-Page 3
www.ti.com PACKAGE OUTLINE C TYP6.2 5.8
1.75 MAX
12X 1.27 14X 0.51 0.31 7.62 TYP0.25 0.13 0 - 8 0.25 0.10 0.25 GAGE PLANE 1.27 0.40 A NOTE 3 8.75 8.55 B NOTE 4 4.0 3.8 4220718/A 09/2016 SOIC - 1.75 mm max heightD0014A SMALL OUTLINE INTEGRATED CIRCUIT NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm, per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm, per side. 5. Reference JEDEC registration MS-012, variation AB. 1 14
0.25 C A B
0.1 C SEE DETAIL A DETAIL A TYPICAL SCALE 1.800
www.ti.com EXAMPLE BOARD LAYOUT (5.4)
0.07 MAX
0.07 MIN
14X (1.55) 14X (0.6) 12X (1.27) (R0.05) TYP 4220718/A 09/2016 SOIC - 1.75 mm max heightD0014A SMALL OUTLINE INTEGRATED CIRCUIT SYMM SYMM LAND PATTERN EXAMPLE SCALE:8X 7 8 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METALSOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED
www.ti.com EXAMPLE STENCIL DESIGN (5.4) 12X (1.27) 14X (0.6) 14X (1.55) 4220718/A 09/2016 SOIC - 1.75 mm max heightD0014A SMALL OUTLINE INTEGRATED CIRCUIT NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SYMM SYMM 7 8 SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:8X
www.ti.com PACKAGE OUTLINE C .228-.244 TYP [5.80-6.19] .069 MAX [1.75] 6X .050 [1.27] 8X .012-.020 [0.31-0.51] .150 [3.81] .005-.010 TYP [0.13-0.25] 0 - 8 .004-.010 [0.11-0.25] .010 [0.25].016-.050 [0.41-1.27] 4X (0 -15 ) A .189-.197 [4.81-5.00] NOTE 3 B .150-.157 [3.81-3.98] NOTE 4 4X (0 -15 ) (.041) [1.04] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. 1 8 .010 [0.25] C A B PIN 1 ID AREA SEATING PLANE .004 [0.1] C SEE DETAIL A DETAIL A TYPICAL SCALE 2.800
www.ti.com EXAMPLE BOARD LAYOUT .0028 MAX [0.07] ALL AROUND .0028 MIN [0.07] ALL AROUND (.213) [5.4] 6X (.050 ) [1.27] 8X (.061 ) [1.55] 8X (.024) [0.6] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METAL SOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS EXPOSED METAL OPENING SOLDER MASK METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SYMM 4 5 SEE DETAILS SYMM
www.ti.com EXAMPLE STENCIL DESIGN 8X (.061 ) [1.55] 8X (.024) [0.6] 6X (.050 ) [1.27] (.213) [5.4] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X SYMM SYMM 4 5
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