LM26001

LM26001/-Q1 1.5-A Switching Regulator With High-Efficiency Sleep Mode datasheet (Rev. I)

Document overview

• Manufacturer or author: Texas Instruments, Incorporated [SNVS430,I]
• PDF pages: 34

Technical content

L R1 C6 R4 D1 VDD EPR6 EN SYNC Product Folder Sample & Buy T echnical Documents Tools & Software Support & Community LM26001,LM26001-Q1 SNVS430I –MAY 2006–REVISED MARCH 2015 LM26001/-Q11.5-ASwitchingRegulatorWithHigh-EfficiencySleepMode

1 Features 3 Description

The LM26001 is a switching regulator designed for 1• LM26001-Q1 is an Automotive-Grade Product that the high-efficiency requirements of applications withis AEC-Q100 Grade 1 Qualified (–40°C to +125°C standby modes. The device features a low-currentOperating Junction Temperature) sleep mode to maintain efficiency under light-load

• High-Efficiency Sleep Mode conditions and current-mode control for accurate regulation over a wide input voltage range. Quiescent• 40-µA Typical Iq in Sleep Mode current is reduced to 10 µA typically in shutdown• 10-µA Typical Iq in Shutdown Mode mode and less than 40 µA in sleep mode. Forced• 3.0-V Minimum Input Voltage PWM mode is also available to disable sleep mode.
• 4.0-V to 38-V Continuous Input Range The LM26001 can deliver up to 1.5 A of continuous• 1.5% Reference Accuracy load current with a fixed current limit, through the
• Cycle-by-Cycle Current Limit internal N-channel switch. The part has a wide input voltage range of 4.0 V to 38 V and can operate with• Adjustable Frequency (150 kHz to 500 kHz) input voltages as low as 3 V during line transients.• Synchronizable to an External Clock Operating frequency is adjustable from 150 kHz to• Power Good Flag 500 kHz with a single resistor and can be• Forced PWM Function synchronized to an external clock.
• Adjustable Soft-Start Other features include Power Good, adjustable soft-• HTSSOP-16 Exposed Pad Package start, enable pin, input undervoltage protection, and
• Thermal Shut Down an internal bootstrap diode for reduced component count.

2 Applications

Device Information(1)

• Automotive Telematics PART NUMBER PACKAGE BODY SIZE (NOM)
• Navigation Systems LM26001 HTSSOP (16) 5.00 mm x 4.40 mm• In-Dash Instrumentation LM26001-Q1
• Battery-Powered Applications (1) For all available packages, see the orderable addendum at
• Standby Power for Home Gateways/Set-top the end of the datasheet. Boxes Typical Application Circuit An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

LM26001,LM26001-Q1 SNVS430I –MAY 2006–REVISED MARCH 2015 www.ti.com Table of Contents

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision H (November 2014) to Revision I Page Changes from Revision G (April 2013) to Revision H Page

• Added Pin Configuration and Functions section, Handling Rating table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information Changes from Revision F (April 2013) to Revision G Page

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9 FREQ

10 FPWM

11 SYNC

12 VBIAS

13 VDD

14 BOOT

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5 Pin Configuration and Functions

NO. NAME

1 VIN A Power supply input

2 VIN A Power supply input

3 PGOOD O Power Good pin. An open-drain output which goes high when the output voltage is greater than 92% of nominal. 4 EN I Enable is an analog level input pin. When pulled below 0.8 V, the device enters shutdown mode. 5 SS A Soft-start pin. Connect a capacitor from this pin to GND to set the soft-start time. 6 COMP A Compensation pin. Connect to a resistor capacitor pair to compensate the control loop. 7 FB A Feedback pin. Connect to a resistor divider between Vout and GND to set output voltage.

8 GND G Ground

9 FREQ A Frequency adjust pin. Connect a resistor from this pin to GND to set the operating frequency. 10 FPWM I FPWM is a logic level input pin. For normal operation, connect to GND. When pulled high, sleep mode operation is disabled. 11 SYNC I Frequency synchronization pin. Connect to an external clock signal for synchronized operation. SYNC must be pulled low for non-synchronized operation. 12 VBIAS A Connect to an external 3-V or greater supply to bypass the internal regulator for improved efficiency. If not used, VBIAS should be tied to GND. 13 VDD A The output of the internal regulator. Bypass with a minimum 1.0-µF capacitor. 14 BOOT A Bootstrap capacitor pin. Connect a 0.1-µF minimum ceramic capacitor from this pin to SW to generate the gate drive bootstrap voltage. 15 SW A Switch pin. The source of the internal N-channel switch. 16 SW A Switch pin. The source of the internal N-channel switch. EP EP G Exposed Pad thermal connection. Connect to GND. Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: LM26001 LM26001-Q1

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6 Specifications

6.1 Absolute Maximum Ratings(1)(2)

VIN –0.3 40 V SW(3) –0.5 40 V VDD –0.3 7 V VBIAS –0.3 10 V FB –0.3 6 V Voltages BOOT SW-0.3 SW+7 Vfrom the indicated PGOOD –0.3 7 V pins to FREQ –0.3 7 VGND SYNC –0.3 7 V EN –0.3 40 V FPWM –0.3 y7 V SS –0.3 7 V Power Dissipation(4)(5) 2.6 W Recomme Vapor Phase (70s) 215 °C nded Lead Infrared (15s) 220 °CTemperatu re Storage Tstg –65 150 °C temperatur e (1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Recommended Operating Conditions indicate conditions for which the device is intended to be functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the Electrical Characteristics. (2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications. (3) The absolute maximum specification applies to DC voltage. An extended negative voltage limit of -2V applies for a pulse of up to 1 µs, and –1 V for a pulse of up to 20 µs. (4) The maximum allowable power dissipation is a function of the maximum junction temperature, TJ_MAX, the junction-to-ambient thermal resistance, θJA, and the ambient temperature, TA. The maximum allowable power dissipation at any ambient temperature is calculated using: PD_MAX = (TJ_MAX - TA) /θJA. The maximum power dissipation of 2.6W is determined using TA = 25°C, θJA = 38°C/W, and TJ_MAX = 125°C. The number stated here reflects the maximum power dissipation for the package and not the device. (5) For Device Power Dissipation, please refer to section 10.3.

6.2 ESD Ratings - LM26001

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ± 2 kVCharged device model (CDM), per JEDEC specification JESD22-C101, ± 1V(ESD) Electrostatic discharge all pins(2) Machine model ± 200 V (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 ESD Ratings - LM26001-Q1

Human body model (HBM), per AEC Q100-002(1) ± 2 Corner pins (1, 8, 9, and ± 1 kVCharged device model (CDM), per AEC 16)V(ESD) Electrostatic discharge Q100-011 Other pins ± 1 Machine model ± 200 V (1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

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6.4 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT Operating Junction Temp. –40 125 °C Supply Voltage(1) 3.0 38 V (1) Below 4.0-V input, power dissipation may increase due to increased RDS(ON). Therefore, a minimum input voltage of 4.0 V is required to operate continuously within specification. A minimum of 3.9 V (typical) is also required for startup.

6.5 Thermal Information

THERMAL METRIC(1) PWP UNIT

16 PINS

RθJA Junction-to-ambient thermal resistance 38.8 RθJC(top) Junction-to-case (top) thermal resistance 23.0 RθJB Junction-to-board thermal resistance 16.7 °C/W ψJT Junction-to-top characterization parameter 0.6 ψJB Junction-to-board characterization parameter 16.4 RθJC(bot) Junction-to-case (bottom) thermal resistance 1.7 (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.6 Electrical Characteristics

Unless otherwise stated, Vin=12 V. Minimum and Maximum limits are ensured through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only.(1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SYSTEM ISD (2) Shutdown Current EN = 0 V 10.8 µA EN = 0 V, –40°C ≤ TJ ≤ 125°C 20 Iq_Sleep_VB (2) Quiescent Current Sleep mode, VBIAS = 5 V 38 µA Sleep mode, VBIAS = 5 V, –40°C 70 ≤ TJ ≤ 125°C Iq_Sleep_VDD Quiescent Current Sleep mode, VBIAS = GND 75 µA Sleep mode, VBIAS = GND, 125 –40°C ≤ TJ ≤ 125°C Iq_PWM_VB Quiescent Current PWM mode, VBIAS = 5 V 150 230 µA Iq_PWM_VDD Quiescent Current PWM mode, VBIAS = GND 0.65 0.85 mA IBIAS_Sleep (2) Bias Current Sleep mode, VBIAS = 5 V 33 µA Sleep mode, VBIAS = 5 V, –40°C 85 ≤ TJ ≤ 125°C IBIAS_PWM Bias Current PWM mode, VBIAS = 5 V 0.5 0.70 mA VFB Feedback Voltage 5 V < Vin < 38 V 1.234 V 5 V < Vin < 38 V, –40°C ≤ TJ ≤ 1.2155 1.2525 125°C IFB FB Bias Current ±200 nA ΔVOUT/ΔVIN Vout line regulation 5 V < Vin < 38 V 0.001 %/V ΔVOUT/ΔIOUT Vout load regulation 0.8 V < VCOMP < 1.15 V 0.07% VDD VDD output voltage 7 V < Vin < 35 V, IVDD= 0 mA to 5 5.95 V mA 7 V < Vin < 35 V, IVDD= 0 mA to 5 5.50 6.50 mA, –40°C ≤ TJ ≤ 125°C (1) All room temperature limits are 100% production tested. All limits at temperature extremes are ensured through correlation using standard Statistical Quality Control (SQC) methods. All limits are used to calculate Average Outgoing Quality Level (AOQL). (2) Iq and ISD specify the current into the VIN pin. IBIAS is the current into the VBIAS pin when the VBIAS voltage is greater than 3 V. All quiescent current specifications apply to non-switching operation. Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: LM26001 LM26001-Q1

LM26001,LM26001-Q1 SNVS430I –MAY 2006–REVISED MARCH 2015 www.ti.com Electrical Characteristics (continued) Unless otherwise stated, Vin=12 V. Minimum and Maximum limits are ensured through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only.(1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ISS_Source Soft-start source current 2.2 µA Vbias_th VBIAS On Voltage Specified at IBIAS = 92.5% of full 2.64 2.9 3.07 V value SWITCHING RDS(ON) Switch on Resistance Isw = 1A 0.2 Ω Isw = 1A, –40°C ≤ TJ ≤ 125°C 0.12 0.42 Isw_off Switch off state leakage current Vin = 38 V, VSW = 0 V 0.002 µA Vin = 38 V, VSW = 0 V, –40°C ≤ 5.0 TJ ≤ 125°C fsw Switching Frequency RFREQ = 62k, 124k, 240k ±10% VFREQ FREQ voltage 1.0 V fSW range Switching Frequency range –40°C ≤ TJ ≤ 125°C 150 500 kHz VSYNC Sync pin threshold SYNC rising 1.2 V SYNC rising, –40°C ≤ TJ ≤ 125°C 1.6 SYNC falling 1.1 SYNC falling, –40°C ≤ TJ ≤ 125°C 0.8 Sync pin hysteresis 114 mV ISYNC SYNC leakage current 6 nA FSYNC_UP Upper frequency synchronization range As compared to nominal fSW, 30% –40°C ≤ TJ ≤ 125°C FSYNC_DN Lower frequency synchronization range As compared to nominal fSW, –20% –40°C ≤ TJ ≤ 125°C TOFFMIN Minimum Off-time 365 ns TONMIN Minimum On-time 155 ns THSLEEP_HYS Sleep mode threshold hysteresis VFB rising, % of THWAKE 101.2% THWAKE Wake up threshold Measured at falling FB, COMP = 1.234 V 0.6 V IBOOT BOOT pin leakage current BOOT = 16 V, SW = 10 V 0.0006 µA BOOT = 16 V, SW = 10 V, –40°C 5.0 ≤ TJ ≤ 125°C PROTECTION ILIMPK Peak Current Limit 2.5 A VFB_SC Short circuit frequency foldback Measured at FB falling 0.87 V threshold F_min_sc Min Frequency in foldback VFB < 0.3 V 71 kHz VTH_PGOOD Power Good Threshold Measured at FB, PGOOD rising 92% Measured at FB, PGOOD rising, 89% 95% –40°C ≤ TJ ≤ 125°C PGOOD hysteresis 2% 7% 8% IPGOOD_HI PGOOD leakage current PGOOD = 5 V 0.2 nA RDS_PGOOD PGOOD on resistance PGOOD sink current = 500 µA 64 Ω

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LM26001,LM26001-Q1 www.ti.com SNVS430I –MAY 2006–REVISED MARCH 2015 Electrical Characteristics (continued) Unless otherwise stated, Vin=12 V. Minimum and Maximum limits are ensured through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only.(1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VUVLO Under-voltage Lock-Out Threshold Vin falling , shutdown, VDD = VIN 2.9 V Vin falling , shutdown, VDD = VIN, 2.60 3.20 –40°C ≤ TJ ≤ 125°C Vin rising, soft-start, VDD = VIN 3.9 Vin rising, soft-start, VDD = VIN, 3.60 4.20 –40°C ≤ TJ ≤ 125°C TSD Thermal Shutdown Threshold 160 °C θJA Thermal resistance Power dissipation = 1W, 0 lfpm air 38 °C/W flow LOGIC VthEN Enable Threshold voltage 1.2 V Enable hysteresis 120 mV IEN_Source EN source current EN = 0 V 4.5 µA VTH_FPWM FPWM threshold 1.2 V IFPWM FPWM leakage current FPWM = 5 V 35 nA EA gm Error amp trans-conductance 670 µmho –40°C ≤ TJ ≤ 125°C 400 1000 ICOMP COMP source current VCOMP = 0.9 V 56 µA COMP sink current VCOMP = 0.9 V 56 µA VCOMP COMP pin voltage range 0.64 1.27 V Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: LM26001 LM26001-Q1

6.7 Typical Characteristics

Unless otherwise specified the following conditions apply: VIN = 12 V, TJ = 25°C. Figure 1. VFB vs Temperature Figure 2. VFB vs Vin (IDC = 300 mA) Figure 4. IQ and IVBIAS vs Temperature (PWM Mode)Figure 3. IQ and IVBIAS vs Temperature (Sleep Mode) Figure 5. Normalized Switching Frequency vs Temperature Figure 6. UVLO Threshold vs Temperature (VDD = VIN)

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Unless otherwise specified the following conditions apply: VIN = 12 V, TJ = 25°C. Figure 13. Low Input Voltage Dropout Nominal VOUT = 5 V

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7 Detailed Description

7.1 Overview

Figure 14. PWM Waveforms 1-A Load, Vin = 12 V

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 Sleep Mode

switching and output voltage waveforms in sleep mode. Figure 15. Sleep Mode Waveforms 25-mA Load, Vin = 12 V Where Imin = Ilim/16 (2.5A/16 typically) and D = duty cycle, defined as (Vout + Vdiode)/Vin. mode threshold varies with frequency, inductance, and duty cycle as shown in Figure 16. Figure 16. Sleep Mode Threshold vs Vin Vout = 3.3 V Where Dwake is the percentage of time awake when the load current is below the sleep threshold.

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And Io is the sum of Iload, Ibias, and current through the feedback resistors. Characteristics. If VBIAS is connected to ground, use the same equation with Ibias equal to zero and Iq_Sleep_VDD.

7.3.2 FPWM

positive current always flows in the inductor. Typical discontinuous operation waveforms are shown in Figure 17. Figure 17. Discontinuous Mode Waveforms 75-mA Load, Vin = 12 V condition from occurring. However, the FPWM sleep threshold is much lower than in normal operation.

7.3.3 Enable

be left open for always-on operation. When open, EN will be pulled up to VIN. driven externally with a maximum voltage of 38V or VIN + 15V, whichever is lower.

7.3.4 Soft-Start

(Vin /cb1 Vout) x Vout fsw x L x VinIripple = Iripple 2Iloadmax = 1.85A - Iss x tss 1.234VCss = LM26001,LM26001-Q1 SNVS430I –MAY 2006–REVISED MARCH 2015 www.ti.com Feature Description (continued) (4) Where tss is the desired soft-start time and Iss is the soft-start source current. During soft-start, current limit and synchronization remain in effect, while sleep mode and frequency foldback are disabled. Soft-start mode ends when the SS pin voltage reaches 1.23 V typical. At this point, output voltage control is transferred to the FB pin and the SS pin is discharged.

7.3.5 Current Limit

The peak current limit is set internally by directly measuring peak inductor current through the internal switch. To ensure accurate current sensing, VIN should be bypassed with a minimum 1-µF ceramic capacitor placed directly at the pin. When the inductor current reaches the current limit threshold, the internal FET turns off immediately allowing inductor current to ramp down until the next cycle. This reduction in duty cycle corresponds to a reduction in output voltage. The current limit comparator is disabled for less than 100 ns at the leading edge for increased immunity to switching noise. Because the current limit monitors peak inductor current, the DC load current limit threshold varies with inductance and frequency. Assuming a minimum current limit of 1.85A, maximum load current can be calculated as follows: (5) Where Iripple is the peak-to-peak inductor ripple current, calculated as shown below: (6) To find the worst case (lowest) current limit threshold, use the maximum input voltage and minimum current limit specification. During high over-current conditions, such as output short circuit, the LM26001 employs frequency foldback as a second level of protection. If the feedback voltage falls below the short circuit threshold of 0.9 V, operating frequency is reduced, thereby reducing average switch current. This is especially helpful in short circuit conditions, when inductor current can rise very high during the minimum on-time. Frequency reduction begins at 20% below the nominal frequency setting. The minimum operating frequency in foldback mode is 71 kHz typical. If the FB voltage falls below the frequency foldback threshold during frequency synchronized operation, the SYNC function is disabled. Operating frequency versus FB voltage in short circuit conditions is shown in the Typical Characteristics section. Under conditions where the on time is close to minimum (less than 200 nsec typically), such as high input voltage and high switching frequency, the current limit may not function properly. This is because the current limit circuit cannot reduce the on-time below minimum which prevents entry into frequency foldback mode. There are two ways to ensure proper current limit and foldback operation under high input voltage conditions. First, the operating frequency can be reduced to increase the nominal on time. Second, the inductor value can be increased to slow the current ramp and reduce the peak over-current.

7.3.6 Frequency Adjustment and Synchronization

The switching frequency of the LM26001 can be adjusted between 150 kHz and 500 kHz using a single external resistor. This resistor is connected from the FREQ pin to ground as shown in the typical application. The resistor value can be calculated with the following empirically derived equation: RFREQ = (6.25 x 1010) x fSW -1.042 (7)

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Figure 18. Switching Frequency vs RFREQ Considerations and TSD section.

7.3.7 VBIAS

added benefit of reducing power dissipation within the device.

7.3.8 Low VIN Operation and UVLO

operation within specification. externally, the pin is not recommended for loads greater than 1 mA.

of seven off pulses, effectively increasing the duty cycle and thus minimizing the dropout from input to output. Typical off-pulse skipping waveforms are shown in Figure 19. Figure 19. Off-pulse Skipping Waveforms Vin = 3.5 V, Vnom = 3.3 V, fnom = 305 kHz holding up VDD, a larger cap can also reduce the RDS(ON) (and dropout voltage) in low VIN conditions. may be triggered by VDD even though the VIN voltage is above the UVLO threshold. and VDD voltage rise above 3.9 V (typical) the device will restart from softstart mode.

7.3.9 PGOOD

improved noise immunity, there is a 5 µs delay between the PGOOD threshold and the PGOOD pin going low.

7.4 Device Functional Modes

The LM26001 has three basic operation mode: Shutdown, Sleep or light load operation and full operation. quiescent current minimized See Enable for more details. operation in sleep mode as well as entering and exiting sleep mode. See Sleep Mode. When the part in enabled and the output load is higher, the part will be in full PWM operation. reduces the operating frequency to protect from short circuits. See Current Limit.

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8 Applications and Implementation

validate and test their design implementation to confirm system functionality.

8.1 Application Information

steps required for designing a successful application with the LM26001 from component selection to layout.

8.2 Typical Application

design criteria given in the following sections. Figure 20. Example Circuit 1.5A Max, 305 kHz

8.2.1 Design Requirements

8.2.2 Detailed Design Procedure

8.2.2.1 Setting Output Voltage

/c27Vt /c27It Re MAX = (Vin /cb1 Vout) x Vout x Re Vin x fsw x VripLMIN = Iripple 2Ipeak = Iload + (Vin /cb1 Vout) x Vout fsw x L x VinIripple = R2 = Vout Vfb/ca9 /ca7 /cb9 /cb7 LM26001,LM26001-Q1 SNVS430I –MAY 2006–REVISED MARCH 2015 www.ti.com (9) Where Vfb = 1.234V typically. A maximum value of 150kΩ is recommended for the sum of R1 and R2. As input voltage decreases towards the nominal output voltage, the LM26001 can skip up to seven off-pulses as described in the Low VIN Operation and UVLO section. In low output voltage applications, if the on-time reaches TonMIN, the device will skip on-pulses to maintain regulation. There is no limit to the number of pulses that are skipped. In this mode of operation, however, output ripple voltage may increase slightly.

8.2.2.2 Inductor

The output inductor should be selected based on inductor ripple current. The amount of inductor ripple current compared to load current, or ripple content, is defined as Iripple/Iload. Ripple content should be less than 40%. Inductor ripple current, Iripple, can be calculated as shown below: (10) Larger ripple content increases losses in the inductor and reduces the effective current limit. Larger inductance values result in lower output ripple voltage and higher efficiency, but a slightly degraded transient response. Lower inductance values allow for smaller case size, but the increased ripple lowers the effective current limit threshold. Remember that inductor value also affects the sleep mode threshold as shown in Figure 16. When choosing the inductor, the saturation current rating must be higher than the maximum peak inductor current and the RMS current rating should be higher than the maximum load current. Peak inductor current, Ipeak, is calculated as: (11) For example, at a maximum load of 1.5A and a ripple content of 40%, peak inductor current is equal to 1.8A which is safely below the minimum current limit of 1.85A. By increasing the inductor size, ripple content and peak inductor current are lowered, which increases the current limit margin. The size of the output inductor can also be determined using the desired output ripple voltage, Vrip. The equation to determine the minimum inductance value based on Vrip is as follows: (12) Where Re is the ESR of the output capacitors, and Vrip is a peak-to-peak value. This equation assumes that the output capacitors have some amount of ESR. It does not apply to ceramic output capacitors. If this method is used, ripple content should still be verified to be less than 40%.

8.2.2.3 Output Capacitor

The primary criterion for selecting an output capacitor is equivalent series resistance, or ESR. ESR (Re) can be selected based on the requirements for output ripple voltage and transient response. Once an inductor value has been selected, ripple voltage can be calculated for a given Re using the equation above for Lmin. Lower ESR values result in lower output ripple. Re can also be calculated from the following equation: (13)

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Irms = Vin Vout x (Vin /cb1 Vout)Iload x C MIN = (/c27 Vt)2 - (/c27 It x Re)2 /c27 Vt -L x/ca9/ca7 /ca9/ca7 Vout x Re LM26001,LM26001-Q1 www.ti.com SNVS430I –MAY 2006–REVISED MARCH 2015 Where ΔVt is the allowed voltage excursion during a load transient, and ΔIt is the maximum expected load transient. If the total ESR is too high, the load transient requirement cannot be met, no matter how large the output capacitance. If the ESR criteria for ripple voltage and transient excursion cannot be met, more capacitors should be used in parallel. For non-ceramic capacitors, the minimum output capacitance is of secondary importance, and is determined only by the load transient requirement. If there is not enough capacitance, the output voltage excursion will exceed the maximum allowed value even if the maximum ESR requirement is met. The minimum capacitance is calculated as follows: (14) It is assumed the total ESR, Re, is no greater than ReMAX. Also, it is assumed that L has already been selected. Generally speaking, the output capacitance requirement decreases with Re, ΔIt, and L. A typical value greater than 100 µF works well for most applications.

8.2.2.4 Input Capacitor

In a switching converter, very fast switching pulse currents are drawn from the input rail. Therefore, input capacitors are required to reduce noise, EMI, and ripple at the input to the LM26001. Capacitors must be selected that can handle both the maximum ripple RMS current at highest ambient temperature as well as the maximum input voltage. The equation for calculating the RMS input ripple current is shown below: (15) For noise suppression, a ceramic capacitor in the range of 1.0 µF to 10 µF should be placed as close as possible to the VIN pin. A larger, high ESR input capacitor should also be used. This capacitor is recommended for damping input voltage spikes during power-on and for holding up the input voltage during transients. In low input voltage applications, line transients may fall below the UVLO threshold if there is not enough input capacitance. Both tantalum and electrolytic type capacitors are suitable for the bulk capacitor. However, large tantalums may not be available for high input voltages and their working voltage must be derated by at least 2X.

8.2.2.5 Bootstrap

The drive voltage for the internal switch is supplied via the BOOT pin. This pin must be connected to a ceramic capacitor, Cboot, from the switch node, shown as C4 in the typical application. The LM26001 provides the VDD voltage internally, so no external diode is needed. A maximum value of 0.1 uF is recommended for Cboot. Values smaller than 0.01 uF may result in insufficient hold up time for the drive voltage and increased power dissipation. During low Vin operation, when the on-time is extended, the bootstrap capacitor is at risk of discharging. If the Cboot capacitor is discharged below approximately 2.5V, the LM26001 enters a high frequency re-charge mode. The Cboot cap is re-charged via the LG synchronous FET shown in the block diagram. Switching returns to normal when the Cboot cap has been recharged.

8.2.2.6 Catch Diode

When the internal switch is off, output current flows through the catch diode. Alternately, when the switch is on, the diode sees a reverse voltage equal to Vin. Therefore, the important parameters for selecting the catch diode are peak current and peak inverse voltage. The average current through the diode is given by: IDAVE = Iload x (1-D) (16) Where D is the duty cycle, defined as Vout/Vin. The catch diode conducts the largest currents during the lowest duty cycle. Therefore IDAVE should be calculated assuming maximum input voltage. The diode should be rated to handle this current continuously. For over-current or short circuit conditions, the catch diode should be rated to handle peak currents equal to the peak current limit. The peak inverse voltage rating of the diode must be greater than maximum input voltage. Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback 19 Product Folder Links: LM26001 LM26001-Q1

protecting the SW pin against large negative voltage spikes.

8.2.2.7 Compensation

the feedback transfer function (the compensation network). frequency, i.e. 60 kHz in the case of 300 kHz switching frequency. Figure 21. Control-Output Transfer Function

1. Place a pole at 0 Hz (fpc)
2. Place a second pole at fz (fpc1)

the feedback response will then result in a nearly continuous –20db/decade slope. Figure 22. Feedback Transfer Function

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switching frequency. The effects of slope compensation and current sense gain are included in this equation. exact transfer function, use 0.2V/V sense amp gain and 36mVp-p slope compensation. Figure 23. Compensation Network

1. The compensation network automatically introduces a low frequency pole (fpc), which is close to 0Hz.
2. Once the fp range is determined, R5 should be calculated using:
3. Next, place a zero (fzc) near fp using C8. C8 can be determined with the following equation:
4. A second pole (fpc1) can also be placed at fz. This pole can be created with a single capacitor, C9. The

somewhat below the fpz1 frequency set by C9. However, if C10 is too large, it will have no effect.

8.2.3 Application Curves

Figure 24. Startup Waveforms Figure 25. Load Transient Response

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LM26001,LM26001-Q1 www.ti.com SNVS430I –MAY 2006–REVISED MARCH 2015

9 Power Supply Recommendations

The LM26001 is designed to operate from various DC power supply including a car battery. If so, VIN input should be protected from reversal voltage and voltage dump over 48 Volts. The impedance of the input supply rail should be low enough that the input current transient does not cause drop below VIN UVLO level. If the input supply is connected by using long wires, additional bulk capacitance may be required in addition to normal input capacitor.

10 Layout

10.1 Layout Guidelines

Good board layout is critical for switching regulators such as the LM26001. First, the ground plane area must be sufficient for thermal dissipation purposes, and second, appropriate guidelines must be followed to reduce the effects of switching noise. Switch mode converters are very fast switching devices. In such devices, the rapid increase of input current combined with parasitic trace inductance generates unwanted Ldi/dt noise spikes at the SW node and also at the VIN node. The magnitude of this noise tends to increase as the output current increases. This parasitic spike noise may turn into electromagnetic interference (EMI), and can also cause problems in device performance. Therefore, care must be taken in layout to minimize the effect of this switching noise. The current sensing circuit in current mode devices can be easily affected by switching noise. This noise can cause duty cycle jitter which leads to increased spectral noise. Although the LM26001 has 100ns blanking time at the beginning of every cycle to ignore this noise, some noise may remain after the blanking time. Following the important guidelines below will help minimize switching noise and its effect on current sensing. The switch node area should be as small as possible. The catch diode, input capacitors, and output capacitors should be grounded to a large ground plane, with the bulk input capacitor grounded as close as possible to the catch diode anode. Additionally, the ground area between the catch diode and bulk input capacitor is very noisy and should be somewhat isolated from the rest of the ground plane. A ceramic input capacitor must be connected as close as possible to the VIN pin and grounded close to the GND pin. Often this capacitor is most easily located on the bottom side of the pcb. If placement close to the GND pin is not practical, the ceramic input capacitor can also be grounded close to the catch diode ground. The above layout recommendations are illustrated below in Figure 26. It is a good practice to connect the EP, GND pin, and small signal components (COMP, FB, FREQ) to a separate ground plane, shown in Figure 26 as EP GND, and in the schematics as a signal ground symbol. Both the exposed pad and the GND pin must be connected to ground. This quieter plane should be connected to the high current ground plane at a quiet location, preferably near the Vout ground as shown by the dashed line in Figure 26. The EP GND plane should be made as large as possible, since it is also used for thermal dissipation. Several vias can be placed directly below the EP to increase heat flow to other layers when they are available. The recommended via hole diameter is 0.3mm. The trace from the FB pin to the resistor divider should be short and the entire feedback trace must be kept away from the inductor and switch node. See AN-1229 SIMPLE SWITCHER® PCB Layout Guidelines, SNVA054, for more information regarding PCB layout for switching regulators. Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback 23 Product Folder Links: LM26001 LM26001-Q1

10.2 Layout Example

Figure 26. Example PCB Layout

10.3 Thermal Considerations and TSD

determine the maximum allowable load current. board type and metallization area. If the power dissipation remains above the maximum allowable level, device temperature will continue to rise. this point, the device restarts in soft-start mode.

24 Submit Documentation Feedback Copyright © 2006–2015, Texas Instruments Incorporated

11 Device and Documentation Support

11.1 Documentation Support

11.1.1 Related Documentation

11.2 Related Links

resources, tools and software, and quick access to sample or buy. Table 1. Related Links

11.3 Trademarks

All trademarks are the property of their respective owners.

11.4 Electrostatic Discharge Caution

during storage or handling to prevent electrostatic damage to the MOS gates.

11.5 Glossary

This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 10-Nov-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) LM26001MXA/NOPB Active Production HTSSOP (PWP) | 16 92 | TUBE Yes Call TI | Sn Level-1-260C-UNLIM -40 to 125 L26001 MXA LM26001MXA/NOPB.A Active Production HTSSOP (PWP) | 16 92 | TUBE Yes Call TI Level-1-260C-UNLIM -40 to 125 L26001 MXA LM26001MXA/NOPB.B Active Production HTSSOP (PWP) | 16 92 | TUBE Yes Call TI Level-1-260C-UNLIM -40 to 125 L26001 MXA LM26001MXAX/NOPB Active Production HTSSOP (PWP) | 16 2500 | LARGE T&R Yes Call TI | Sn Level-1-260C-UNLIM -40 to 125 L26001 MXA LM26001MXAX/NOPB.A Active Production HTSSOP (PWP) | 16 2500 | LARGE T&R Yes Call TI Level-1-260C-UNLIM -40 to 125 L26001 MXA LM26001MXAX/NOPB.B Active Production HTSSOP (PWP) | 16 2500 | LARGE T&R Yes Call TI Level-1-260C-UNLIM -40 to 125 L26001 MXA LM26001QMXA/NOPB Active Production HTSSOP (PWP) | 16 92 | TUBE Yes Call TI | Sn Level-1-260C-UNLIM -40 to 125 L26001 QMXA LM26001QMXA/NOPB.A Active Production HTSSOP (PWP) | 16 92 | TUBE Yes Call TI Level-1-260C-UNLIM -40 to 125 L26001 QMXA LM26001QMXA/NOPB.B Active Production HTSSOP (PWP) | 16 92 | TUBE Yes Call TI Level-1-260C-UNLIM -40 to 125 L26001 QMXA LM26001QMXAX/NOPB Active Production HTSSOP (PWP) | 16 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 L26001 QMXA LM26001QMXAX/NOPB.A Active Production HTSSOP (PWP) | 16 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 L26001 QMXA LM26001QMXAX/NOPB.B Active Production HTSSOP (PWP) | 16 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 L26001 QMXA (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. Addendum-Page 1

www.ti.com 10-Nov-2025 (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF LM26001, LM26001-Q1 :

• Catalog : LM26001
• Automotive : LM26001-Q1 NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 10-Aug-2026 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 10-Aug-2026 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM26001MXAX/NOPB HTSSOP PWP 16 2500 367.0 367.0 35.0 LM26001QMXAX/NOPB HTSSOP PWP 16 2500 367.0 367.0 35.0 Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 10-Aug-2026 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) LM26001MXA/NOPB PWP HTSSOP 16 92 495 8 2514.6 4.06 LM26001MXA/NOPB.A PWP HTSSOP 16 92 495 8 2514.6 4.06 LM26001MXA/NOPB.B PWP HTSSOP 16 92 495 8 2514.6 4.06 LM26001QMXA/NOPB PWP HTSSOP 16 92 495 8 2514.6 4.06 LM26001QMXA/NOPB.A PWP HTSSOP 16 92 495 8 2514.6 4.06 LM26001QMXA/NOPB.B PWP HTSSOP 16 92 495 8 2514.6 4.06 Pack Materials-Page 3

www.ti.com PACKAGE OUTLINE C TYP6.6 6.2 14X 0.65 16X 0.30 0.19 4.55 (0.15) TYP 0 - 8 0.15 0.05 3.3 2.7 3.3 2.7 2X 1.34 MAX NOTE 5

1.2 MAX

(1) 0.25 GAGE PLANE 0.75 0.50 A NOTE 3 5.1 4.9 B 4.5 4.3 4X 0.166 MAX NOTE 5 4214868/A 02/2017 PowerPAD HTSSOP - 1.2 mm max heightPWP0016A PLASTIC SMALL OUTLINE NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. Reference JEDEC registration MO-153. 5. Features may not be present. PowerPAD is a trademark of Texas Instruments. TM 1 16

0.1 C A B

0.1 C SEE DETAIL A DETAIL A TYPICAL SCALE 2.400 THERMAL PAD

www.ti.com EXAMPLE BOARD LAYOUT (5.8)

0.05 MAX

0.05 MIN

16X (1.5) 16X (0.45) 14X (0.65) (3.4) NOTE 9 (5) NOTE 9 (3.3) (3.3) ( 0.2) TYP VIA (1.1) TYP (1.1) TYP 4214868/A 02/2017 PowerPAD HTSSOP - 1.2 mm max heightPWP0016A PLASTIC SMALL OUTLINE SYMM SYMM SEE DETAILS LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:10X 8 9 METAL COVERED BY SOLDER MASK SOLDER MASK DEFINED PAD NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. 8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature 9. Size of metal pad may vary due to creepage requirement. TM METALSOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS PADS 1-16 EXPOSED METAL SOLDER MASK DEFINED SOLDER MASK METAL UNDER SOLDER MASK OPENING EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN 16X (1.5) 16X (0.45) (3.3) (3.3) BASED ON

0.125 THICK

14X (0.65) (R0.05) TYP (5.8) 4214868/A 02/2017 PowerPAD HTSSOP - 1.2 mm max heightPWP0016A PLASTIC SMALL OUTLINE 2.79 X 2.790.175 3.01 X 3.010.15 3.3 X 3.3 (SHOWN)0.125 3.69 X 3.690.1 SOLDER STENCIL OPENING STENCIL THICKNESS NOTES: (continued) 10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 11. Board assembly site may have different recommendations for stencil design. TM SYMM SYMM 8 9 BASED ON METAL COVERED SEE TABLE FOR DIFFERENT OPENINGS FOR OTHER STENCIL THICKNESSES SOLDER PASTE EXAMPLE EXPOSED PAD 100% PRINTED SOLDER COVERAGE BY AREA SCALE:10X

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