LM1771 Low-Voltage Synchronous Buck Controller With Precision Enable and No External Compensation datasheet (Rev. D)
Document overview
- Manufacturer or author: Texas Instruments, Incorporated [SNVS446,D]
- PDF pages: 32
Technical content
Sample & Buy T echnical Documents Tools & Software Support & Community LM1771 SNVS446D –JUNE 2006–REVISED JANUARY 2016 LM1771Low-VoltageSynchronousBuckControllerWithPrecisionEnableandNo ExternalCompensation
1 Features 3 Description
The LM1771 device is an efficient synchronous buck 1• Input Voltage Range of 2.8 V to 5.5 V switching controller with a precision enable requiring• 0.8-V Reference Voltage no external compensation. The constant ON-time
- Precision Enable control scheme provides a simple design free of compensation components, allowing minimal• No Compensation Required component count and board space. The precision• Constant Frequency Across Input Range enable pin allows flexibility in sequencing multiple• Low Quiescent Current of 400 µA rails and setting UVLO. The LM1771 also incorporates a unique input feedforward to maintain a• Internal Soft-Start constant frequency independent of the input voltage.• Short Circuit Protection The LM1771 is optimized for a low-voltage input• 6-Pin WSON Package and 8-Pin VSSOP Package range of 2.8 V to 5.5 V and can provide an adjustable output as low as 0.8 V. Driving an external high-side
2 Applications PFET and low-side NFET, it can provide efficiencies
as high as 95%.• Simple-to-Design, High-Efficiency, Step-Down Switching Regulators Three versions of the LM1771 are available depending on the switching frequency desired for the• FPGAs, DSPs, and ASIC Power Supplies application. Nominal switching frequencies are in the• Set-Top Boxes range of 100 kHz to 1000 kHz.• Cable Modems
- Printers Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM)• Digital Video Recorders WSON (6) 3.00 mm × 3.00 mm• Servers LM1771 VSSOP (8) 3.00 mm × 3.00 mm• Graphic Cards (1) For all available packages, see the orderable addendum at the end of the data sheet. Typical Application Circuit An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.
SNVS446D –JUNE 2006–REVISED JANUARY 2016 www.ti.com Table of Contents
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision C (April 2013) to Revision D Page
- Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Changes from Revision B (April 2013) to Revision C Page
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5 Pin Configuration and Functions
TYPE(1) DESCRIPTION NAME WSON VSSOP Die Attach Pad is internally connected to GND, but it cannot be used as theDAP — — GND primary GND connection EN 6 8 I Enable Pin FB 1 1 A Feedback Pin GND 2 2, 3 GND Ground HG 3 4 AO PFET Gate Drive LG 4 5 AO NFET Gate Drive VIN 5 6, 7 PWR Input Supply (1) I = Input, A = Analog, GND = Ground, AO = Analog output, PWR = Power Copyright © 2006–2016, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: LM1771
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6 Specifications
6.1 Absolute Maximum Ratings
See (1) (2) MIN MAX UNIT VIN –0.3 6 V EN, FB, HG, LG –0.3 VIN V Junction temperature 150 °C Lead temperature Soldering, 10 sec 260 °C Storage temperature, Tstg –65 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications.
6.2 ESD Ratings
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
VIN to GND 2.8 5.5 V Junction temperature, TJ −40 125 °C
6.4 Thermal Information
THERMAL METRIC(1) NGG (WSON) DGK (VSSOP) UNIT
6 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 52.8 169.2 °C/W RθJC(top) Junction-to-case (top) thermal resistance 51.4 59.7 °C/W RθJB Junction-to-board thermal resistance 27.2 89.3 °C/W ψJT Junction-to-top characterization parameter 0.7 7.0 °C/W ψJB Junction-to-board characterization parameter 27.3 87.9 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 7.4 N/A °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.
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6.5 Electrical Characteristics
Specifications are for TJ = 25°C. All maximum and minimum limits apply over the full junction temperature range (−40°C to +125°C), unless otherwise specified. Minimum and maximum limits are ensured through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C and are provided for reference purposes only. Unless otherwise specified, VIN = 3.3 V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VFB Feedback pin voltage 0.782 0.8 0.818 V IQ Quiescent current VFB = 0.9 V 400 700 µA LM1771S - (500 ns) 0.4 0.5 0.6 TON Switch ON-time LM1771T - (1000 ns) 0.8 1 1.2 µs LM1771U - (2000 ns) 1.6 2 2.4 LM1771S - (500 ns) 150 250 TOFF_MIN Minimum OFF-time LM1771T - (1000 ns) 135 225 ns LM1771U - (2000 ns) 120 220 TD Gate drive dead-time 70 ns VIH_EN EN pin rising threshold 1.15 1.2 1.25 V VEN_HYS EN pin hysteresis 50 200 mV IFB Feedback pin bias current VFB = 0.9 V 50 nA VUVLO Undervoltage lockout VIN Rising Edge 2.65 2.8 V VUVLO_HYS Undervoltage lockout hysteresis 50 mV VSC_TH Feedback pin short circuit latch 0.42 0.55 0.65 Vthreshold RDS(ON) 1 HG FET driver pullup ON-resistance IHG = 20 mA 4 Ω RDS(ON) 2 HG FET driver pulldown ON-resistance IHG = 20 mA 6 Ω RDS(ON) 3 LG FET driver pullup ON-resistance ILG = 20 mA 4 Ω RDS(ON) 4 LG FET driver pulldown ON-resistance ILG = 20 mA 6 Ω Copyright © 2006–2016, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: LM1771
6.6 Typical Characteristics
Figure 1. TON vs VIN (LM1771S) Figure 2. TON vs VIN (LM1771T) Figure 3. TON vs VIN (LM1771U) Figure 4. TON vs Temperature (LM1771S) Figure 5. TON vs Temperature (LM1771T) Figure 6. TON vs Temperature (LM1771U)
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Figure 13. Quiescent Current vs Temperature Figure 14. Dead-Time vs Temperature Figure 15. Efficiency vs IOUT (LM1771T) Figure 16. Efficiency vs IOUT (LM1771U) Figure 17. Efficiency vs IOUT (LM1771U) Figure 18. Efficiency vs IOUT (LM1771S)
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0.8V Q Vin LM1771 REGULATION COMPARATOR Q OFF TIMER GND HG LG Level Shift and Shoot Through Protection Low-Side Driver SHORT CIRCUIT PROTECTION 0.55 V /Soft-Start UVLO UVLO SD SD Q Q R S Q Q R S 1.2 V EN ENABLE COMPARATOR LM1771 www.ti.com SNVS446D –JUNE 2006–REVISED JANUARY 2016
7 Detailed Description
7.1 Overview
The LM1771 synchronous buck controller has a control scheme that is referred to as adaptive ON-time control. This topology relies on a fixed switch ON-time to regulate the output voltage. This ON-time is internally set by EEPROM and is available with three different set-points to allow for different frequency options. The LM1771 automatically adjusts the ON-time during operation inversely with the input voltage (VIN) to maintain a constant frequency. Therefore the switching frequency during continuous conduction mode is independent of the inductor and capacitor size unlike hysteretic switchers. At the beginning of the cycle, the LM1771 turns on the high-side PFET for a fixed duration. This ON-time is predetermined (internally set by EEPROM and adjusted by VIN) and the switch does not turn off until the timer has completed its period. The PFET then turns off for a minimum predetermined time period. This minimum TOFF of 150 ns is internally set and cannot be adjusted. This is to prevent false triggering from occurring on the comparator due to noise from the SW node transition. After the minimum TOFF period has expired, the PFET remains off until the comparator trip-point has been reached. Upon passing this trip-point (set at 0.8 V at the feedback pin), the PFET turns back on and the process repeats, thus regulating the output. The NFET control is complementary to the PFET control with the exception of a short dead-time to prevent shoot-through from occurring.
7.2 Functional Block Diagram
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7.3 Feature Description
7.3.1 Timing Opinion
the switching frequency on VIN and TON is shown in Equation 1 through Equation 6.
- α = VIN x TON (6) To maintain a set frequency in an application, α is always held constant by varying TON inversely with VIN. The three versions of the LM1771 are identified by the ON-times at a VIN of 3.3 V for consistency. For clarification, see Table 1.
Table 1. Timing for All Variants Characteristics of the data sheet. Table 2. The recommended frequency range of operation is 100 kHz to 1000 kHz.
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Table 2. Frequency vs VOUT for Variants
7.3.2 Short-Circuit Protection
approaches the PMOS RDS(ON).
7.3.3 Precision Enable
on VIN. There is no internal pullup connected to the EN pin, so an external signal is required to initiate switching.
7.3.4 Soft-Start
To limit in-rush current and allow for a controlled start-up the LM1771 incorporates an internal soft-start scheme. on the timing option. The approximate soft-start time can be seen in Table 3 for each timing option. Table 3. Soft-Start Timing for All Variants
SNVS446D –JUNE 2006–REVISED JANUARY 2016 www.ti.com Therefore, if the input supply is extremely slow rising such that at the end of soft-start the input voltage is still near the UVLO threshold, a timing option must be chosen to ensure that maximum duty-cycle permits the output to meet the minimum condition. TI recommends using the 2000-ns option (LM1771U) in conditions where the output voltage is 2.5 V or greater to avoid false latch-offs when there is concern regarding the input supply slew rate. NOTE As soon as soft-start terminates the short-circuit protection is enabled. This means that if the output voltage does not reach at least 68% of its final value the part latches off. In some situations, the internal soft-start routine can create a slight overshoot on the output voltage. If this must be avoided, the use of a feedforward capacitor as detailed in the Feedforward Capacitor section.
7.3.5 Jitter
The LM1771 uses an adaptive ON-time control scheme that relies on the output voltage ripple to provide a consistent switching frequency. Under certain conditions, excessive noise can couple onto the feedback pin causing the switch node to appear to have a slight amount of jitter. This is not indicative of an unstable design. The output voltage still regulates to the exact same value. Careful component selection and layout must minimize any external influence. In addition to any external noise that can add to the jitter seen on the switch node, the LM1771 always has a slight amount of switch jitter. This is because the LM1771 makes a small alteration in the reference voltage every 128 cycles to improve its accuracy and long-term performance. This has the effect of causing a change in the switching frequency at that instant. When viewed on an oscilloscope this can be seen as a jitter in the switch node. The change in feedback voltage or output voltage, however, is almost indistinguishable.
7.4 Device Functional Modes
The LM1771 has essentially one normal operational mode: in normal operation, the part operates in full synchronous mode to regulate the FB input to 0.8 V (typical) after soft-start period is over. The EN pin allows the user to shut down the part. When the part is enabled, the IC enters soft-start for 1 ms to 1.8 ms depending on the variant of the IC. See Soft-Start for more detail on the soft-start pattern.
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8 Application and Implementation
validate and test their design implementation to confirm system functionality.
8.1 Application Information
achieve optimal response, such as the inductor L1.
8.2 Typical Applications
8.2.1 LM1771 Typical Application
Figure 19. Example Circuit Schematic
8.2.1.1 Design Requirements
Output Capacitor for details on the output capacitor requirements.
8.2.1.2 Detailed Design Procedure
8.2.1.2.1 Design Guide
performance. These are taken into account and highlighted throughout this discussion. equation works well for component calculation.
due to the maximum duty-cycle limitations of the device coupled with the internal start-up. Table 4. Recommended Switching Frequency vs VOUT unexpected tripping of the feedback comparator.
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Feedforward Capacitor section for more details. they are to be used, an external ESR resistor (RSNS) must be added. This can be seen in Figure 20. Figure 20. LM1771 With an External ESR Resistor (RSNS) account when selecting this component. capacitor. This can be seen in Figure 21.
Figure 21. LM1771 With ESR Resistor (RSNS) in Series With Output Capacitor of the ripple voltage. In general a small ceramic capacitor in the range of 1 nF to 10 nF is sufficient. approaching VREF , therefore it is not needed in this situation. ceramic capacitor for the input as they provide a low impedance and small footprint.
8.2.1.2.2 MOSFET Selection
one package or as two separate packages.
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R FB1 = RFB2 VFB VOUT - 1§¨© LM1771 www.ti.com SNVS446D –JUNE 2006–REVISED JANUARY 2016 The first selection criteria is to select FETs that have sufficient VDS voltage ratings to handle the maximum voltage seen at the input plus any transient spikes that can occur from parasitic ringing. In general most FETs available for this application have ratings from 8 V to 20 V. If a larger voltage rating is used then the performance is most likely be degraded because of higher gate capacitance. The RDS(ON) specification is important as it determines several attributes of the FET and the overall power supply. The first is that it sets the maximum current of the FET for a given package. A lower RDS(ON) permits a higher allowable current and reduce conduction losses, however, it increases the gate capacitance and the switching losses. The next step is to ensure that the FETs are capable of switching at the low Vin supplies used by the LM1771. The FET must have the Rdson specified at either 1.8 V or 2.5 V to ensure that it can switch effectively as soon as the LM1771 starts up. Because the LM1771 uses a fixed dead-time scheme to prevent cross conduction, the FET transitions must occur in this time. The rise and fall time of the FETs gate can be influenced by several factors including the gate capacitance. Therefore the total gate charge of both FETs must be limited to less than 20 nC at 4.5 V VGS. The lower the number the faster the FETs must switch and the better the efficiency. A better indication of the actual switching times of the FETs can be found in their Electrical Characteristics table. The rise and fall time must be specified and selected to be at a minimum. This helps improve efficiency and ensuring that shoot-through does not occur. Another consideration in selecting the FETs is to pay attention to the Qgd / Qgs ratio. The reason for this is that proper selection can prevent spurious turnon. If we look at the NFET for example, when the FET is turning off, the gate signal pulls to ground. Conversely the PFET is turning on, causing the SW node to rise towards VIN. The gate-to-drain capacitance of the NFET couples the SW node to the gate and causes it to rise. If this voltage is excessive, then it could weakly turn on the low-side FET causing an efficiency loss. However, this coupling is mitigated by having a large gate to source capacitance of the FET, which helps to hold the gate voltage down. Ideally, a very low Qgd / Qgs would be ideal, but in practice it is common to find the number around 1. As a general rule, the lower the ratio, the better. If the above selection criteria have been met it is useful to generate a figure of merit to allow comparison between the FETs. One such method is to multiply the RDS(ON) of the FET by the total gate charge. This allows an easy comparison of the different FETs available. Once again, the lower the product, the better. The feedback resistors are used to scale the output voltage to the internal reference value such that the loop can be regulated. The feedback resistors must not be made arbitrarily large as this creates a high impedance node at the feedback pin that is more susceptible to noise. A combined value of 50 kΩ for the two resistors is adequate. To calculate the resistor values use Equation 16. Typically, the low-side resistor is initially set to a predetermined value such as 10 kΩ. where
- VFB is the internal reference voltage that can be found in the Electrical Characteristics table or approximated by 0.8 V (16) Copyright © 2006–2016, Texas Instruments Incorporated Submit Documentation Feedback 17 Product Folder Links: LM1771
Figure 22. Output Voltage Waveform
8.2.1.2.3 Efficiency Calculations
of the individual components. The quiescent current consumed by the LM1771 is one of the major sources of loss within the controller.
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8.2.1.3 Application Curve
Figure 23. Typical Efficiency 5 VIN to 2.5 VOUT frequency of 1.1 MHz and a 2-A maximum output current. Figure 24. Example Circuit Schematic, 5 VIN to 1.8 VOUT
Table 5. Bill of Materials (5-V to 1.8-V Conversion, fSW = 1090 kHz, IOUT = 2 A) frequency of 500 kHz and a 5-A maximum output current. Figure 25. Example Circuit Schematic, 5 VIN to 3.3 VOUT Table 6. Bill of Materials (5-V to 3.3-V Conversion, fSW = 500 kHz, IOUT = 5 A)
9 Power Supply Recommendations
the system to ensure that clean power is delivered to the IC.
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10 Layout
10.1 Layout Guidelines
- Ensure that the ground connections of the input capacitor, output capacitor and NMOS are as close as
possible. Ideally these must all be grounded together in close proximity on the component side of the board.
- Keep the switch node small to minimize EMI without degrading thermal cooling of the FETs.
- Locate the feedback resistors close to the IC and keep the feedback trace as short as possible. Do not run
any feedback traces near the switch node.
- Keep the gate traces short and keep them away from the switch node as much as possible.
- If a small bypass capacitor is used on VIN (0.1 µF) place it as close to the pin, with the ground connection as
close to the chip ground, as possible.
10.2 Layout Examples
Figure 26. LM1771 Layout Example (Top)
Figure 27. LM1771 Layout Example (Bottom)
10.3 Thermal Considerations
assumed that any loss associated with the body diode conduction during the dead-time is negligible. inductor manufacturer for appropriate temp curves based on current.
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation, see the following: User's Guide, AN-1299 LM5041 Evaluation Board, SNVA074
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Copyright © 2006–2016, Texas Instruments Incorporated Submit Documentation Feedback 23 Product Folder Links: LM1771
www.ti.com 31-Oct-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) LM1771SSD/NOPB Active Production WSON (NGG) | 6 1000 | SMALL T&R Yes SN Level-1-260C-UNLIM -40 to 125 1771S LM1771SSD/NOPB.A Active Production WSON (NGG) | 6 1000 | SMALL T&R Yes SN Level-1-260C-UNLIM -40 to 125 1771S LM1771TMM/NOPB Active Production VSSOP (DGK) | 8 1000 | SMALL T&R Yes SN Level-1-260C-UNLIM -40 to 125 SNSB LM1771TMM/NOPB.A Active Production VSSOP (DGK) | 8 1000 | SMALL T&R Yes SN Level-1-260C-UNLIM -40 to 125 SNSB LM1771UMM/NOPB Active Production VSSOP (DGK) | 8 1000 | SMALL T&R Yes SN Level-1-260C-UNLIM -40 to 125 SNTB LM1771UMM/NOPB.A Active Production VSSOP (DGK) | 8 1000 | SMALL T&R Yes SN Level-1-260C-UNLIM -40 to 125 SNTB LM1771USD/NOPB Active Production WSON (NGG) | 6 1000 | SMALL T&R Yes SN Level-1-260C-UNLIM -40 to 125 1771U LM1771USD/NOPB.A Active Production WSON (NGG) | 6 1000 | SMALL T&R Yes SN Level-1-260C-UNLIM -40 to 125 1771U (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1
www.ti.com 31-Oct-2025 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2
PACKAGE MATERIALS INFORMATION www.ti.com 23-Jul-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION www.ti.com 23-Jul-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM1771SSD/NOPB WSON NGG 6 1000 210.0 185.0 35.0 LM1771TMM/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 LM1771UMM/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 LM1771USD/NOPB WSON NGG 6 1000 210.0 185.0 35.0 Pack Materials-Page 2
www.ti.com PACKAGE OUTLINE C 6X 0.65 1.95 8X 0.38 0.25 5.05
4.75 TYP
0.15 0.05 0.25 GAGE PLANE 0 -8
1.1 MAX
0.23 0.13 B 3.1 2.9 NOTE 4 A 3.1 2.9 NOTE 3 0.7 0.4 VSSOP - 1.1 mm max heightDGK0008A SMALL OUTLINE PACKAGE 4214862/A 04/2023
0.13 C A B
0.1 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-187. PowerPAD is a trademark of Texas Instruments. A 20 DETAIL A TYPICAL SCALE 4.000
www.ti.com EXAMPLE BOARD LAYOUT
0.05 MAX
0.05 MIN
8X (1.4) 8X (0.45) 6X (0.65) (4.4) (R0.05) TYP VSSOP - 1.1 mm max heightDGK0008A SMALL OUTLINE PACKAGE 4214862/A 04/2023 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. 8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. 9. Size of metal pad may vary due to creepage requirement. TM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 15X SYMM SYMM SEE DETAILS 15.000 METALSOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METALEXPOSED METAL SOLDER MASK DETAILS NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED
www.ti.com EXAMPLE STENCIL DESIGN 8X (1.4) 8X (0.45) 6X (0.65) (4.4) (R0.05) TYP VSSOP - 1.1 mm max heightDGK0008A SMALL OUTLINE PACKAGE 4214862/A 04/2023 NOTES: (continued) 11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 12. Board assembly site may have different recommendations for stencil design. TM SOLDER PASTE EXAMPLE SCALE: 15X SYMM SYMM
www.ti.com SDE06A (Rev A)
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