LM1770

LM1770 Low-V SOT23 Synch Buck Cntrr w/No Ext Compensation datasheet (Rev. C)

Document overview

• Manufacturer or author: Texas Instruments, Incorporated [SNVS403,C]
• PDF pages: 25

Technical content

www.ti.com SNVS403C –SEPTEMBER 2005–REVISED APRIL 2013 LM1770Low-VoltageSOT-23SynchronousBuckControllerWithNoExternal Compensation Check forSamples: LM1770 1FEATURES DESCRIPTION The LM1770 is an efficientsynchronous buck 2• InputVoltageRange of2.8Vto5.5V switchingcontrollerin a tinySOT-23 package.The• 0.8VReferenceVoltage constanton-timecontrolscheme providesa simple

• No Compensation Required design freeof compensationcomponents, allowing minimalcomponent count and board space.Italso• Constant Frequency Across InputRange incorporatesa uniqueinputfeed-forwardto maintain• Low QuiescentCurrentof400µA a constant frequency independent of the input
• InternalSoft-start voltage.The LM1770 isoptimizedfora low voltage inputrange of 2.8V to 5.5V and can providean• ShortCircuitProtection adjustableoutputas low as 0.8V.Drivingan external• 5-PinSOT-23 Package high sidePFET and low sideNFET itcan provide efficienciesas highas 95%.APPLICATIONS Three versions of the LM1770 are available• Simple To Design,High EfficiencyStep Down dependingon theswitchingfrequencydesiredfortheSwitchingRegulators application.Nominal switchingfrequenciesare inthe
• Set-TopBoxes rangeof100kHz to1000kHz.
• Cable Modems
• Printers
• DigitalVideo Recorders
• Servers TypicalApplicationCircuit Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2Alltrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2005–2013,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

SNVS403C –SEPTEMBER 2005–REVISED APRIL 2013 www.ti.com Connection Diagram Figure1. 5-PinSOT-23 (Top View) See DBV Package Pin Functions Table1.Pin Descriptions Pin # Name Function

1 VIN Inputsupply

2 GND Ground

3 LG NFET Gate Drive

4 HG PFET Gate Drive

5 FB Feedback Pin

These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates. AbsoluteMaximum Ratings (1)(2) VIN -0.3Vto6V StorageTemperatureRange −65°C to150°C JunctionTemperature 150°C Lead Temperature(soldering,10sec) 260°C ESD Rating 2.5kV (1) AbsoluteMaximum Ratingsindicatelimitsbeyond whichdamage may occurtothedevice.OperatingRatingsindicateconditionsfor whichthedeviceisintendedtobe functional,butdo notensurespecificperformancelimits.Forensuredspecifications,see Electrical Characteristics. (2) IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheTexas InstrumentsSalesOffice/Distributorsforavailabilityand specifications. OperatingRatings (1) VIN toGND 2.8Vto5.5V JunctionTemperatureRange (TJ) −40°C to+125°C (1) AbsoluteMaximum Ratingsindicatelimitsbeyond whichdamage may occurtothedevice.OperatingRatingsindicateconditionsfor whichthedeviceisintendedtobe functional,butdo notensurespecificperformancelimits.Forensuredspecifications,see Electrical Characteristics.

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www.ti.com SNVS403C –SEPTEMBER 2005–REVISED APRIL 2013 ElectricalCharacteristics(1) SpecificationswithstandardtypefaceareforTJ = 25°C, and thoseinbold facetypeapplyoverthefullJunctionTemperature Range (−40°C to+125°C).Minimum and Maximum limitsarespecifiedthroughtest,designorstatisticalcorrelation.Typical valuesrepresentthemost likelyparametricnorm atTJ = 25°C and areprovidedforreferencepurposesonly.Unless otherwisespecifiedVIN = 3.3V. Symbol Parameter Conditions Min Typ Max Unit VFB Feedback pinvoltage VIN = 3.3V 0.782 0.80 0.818 V VIN = 5.0V 0.772 0.79 0.808 ΔVFB /ΔVIN LineRegulation VIN = 2.8Vto5.5V -5 mV/V IQ OperatingQuiescentcurrent VFB = 0.9V 400 600 µA TON SwitchOn-Time LM1770S -(500ns) 0.4 0.5 0.6 µs LM1770T -(1000ns) 0.8 1.0 1.2 LM1770U -(2000ns) 1.6 2.0 2.4 TOFF_MIN Minimum Off-Time LM1770S -(500ns) 150 250 ns LM1770T -(1000ns) 135 225 LM1770U -(2000ns) 120 220 TD Gate DriveDead-Time 70 ns IFB Feedback pinbiascurrent VFB = 0.9V 50 nA VUVLO Under-voltagelockout VIN RisingEdge 2.6 2.8 V VUVLO_HYS Under-voltagelockouthysteresis 30 mV VSC_TH Feedback pinShortCircuitLatch 0.5 0.55 0.65 V Threshold R DS(ON) 1 HG FET driverpull-upOn resistance IHG = 20 mA 5 Ω R DS(ON) 2 HG FET driverpull-downOn resistance IHG = 20 mA 9 Ω R DS(ON) 3 LG FET driverpull-upOn resistance ILG = 20 mA 9 Ω R DS(ON) 4 LG FET driverpull-downOn resistance ILG = 20 mA 5 Ω (1) AbsoluteMaximum Ratingsindicatelimitsbeyond whichdamage may occurtothedevice.OperatingRatingsindicateconditionsfor whichthedeviceisintendedtobe functional,butdo notensurespecificperformancelimits.Forensuredspecifications,see Electrical Characteristics. Copyright© 2005–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:LM1770

-50 -25 0 25 50 75 100 125 TEMPERATURE (° C) 62.5 65.0 67.5 70.0 72.5 75.0 77.5 80.0 DEADTIME (ns) -50 -25 0 25 50 75 100 125 TEMPERATURE (° C) 0.51 0.52 0.53 0.54 0.55 0.56 0.57 0.58 SHORT CIRCUIT THRESHOLD (V) -50 -25 0 25 50 75 100 125 TEMPERATURE (° C) 0.06 0.08 0.10 0.12 0.14 0.16 0.18 0.20 TOFF (Ps) -50 -25 0 25 50 75 100 125 TEMPERATURE (° C) 0.795 0.796 0.797 0.798 0.799 0.800 0.801 0.802FEEDBACK VOLTAGE (V) -50 -25 0 25 50 75 100 125 TEMPERATURE (° C) 0.47 0.48 0.49 0.50 0.51 0.52 0.53 0.54 TON (Ps) -50 -25 0 25 50 75 100 125 TEMPERATURE (° C) 150 200 250 300 350 400 450 500 QUIESCENT CURRENT ( PA) LM1770 SNVS403C –SEPTEMBER 2005–REVISED APRIL 2013 www.ti.com TypicalPerformance Characteristics TON vs Temperature (LM1770S) QuiescentCurrentvs Temperature Figure2. Figure3. TOFF vs Temperature Feedback Voltagevs Temperature Figure4. Figure5. Deadtime vs Temperature ShortCircuitThresholdvs Temperature Figure6. Figure7.

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VIN (V) 500 1000 1500 2000 2500 3000 3500TON (ns) -50 -25 0 25 50 75 100 125 TEMPERATURE (° C) 1.94 1.96 1.98 2.00 2.02 2.04 2.06 2.08 TON (Ps) VIN (V) 200 400 600 800 1000 1200 1400TON (ns) -50 -25 0 25 50 75 100 125 TEMPERATURE (° C) 0.985 0.990 0.995 1.000 1.005 1.010 1.015 1.020TON (Ps) VIN (V) 100 200 300 400 500 600 700 TON (ns) -50 -25 0 25 50 75 100 125 TEMPERATURE (° C) 2.61 2.63 2.65 2.67 2.69 2.71 2.73 2.75 UVLO THRESHOLD (V) LM1770 www.ti.com SNVS403C –SEPTEMBER 2005–REVISED APRIL 2013 TypicalPerformance Characteristics(continued) UVLO Thresholdvs Temperature TON vs VIN (LM1770S) Figure8. Figure9. TON vs Temperature (LM1770T) TON vs VIN (LM1770T) Figure10. Figure11. TON vs Temperature (LM1770U) TON vs VIN (LM1770U) Figure12. Figure13. Copyright© 2005–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:LM1770

IOUT (A) 100 EFFICIENCY (%) IOUT (A) 100 EFFICIENCY (%) IOUT (A) 100 EFFICIENCY (%) IOUT (A) 100 EFFICIENCY (%) LM1770 SNVS403C –SEPTEMBER 2005–REVISED APRIL 2013 www.ti.com TypicalPerformance Characteristics(continued) Efficiencyvs IOUT Efficiencyvs IOUT (VIN = 5V,VOUT = 3.3V) (VIN = 5V,VOUT = 2.5V) Figure14. Figure15. Efficiencyvs IOUT Efficiencyvs IOUT (VIN = 5V,VOUT = 1V) (VIN = 3.3V,VOUT = 0.8V) Figure16. Figure17.

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0.8V Q Vin LM1770 REGULATION COMPARATOR Q OFF TIMER GND HG LG Level Shift and Shoot Through Protection Low Side Driver SHORT CIRCUIT PROTECTION 0.55V /Soft Start UVLO UVLO SD SD Q Q R S Q Q R S LM1770 www.ti.com SNVS403C –SEPTEMBER 2005–REVISED APRIL 2013 BLOCK DIAGRAM Copyright© 2005–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:LM1770

fSW = D VOUT F = VIN x TON 1TP = fSW VOUT D = VIN LM1770 SNVS403C –SEPTEMBER 2005–REVISED APRIL 2013 www.ti.com

APPLICATION INFORMATION

The LM1770 synchronousbuck switcherhas a controlscheme thatisreferredto as constanton-timecontrol. Thistopologyrelieson a fixedswitchon-timeto regulatethe outputvoltage.Thison-timeisinternallysetby EEPROM and isavailablewiththreedifferentset-pointsto allowfordifferentfrequencyoptions.The LM1770 automaticallyadjuststheon-timeduringoperationinverselywiththeinputvoltage(VIN) tomaintaina constant frequency.Thereforetheswitchingfrequencyduringcontinuousconductionmode isindependentoftheinductor and capacitorsizeunlikehystereticswitchers. At the beginningof the cyclethe LM1770 turnson the highsidePFET fora fixedduration.Thison-timeis predetermined(internallysetby EEPROM and adjustedby VIN)and theswitchwillnotturnoffuntilthetimerhas completeditsperiod.The PFET willthenturnofffora minimum pre-determinedtimeperiod.Thisminimum TOFF of 150ns isinternallyset and cannot be adjusted.This isto preventfalsetriggeringfrom occurringon the comparatordue tonoisefromtheSW node transition.Aftertheminimum TOFF periodhas expired,thePFET will remain offuntilthe comparatortrip-pointhas been reached.Upon passingthistrip-point(setat 0.8V at the feedbackpin),thePFET willturnback on and theprocesswillrepeat,thusregulatingtheoutput. The NFET controliscomplementarytothePFET controlwiththeexceptionofa shortdead-timetopreventshoot throughfromoccurring. DEVICE OPERATION Timing Opinion Three versionsoftheLM1770 areavailableeach witha predeterminedTON setinternallyby EEPROM. ThisTON settingwilldeterminethe switchingfrequencyforthe application.Derivationand calculationof the switching frequency’s dependence on VIN and TON can be seen inthefollowingsection. In a PWM buck switcherthe followingequationscan be manipulatedto obtainthe switchingfrequency. Equation1 shows thestandardduty-cycleequationgivenby thevolts-secondsbalanceon theinductorwiththe followingequationsdefiningstandardrelationships: (1) TON = D x TP (2) (3) Usingthisequationand solvingforduty-cycle: D = fSW x TON (4) Frequencycan now be expressedas: (5) Or simplywrittenas: (6) where, α = VIN x TON (7) To maintaina setfrequencyinan application,α isalwaysheldconstantby varyingTON inverselywithVIN.The threeversionsoftheLM1770 areidentifiedby theon timesata VIN of3.3V forconsistency.For clarificationsee Table2: Table2.LM1770 "ON " Times Identification Product ID TON @ 3.3V α (V µs) LM1770S 0.5µs 1.65 LM1770T 1.0µs 3.3

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www.ti.com SNVS403C –SEPTEMBER 2005–REVISED APRIL 2013 Table2.LM1770 "ON " Times Identification(continued) Product ID TON @ 3.3V α (V µs) LM1770U 2.0µs 6.6 The variationofTON versusVIN can alsobe expressedgraphically.These graphscan be foundintheTypical PerformanceCharacteristicssection. With α being a constantregardlessof the versionof the LM1770 used, Equation6 shows thatthe only dependentvariableremainingisVOUT .SinceVOUT willbe a constantinany application,thefrequencywillalso remainconstant.The switchingfrequencyatwhichtheapplicationrunsdepends upon theVOUT desiredand the LM1770 versionchosen.For any VOUT ,threefrequencyoptions(LM1770 versions)can be selected.Thiscan be seen inTable3.The recommended frequencyrangeofoperationis100kHz to1000kHz. Table3.LM1770 VOUT Frequency Option VOUT Timing Options 500ns 1000ns 2000ns 0.8 485 242 121 1 606 303 152 1.2 727 364 182 1.5 909 455 227 1.8 1091 545 273 2.5 1515 758 379 3.3 2000 1000 500 SHORT-CIRCUIT PROTECTION The LM1770 has an internalshortcircuitcomparatorthatconstantlymonitorsthefeedbacknode (exceptduring soft-start).Ifthefeedbackvoltagedropsbelow 0.55V (equivalenttotheoutputvoltagedroppingbelow 68% of nominal),thecomparatorwilltripcausingtheparttolatchoff.The LM1770 willnotresume switchinguntilthe inputvoltageistakenbelow the UVLO thresholdand then broughtback intoitsnormal operatingrange.The purposeofthisfunctionistopreventa severeshortcircuitfrom causingdamage totheapplication.Due tothe fasttransientresponseof the LM1770 a severeshorton the outputcausingthe feedbackto drop would only occuriftheloadappliedhad an effectiveresistancethatapproachesthePMOS R DS(ON) . SOFT-START To limitin-rushcurrentand allowfora controlledstartuptheLM1770 incorporatesan internalsoft-startscheme. Every timetheinputvoltagerisesthroughtheUVLO thresholdtheLM1770 goes throughan adaptivesoft-start thatlimitsthe on-timeand expands the minimum off-time.In additionthe partwillonlyactivatethe PMOS allowinga discontinuousmode of operationenablinga pre-biasedstartup.The time spent in soft-startwill depend on theloadappliedtotheoutput,butisusuallyclosetoa settimethatisdependenton thetimingoption. The approximatesoft-starttimecan be seen inTable4 foreach timingoption. Table4.Soft-StartTime Approximations Product ID Timing TSS LM1770S 0.5µs 1ms LM1770T 1.0µs 1.2ms LM1770U 2.0µs 1.8ms Itshouldbe notedthatas soon as soft-startterminatestheshort-circuitprotectionisenabled.Thismeans thatif the outputvoltagedoes not reach at least68% of itsfinalvaluethe partwilllatchoff.Therefore,ifthe input supplyisextremelyslowrisingsuch thatattheend ofsoft-starttheinputvoltageisstillneartheUVLO threshold, a timingoptionshouldbe chosen toensurethatmaximum duty-cyclepermitstheoutputtomeet theminimum condition.As a generalrecommendationitisadvisabletouse the2000ns option(LM1770U) inconditionswhere theoutputvoltageis2.5V or greatertoavoidfalselatchoffswhen thereisconcernregardingtheinputsupply slewrate. Copyright© 2005–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:LM1770

SNVS403C –SEPTEMBER 2005–REVISED APRIL 2013 www.ti.com JITTER The LM1770 utilizesa constanton-timecontrolscheme thatrelieson the outputvoltagerippleto providea consistentswitchingfrequency.Under certainconditions,excessivenoisecan coupleonto the feedbackpin causingtheswitchnode toappeartohave a slightamount ofjitter.Thisisnotindicativeofan unstabledesign. The outputvoltagewillstillregulateto the exactsame value.Carefulcomponent selectionand layoutshould minimizeany externalinfluence. Inadditiontoany externalnoisethatcan add tothejitterseen on theswitchnode,theLM1770 willalwayshave a slightamount ofswitchjitter.Thisisbecause theLM1770 makes a smallalterationinthereferencevoltage every128 cyclestoimproveitsaccuracyand longtermperformance.Thishas theeffectofcausinga change in theswitchingfrequencyatthatinstant.When viewedon an oscilloscopethiscan be seen as a jitterintheswitch node.The change infeedbackvoltageoroutputvoltage,however,isalmostindistinguishable.

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L = (VIN ± VOUT ) x D 0.3 x fSW x IOUT 'IL = (VIN ± VOUT ) x D L x fSW VOUT + VDS_NMOS D = VIN + VDS_NMOS + VDS_PMOS VOUT D = VIN LM1770 www.ti.com SNVS403C –SEPTEMBER 2005–REVISED APRIL 2013 DESIGN GUIDE The followingsectionwalksthedesignerthroughthestepsnecessarytoselecttheexternalcomponents tobuild a fullyfunctionalpower supply.As withany DC-DC converternumerous trade-offsare possibletooptimizethe designforefficiency,sizeor performance.These willbe taken intoaccountand highlightedthroughoutthis discussion. The firstequationtocalculateforany buck converterisduty-cycle.Ignoringconductionlossesassociatedwith theFETs and parasiticresistancesitcan be approximatedby: (8) A more accuratecalculationforduty-cyclecan be used thattakesintoaccountthe voltagedrops acrossthe FETs. Equation9 can be used todeterminetheslightloaddependency on switchfrequencyifneeded.Otherwise thesimplifiedequationworkswellforcomponent calculation. (9) FREQUENCY SELECTION The LM1770 isavailablewiththreepresettimingoptionsthatselectthe on-timeand hence determinethe switchingfrequencyoftheapplication.Increasingtheswitchingfrequencyhas theeffectofreducingtheinductor sizeneeded fortheapplicationwhilerequiringa slighttrade-offinefficiency.Table5 shows thesame frequency tableas shown previouslyinTable3,withtheexceptionthattherecommended timingoptionforeach VOUT is highlighted.Itisnotrecommended touse a highswitchingfrequencywithVOUT equaltoorgreaterthan2.5V due tothemaximum duty-cyclelimitationsofthedevicecoupledwiththeinternalstartup. Table5.LM1770 Recommended VOUT Frequency Option VOUT Timing Options 500ns 1000ns 2000ns 0.8 485 242 - 1 606 303 - 1.2 727 364 - 1.5 909 455 227 1.8 - 545 273 2.5 - - 379 3.3 - - 500 INDUCTOR SELECTION The inductorselectionisan iterativeprocesslikelyrequiringseveralpasses beforesettlingon a finalvalue.The reasonforthisisbecause itinfluencestheamount ofrippleseen attheoutput,a criticalcomponent toensure generalstabilityofan adaptiveon-timecircuit.For thefirstpass atinductorselectionthevaluecan be obtained by targetinga maximum peak-to-peakripplecurrentequalto 30% of the maximum loadcurrent.The inductor currentripple(ΔIL)can be calculatedby: (10) Therefore,L can be initiallysettothefollowingby applyingthe30% rule: (11) Copyright© 2005–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:LM1770

H = VFB VOUT 0.8V VOUT LM1770 SNVS403C –SEPTEMBER 2005–REVISED APRIL 2013 www.ti.com The otherfeaturesoftheinductorthatcan be selectedbesidesinductancevaluearesaturationcurrentand core material.Because the LM1770 does not have a currentlimit,itisrecommended to have a saturationcurrent higherthan the maximum outputcurrentto handle any rippleor momentary over-currentevents.The core materialalsoinfluencesthesaturationcharacteristicsas ferritematerialshave a hardsaturationcurveand care shouldbe takensuch thattheyneversaturateduringnormaluse.A shieldedinductoror low profileunshielded inductorisrecommended to reduce EMI. Thisalsohelpspreventany spuriousnoisefrom pickingup on the feedbacknode resultinginunexpectedtrippingofthefeedbackcomparator. OUTPUT CAPACITOR One ofthemost importantcomponents toselectwiththeLM1770 istheoutputcapacitor.Thisisbecause itssize and ESR have a directeffecton thestabilityoftheloop.A constanton-timecontrolscheme worksby sensingthe outputvoltagerippleand switchingtheFETs appropriately.The outputvoltagerippleon a buck convertercan be approximatedby statingthattheAC inductorrippleflowsentirelyintotheoutputcapacitorand iscreatedby the ESR ofthecapacitor.Thiscan be expressedinthefollowingequation: ΔVOUT = ΔIL x R ESR (12) To ensure stability,two constraintsneed to be met. The firstisthatthereissufficientESR to createenough voltagerippleatthefeedbackpin.The recommendationistohave atleast10mV ofrippleseen atthefeedback pin.This can be calculatedby multiplyingthe outputvoltagerippleby the gain seen throughthe feedback resistors.Thisgain,H, can be calculatedbelow: (13) Iftheoutputvoltageisfairlyhigh,causingsignificantattenuationthroughthefeedbackresistors,a feed-forward capacitorcan be used.Thisisactuallyrecommended formost circuitsas itimprovesperformance.See the Feed-ForwardCapacitorsectionformore details. The second criteriaistoensurethatthereissufficientrippleattheoutputthatisin-phasewiththeswitch.The problemexiststhatthereisactuallyripplecaused by thecapacitorchargingand discharging,notonlytheESR ripple.Sincetheseare effectivelyoutofphase,problemscan exist.To avoidthisissueitisrecommended that the ratioof the two ripples(β) isalways greaterthan 5. To calculatethe minimum ESR valueneeded, the followingequationcan be used. (14) Ingeneralthebestcapacitorstouse are chemistriesthathave a known and consistentESR acrosstheentire operatingtemperaturerange.Tantalum capacitorsor similarchemistriessuch as Niobium Oxide performwell alongwithcertainfamiliesof Aluminum Electrolytics.Small valuePOSCAPs and SP CAPs alsowork as they have sufficientESR. When used inconjunctionwitha low valueinductoritispossibleto have an extremely stabledesign.The only capacitorsthatrequiremodificationto the circuitare ceramic capacitors.Ceramic capacitorscause problemsmeetingbothcriteriabecause theyhave low ESR and low capacitance.Therefore,if theyaretobe used,an externalESR resistor(RSNS) shouldbe added.Thiscan be seen below inthefollowing circuit.

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ICIN_RMS = IOUT x D(1 - D) ICIN_RMS = IOUT §¨© §¨© D 1 - D + 'IL 12 x IOUT FB VIN VIN LM1770 VOUT HG LG GND C OUT Q 1 C IN Q 2 R FB1 R FB2 R SNS LM1770 www.ti.com SNVS403C –SEPTEMBER 2005–REVISED APRIL 2013 Thiscircuituses an additionalresistorinserieswiththeinductortoadd rippleattheoutput.Itisplacedinthis locationand used incombinationwiththe feed-forwardcapacitor(CFF) to providerippleto the feedbackpin, withoutaddingrippleora DC offsettotheoutput.The benefitofusinga ceramiccapacitorisstillobtainedwith thistechnique.Because the additionof the resistorresultsin power loss,thiscircuitimplementationisonly recommended forlow currents(2A and below).The power lossand ratingoftheresistorshouldbe takeninto accountwhen selectingthiscomponent. Thiscircuitimplementationutilizingthefeed-forwardcapacitorbeginstoexperiencelimitationswhen theoutput voltageissmall.Previouslythecircuitreliedon theC FF foralltherippleatthefeedbacknode by assuming that theresistordividerwas negligible.As VOUT decreasesthiscan notbe assumed. The resistordividercontributesa largeramount ofripplewhichisproblematicas itisalsooutofphase.Thereforetheresistorlocationshouldbe changed tobe inserieswiththeoutputcapacitor.Thiscan be viewedas addingan effectiveESR totheoutput capacitor. FEED-FORWARD CAPACITOR The feed-forwardcapacitorisused acrossthetopfeedbackresistortoprovidea lowerimpedance pathforthe highfrequencyripplewithoutdegradingtheDC accuracy.Typicallythevalueforthiscapacitorshouldbe small enough topreventloadtransienterrorsbecause ofthedischargingtime,butlargeenough topreventattenuation oftheripplevoltage.Ingenerala smallceramiccapacitorintherangeof1nF to10nF issufficient. IfC FF isused thenitcan be assumed thattheripplevoltageseen atthefeedbackpinisthesame as theripple voltageattheoutput.The attenuationfactorH no longerneeds tobe used.However, intheseconditions,itis recommended to have a minimum of 20mV rippleat the feedback pin.The use of a C FF capacitoris recommended as itimprovestheregulationand stabilityofthedesign.However,itsbenefitisdiminishedas VOUT startsapproachingVREF ,thereforeitisnotneeded inthissituation. INPUT CAPACITOR The dominatingfactorthatusuallysetsan inputcapacitors’sizeisthe currenthandlingability.Thisisusually determinedby thepackage sizeand ESR ofthecapacitor.Ifthesetwo criteriaaremet thenthereusuallyshould be enough capacitancetopreventimpedance interactionswiththesource.Ingeneralitisrecommended touse a ceramiccapacitorfortheinputas theyprovidea lowimpedance and smallfootprint.One importantnoteistouse a good dielectricforthe ceramic capacitorsuch as X5R or X7R. These providebetterover temperature performanceand alsominimizetheDC voltagederatingthatoccurson Y5V capacitors.To calculatetheinput capacitorRMS current,theequationbelowcan be used: (15) whichcan be approximatedby, (16) Copyright© 2005–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:LM1770

SNVS403C –SEPTEMBER 2005–REVISED APRIL 2013 www.ti.com MOSFET Selection The two FETs used intheLM1770 requiresattentiontoselectionofparameterstoensureoptimalperformanceof thepower supply.The highsideFET shouldbe a PFET and thelow sidean NFET. These can be integratedin one package oras two separatepackages.The criteriathatmatterinselectionarelistedbelow: VDS VOLTAGE RATING The firstselectioncriteriaisto selectFETs thathave sufficientVDS voltageratingsto handle the maximum voltageseen attheinputplusany transientspikesthatcan occurfrom parasiticringing.Ingeneralmost FETs availableforthisapplicationwillhave ratingsfrom 8V to 20V. Ifa largervoltageratingis used then the performancewillmost likelybe degradedbecause ofhighergatecapacitance. RDSON The R DS(ON) specificationisimportantas itdeterminesseveralattributesoftheFET and theoverallpower supply. The firstisthatitsetsthemaximum currentoftheFET fora givenpackage.A lowerR DS(ON) willpermita higher allowablecurrentand reduceconductionlosses,however,itwillincreasethegatecapacitanceand theswitching losses. GATE DRIVE The nextstepistoensurethattheFETs arecapableofswitchingatthelow Vinsuppliesused by theLM1770. The FET shouldhave theRdson specifiedateither1.8V or2.5V toensurethatitcan switcheffectivelyas soon as theLM1770 startsup. GATE CHARGE Because theLM1770 utilizesa fixeddead-timescheme topreventcrossconduction,theFET transitionsmust occurinthistime.The riseand falltimeoftheFETs gatecan be influencedby severalfactorsincludingthegate capacitance.ThereforethetotalgatechargeofbothFETs shouldbe limitedtolessthan20nC at4.5V VGS .The lowerthenumber thefastertheFETs shouldswitchand thebettertheefficiency. RISE /FALL TIMES A betterindicationoftheactualswitchingtimesoftheFETs can be foundintheirElectricalCharacteristicstable. The riseand falltimeshouldbe specifiedand selectedtobe ata minimum. Thishelpsimproveefficiencyand ensuringthatshootthroughdoes notoccur. GATE CHARGE RATIO AnotherconsiderationinselectingtheFETs istopay attentiontotheQgd /Qgs ratio.The reasonforthisisthat properselectioncan preventspuriousturnon.Ifwe lookattheNFET forexample,when theFET isturningoff, thegatesignalwillpulltoground.ConverselythePFET willbe turningon,causingtheSW node torisetowards VIN.The gatetodraincapacitanceoftheNFET couplestheSW node tothegateand willcause ittorise.Ifthis voltageisexcessive,then itcouldweakly turnon the low sideFET causingan efficiencyloss.However, this couplingismitigatedby havinga largegate to sourcecapacitanceof the FET, which helpsto holdthe gate voltagedown. Ideally,a verylow Qgd / Qgs would be ideal,but inpracticeitiscommon to findthe number around1.As a generalrule,thelowertheratio,thebetter. Ifthe above selectioncriteriahave been met itisusefulto generatea figureof meritto allowcomparison between theFETs. One such method istomultiplytheR DS(ON) oftheFET by thetotalgatecharge.Thisallows an easy comparisonofthedifferentFETs available.Once again,thelowertheproduct,thebetter. FEEDBACK RESISTORS The feedbackresistorsareused toscaletheoutputvoltagetotheinternalreferencevaluesuch thattheloopcan be regulated.The feedbackresistorsshouldnotbe made arbitrarilylargeas thiscreatesa highimpedance node at the feedback pin thatis more susceptibleto noise.A combined value of 50kΩ forthe two resistorsis adequate.To calculatetheresistorvaluesuse theequationbelow.Typicallythelow sideresistorisinitiallysetto a pre-determinedvaluesuch as 10 kΩ.

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'VOUTVOUT_ACTUAL VOUT_SET R FB1 = RFB2 VFB VOUT - 1 LM1770 www.ti.com SNVS403C –SEPTEMBER 2005–REVISED APRIL 2013 (17) VFB istheinternalreferencevoltagethatcan be foundintheElectricalCharacteristicstableorapproximatedby 0.8V. The outputvoltagevaluecan be set in a precisemanner by takingintoaccountthe factthatthe reference voltageisregulatingthebottomoftheoutputrippleas opposed totheaveragevalue.Thisrelationshipisshown inthefigurebelow. Itcan be seen thattheaverageoutputvoltage(VOUT_ACTUAL) ishigherthantheoutputvoltage(VOUT_SET) thatwas calculatedby theearlierequationby exactlyhalftheoutputvoltageripple.The outputvoltagethatis targetedforregulationmay thenbe appended accordingtothevoltageripple.Thiscan be seen below: VOUT_ACTUAL = VOUT_SET + ½ ΔVOUT = VOUT_SET + ½ ΔIL x R ESR (18) EfficiencyCalculations One of the most importantparametersto calculateduringthe designstageisthe expectedefficiencyof the system.Thiscan helpdetermineoptimalFET selectionand can be used tocalculateexpectedtemperaturerise oftheindividualcomponents.The individuallossesofeach component arebrokendown and theequationsare listedbelow: QUIESCENT CURRENT The quiescentcurrentconsumed by the LM1770 is one of the major sources of losswithinthe controller. However, from a system standpointthisisusuallylessthan 0.5% of the overallefficiency.Therefore,itcould easilybe omittedbutisshown forcompleteness: PIQ = VIN x IQ (19) CONDUCTION LOSS There arethreelossesassociatedwiththeexternalFETs. From theDC standpointthereistheI-squaredR loss, caused by theon resistanceoftheFET. Thiscan be modeled forthePMOS by: PP_COND = D x R DSON_PMOS x IOUT 2 (20) and theNMOS by: PN_COND = (1-D) x R DSON_NMOS x IOUT 2 (21) SWITCHING LOSS The nextlossistheswitchinglossthatiscaused by theneed tochargeand dischargethegatecapacitanceof theFETs everycycle.Thiscan be approximatedby: PP_SWITCH = VIN x Q g_PMOS x fSW (22) forthePMOS, and thesame approachcan be adaptedfortheNMOS: PN_SWITCH = VIN x Q g_NMOS x fSW (23) Copyright© 2005–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:LM1770

K = POUT POUT + PLOSSES LM1770 SNVS403C –SEPTEMBER 2005–REVISED APRIL 2013 www.ti.com TRANSITIONAL LOSS The lastFET power lossisthe transitionalloss.Thisiscaused by switchingthe PMOS whileitisconducting current.Thisapproachonlymodels thePMOS transition,theNMOS lossisconsiderednegligiblebecause ithas minimaldrainto source voltagewhen itswitchesdue to the conductionof the body diode.Thereforethe transitionallossofthePMOS can be modeled by: PP_TRANSITIONAL = 0.5x VIN x IOUT x fSW x (tr + tf) (24) tr and tf aretheriseand falltimesoftheFET and can be foundintheircorrespondingdatasheet.Typicallythese numbers are simulatedusinga 6Ω drive,which correspondswelltotheLM1770. Given this,no adjustmentis needed. DCR LOSS The lastsourceofpower lossinthesystem thatneeds tobe calculatedisthelossassociatedwiththeinductor resistance(DCR) whichcan be calculatedby PDCR = R DCR x IOUT 2 (25) EFFICIENCY The efficiency,η,can thenbe calculatedby summing allthepower lossesand thenusingtheequationbelow: (26) Thermals By breakingdown theindividualpower lossineach component itmakes iteasy todeterminethetemperature riseofeach component.GenerallytheexpectedtemperatureriseoftheLM1770 isextremelylow as itisnotin thepower path.Thereforetheonlytwo itemsofconcernare thePMOS and theNMOS. The power lossinthe PMOS isthesum oftheconductionlossand transitionalloss,whiletheNMOS onlyhas conductionloss.Itis assumed thatany lossassociatedwiththebody diodeconductionduringthedead-timeisnegligible. For completenessofdesignitisimportanttowatch outforthetemperatureriseoftheinductor.Assuming the inductoriskeptoutofsaturationthepredominantlosswillbe theDC copperresistance.At higherfrequencies, depending on the core material,the core losscouldapproach or exceed the DCR losses.Consultwiththe inductormanufacturerforappropriatetemp curvesbased on current. Layout The LM1770, likeallswitchingregulators,requirescarefulattentiontolayouttoensureoptimalperformance.The followingstepsshouldbe takento aidinthe layout.For more informationreferto ApplicationNote AN-1299 SNVA074 . 1. Ensure thatthe ground connectionsof the inputcapacitor,outputcapacitorand NMOS are as closeas possible.Ideallythese shouldallbe grounded togetherin closeproximityon the component sideof the board. 2. Keep theswitchnode smalltominimizeEMI withoutdegradingthermalcoolingoftheFETs. 3. LocatethefeedbackresistorsclosetotheIC and keep thefeedbacktraceas shortas possible.Do notrun any feedbacktracesneartheswitchnode. 4. Keep thegatetracesshortand keep them away fromtheswitchnode as much as possible. 5. Ifa smallbypass capacitorisused on VIN (0.1µF) placeitas closetothepin,withthegroundconnectionas closetothechipgroundas possible.

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REVISION HISTORY

Changes from RevisionB (April2013)toRevisionC Page Copyright© 2005–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:LM1770

www.ti.com 11-Nov-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) LM1770SMF/NOPB Active Production SOT-23 (DBV) | 5 1000 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 SKJB LM1770SMF/NOPB.A Active Production SOT-23 (DBV) | 5 1000 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 SKJB LM1770TMF/NOPB Active Production SOT-23 (DBV) | 5 1000 | SMALL T&R Yes SN Level-1-260C-UNLIM -40 to 125 SKKB LM1770TMF/NOPB.A Active Production SOT-23 (DBV) | 5 1000 | SMALL T&R Yes SN Level-1-260C-UNLIM -40 to 125 SKKB LM1770TMFX/NOPB Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 SKKB LM1770TMFX/NOPB.A Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 SKKB LM1770UMF/NOPB Active Production SOT-23 (DBV) | 5 1000 | SMALL T&R Yes SN Level-1-260C-UNLIM -40 to 125 SKLB LM1770UMF/NOPB.A Active Production SOT-23 (DBV) | 5 1000 | SMALL T&R Yes SN Level-1-260C-UNLIM -40 to 125 SKLB LM1770UMFX/NOPB Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 SKLB LM1770UMFX/NOPB.A Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 SKLB (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative Addendum-Page 1

www.ti.com 11-Nov-2025 and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 5-Sep-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 5-Sep-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM1770SMF/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0 LM1770TMF/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0 LM1770TMFX/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0 LM1770UMF/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0 LM1770UMFX/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0 Pack Materials-Page 2

www.ti.com PACKAGE OUTLINE C 0.22

0.08 TYP

0.25 3.0 2.6 2X 0.95 1.9 1.45 0.90 0.15

0.00 TYP

5X 0.5 0.3 0.6

0.3 TYP

0 TYP

1.9 (0.1) (0.15) 4X 0 -15 4X 4 -15 A 3.05 2.75 B1.75 1.45 (1.1) SOT-23 - 1.45 mm max heightDBV0005A SMALL OUTLINE TRANSISTOR 4214839/K 08/2024 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-178. 4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.25 mm per side. 5. Support pin may differ or may not be present.

0.2 C A B

0.1 C SCALE 4.000

www.ti.com EXAMPLE BOARD LAYOUT

0.07 MAX

0.07 MIN

5X (1.1) 5X (0.6) (2.6) (1.9) 2X (0.95) (R0.05) TYP 4214839/K 08/2024 SOT-23 - 1.45 mm max heightDBV0005A SMALL OUTLINE TRANSISTOR NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X PKG 3 4 SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL METALSOLDER MASK OPENING NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DETAILS EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN (2.6) (1.9) 2X(0.95) 5X (1.1) 5X (0.6) (R0.05) TYP SOT-23 - 1.45 mm max heightDBV0005A SMALL OUTLINE TRANSISTOR 4214839/K 08/2024 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X SYMM PKG 3 4

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