LM10

LM10 Operational Amplifier and Voltage Reference datasheet (Rev. E)

Document overview

• Manufacturer or author: Texas Instruments, Incorporated [SNOSBH4,E]
• PDF pages: 37

Technical content

Sample & Buy T echnical Documents Tools & Software Support & Community LM10 SNOSBH4E –MAY 1998–REVISED OCTOBER 2015 LM10OperationalAmplifierandVoltageReference The circuit is recommended for portable equipment1 Features and is completely specified for operation from a 1• Input Offset Voltage: 2 mV (Maximum) single power cell. In contrast, high output-drive

• Input Offset Current: 0.7 nA (Maximum) capability, both voltage and current, along with thermal overload protection, suggest it in demanding• Input Bias Current: 20 nA (Maximum) general-purpose applications.• Reference Regulation: 0.1% (Maximum) The device is capable of operating in a floating mode,• Offset Voltage Drift: 2 μV/°C independent of fixed supplies. It can function as a• Reference Drift: 0.002%/°C remote comparator, signal conditioner, SCR controller or transmitter for analog signals, delivering the2 Applications processed signal on the same line used to supply power. It is also suited for operation in a wide range• Remote Amplifiers of voltage and current regulator applications, from low• Battery-Level Indicators voltages to several hundred volts, providing greater• Thermocouple Transmitters precision than existing ICs.
• Voltage and Current regulators This series is available in the three standard temperature ranges, with the commercial part having3 Description relaxed limits. In addition, a low-voltage specification The LM10 series are monolithic linear ICs consisting (suffix L) is available in the limited temperature of a precision reference, an adjustable reference ranges at a cost savings. buffer and an independent, high-quality operational amplifier. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM)The unit can operate from a total supply voltage as low as 1.1 V or as high as 40 V, drawing only 270 μA. SOIC (14) 8.992 mm × 7.498 mm A complementary output stage swings within 15 mV LM10 SDIP (8) 8.255 mm × 8.255 mm of the supply terminals or will deliver ±20-mA output PDIP (8) 9.81 mm × 6.35 mm current with ±0.4-V saturation. Reference output can (1) For all available packages, see the orderable addendum atbe as low as 200 mV. the end of the data sheet. Operational Amplifier Schematic (Pin numbers are for 8-pin packages) An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

SNOSBH4E –MAY 1998–REVISED OCTOBER 2015 www.ti.com Table of Contents

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision D (March 2013) to Revision E Page

• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device Changes from Revision C (March 2013) to Revision D Page

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5 Pin Configuration and Functions

Pin Functions — 8-Pin SDIP or PDIP PIN I/O DESCRIPTION NAME NO. Balance 5 I Used for offset nulling Op Amp Input (+) 3 I Noninverting input of operational amplifier Op Amp Input (–) 2 I Inverting input of operational amplifier Op Amp Output 6 O Output terminal of operational amplifier Reference Feedback 8 I Feedback terminal of reference Reference Output 1 O Output terminal of reference V+ 7 I Positive supply voltage V– 4 I Negative supply voltage 14-Pin SOIC Top View Pin Functions — 14-Pin SOIC PIN I/O DESCRIPTION NAME NO. Balance 9 I Used for offset nulling NC 1, 2, 7, 8, 14, 13 — No connection Op Amp Input (–) 4 I Inverting input of operational amplifier Op Amp Input (+) 5 I Noninverting input of operational amplifier Op Amp Output 10 O Output terminal of operational amplifier Reference Feedback 12 I Feedback terminal of reference Reference Output 3 O Output terminal of reference V+ 11 I Positive supply voltage V– 6 I Negative supply voltage Copyright © 1998–2015, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: LM10

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6 Specifications

6.1 Absolute Maximum Ratings

See (1)(2)(3) MIN MAX UNIT LM10/LM10B/LM10C 45 V Total supply voltage LM10BL/LM10CL 7 V LM10/LM10B/LM10C ±40 V Differential input voltage(4) LM10BL/LM10CL ±7 V Power dissipation(5) Internally limited Output short-circuit duration(6) Continuous TO Soldering (10 seconds) 300 °C Soldering (10 seconds) 260 °C Lead temperature DIP Vapor phase (60 seconds) 215 °C Infrared (15 seconds) 220 °C LM10 150 °C Maximum junction LM10B 100 °Ctemperature LM10C 85 °C Storage temperature, Tstg −55 150 °C (1) Refer to RETS10X for LM10H military specifications. (2) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (3) If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications. (4) The Input voltage can exceed the supply voltages provided that the voltage from the input to any other terminal does not exceed the maximum differential input voltage and excess dissipation is accounted for when VIN < V−. (5) The maximum, operating-junction temperature is 150°C for the LM10, 100°C for the LM10B(L) and 85°C for the LM10C(L). At elevated temperatures, devices must be derated based on package thermal resistance. (6) Internal thermal limiting prevents excessive heating that could result in sudden failure, but the IC can be subjected to accelerated stress with a shorted output and worst-case conditions.

6.2 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VS Supply input voltage range (V–) – (V+) 1.2 40 V VCM Common-mode voltage (V–) (V+) – 0.85 V VREF Reference voltage 0.2 V IREF Reference current 0 1 mA

6.3 Thermal Information

THERMAL METRIC(1) NEV (SDIP) NPA (SOIC) P (PDIP) UNIT

8 PINS 14 PINS 8 PINS

RθJA Junction-to-ambient thermal resistance 150 90 87 °C/W RθJC(top) Junction-to-case (top) thermal resistance 45 — — °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

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6.4 Electrical Characteristics LM10/LM10B

TJ=25°C unless otherwise specified(1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TJ=25°C 0.3 2 mV Input offset voltage TMIN ≤ TJ ≤ TMAX (see (1)) 3 mV TJ=25°C 0.25 0.7 nA Input offset current(2) TMIN ≤ TJ ≤ TMAX (see (1)) 1.5 nA TJ=25°C 10 20 nA Input bias current TMIN ≤ TJ ≤ TMAX (see (1)) 30 nA TJ=25°C 250 500 kΩ Input resistance TMIN ≤ TJ ≤ TMAX (see (1)) 150 kΩ VS = ±20 V, IOUT = 0 120 400 V/mV VOUT = ±19.95 V, TMIN ≤ TJ ≤ TMAX (see (1)) 80 V/mV VS = ±20 V, VOUT = ±19.4 V 50 130 V/mV IOUT = ±20 mA, TMIN ≤ TJ ≤ TMAX (see (1)) 20 V/mV Large signal voltage IOUT = ±15 mA, TMIN ≤ TJ ≤ TMAX (see (1)) 20 V/mVgain VS = ±0.6 V, IOUT = ±2 mA 1.5 3 V/mV VS = ±0.65 V, IOUT = ±2 mA, TMIN ≤ TJ ≤ TMAX (see (1)) 1.5 3 V/mV VOUT = ±0.4 V, TMIN ≤ TJ ≤ TMAX (see (1)) 0.5 V/mV VOUT = ±0.3 V, VCM = −0.4 V, TMIN ≤ TJ ≤ TMAX (see (1)) 0.5 V/mV 1.2 V ≤ VOUT ≤ 40 V, RL = 1.1 kΩ 14 33 V/mV 1.3 V ≤ VOUT ≤ 40 V, RL = 1.1 kΩ, TMIN ≤ TJ ≤ TMAX (see (1)) 14 33 V/mV Shunt gain(3) 0.1 mA ≤ IOUT ≤ 5 mA, TMIN ≤ TJ ≤ TMAX (see (1)) 6 V/mV

1.5 V ≤ V+ ≤ 40 V, RL = 250 Ω 8 25 V/mV

0.1 mA ≤ IOUT ≤ 20 mA, TMIN ≤ TJ ≤ TMAX (see (1)) 4 V/mV −20 V ≤ VCM ≤ 19.15 V 93 102 dB Common-mode −20 V ≤ VCM ≤ 19 V, TMIN ≤ TJ ≤ TMAX (see (1)) 93 102 dBrejection VS = ±20 V, TMIN ≤ TJ ≤ TMAX (see (1)) 87 dB −0.2 V ≥ V− ≥ −39 V 90 96 dB V+ = 1 V, TMIN ≤ TJ ≤ TMAX (see (1)) 84 dB V+ = 1.1 V, TMIN ≤ TJ ≤ TMAX (see (1)) 84 dBSupply-voltage rejection 1 V ≤ V+ ≤ 39.8 V 96 106 dB 1.1 V ≤ V+ ≤ 39.8 V, TMIN ≤ TJ ≤ TMAX (see (1)) 96 106 dB V− = −0.2 V, TMIN ≤ TJ ≤ TMAX (see (1)) 90 dB Offset voltage drift 2 μV/°C Offset current drift 2 pA/°C Bias current drift TC < 100°C 60 pA/°C 1.2 V ≤ VS ≤ 40 V 0.001 0.003 %/V Line regulation 1.3 V ≤ VS ≤ 40 V, TMIN ≤ TJ ≤ TMAX (see (1)) 0.001 0.003 %/V 0 ≤ IREF ≤ 1 mA, VREF = 200 mV, TMIN ≤ TJ ≤ TMAX (see (1)) 0.006 %/V 0 ≤ IREF ≤ 1 mA 0.01% 0.1% Load regulation V+− VREF ≥ 1 V, TMIN ≤ TJ ≤ TMAX (see (1)) 0.15% V+− VREF ≥ 1.1 V, TMIN ≤ TJ ≤ TMAX (see (1)) 0.15% (1) These specifications apply for V− ≤ VCM ≤ V+− 0.85 V, 1 V (TMIN ≤ TJ ≤ TMAX), 1.2 V, 1.3 V (TMIN ≤ TJ ≤ TMAX) < VS ≤ VMAX, VREF = 0.2 V and 0 ≤ IREF ≤ 1 mA, unless otherwise specified: VMAX = 40 V for the standard part and 6.5 V for the low voltage part. The full- temperature-range operation is −55°C to 125°C for the LM10, −25°C to 85°C for the LM10B(L) and 0°C to 70°C for the LM10C(L). The specifications do not include the effects of thermal gradients (τ1 ≃ 20 ms), die heating (τ2 ≃ 0.2 s) or package heating. Gradient effects are small and tend to offset the electrical error (see curves). (2) For TJ > 90°C, IOS may exceed 1.5 nA for VCM = V−. With TJ = 125°C and V− ≤ VCM ≤ V− + 0.1 V, IOS ≤ 5 nA. (3) This defines operation in floating applications such as the bootstrapped regulator or two-wire transmitter. Output is connected to the V+ terminal of the IC and input common mode is referred to V− (see System Examples). Effect of larger output-voltage swings with higher load resistance can be accounted for by adding the positive-supply rejection error. Copyright © 1998–2015, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: LM10

SNOSBH4E –MAY 1998–REVISED OCTOBER 2015 www.ti.com TJ=25°C unless otherwise specified(1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TJ=25°C 50 75 V/mV Amplifier gain 0.2 V ≤ VREF ≤ 35 V TMIN ≤ TJ ≤ TMAX (see (1)) 23 V/mV TJ=25°C 195 200 205 mVFeedback sense voltage TMIN ≤ TJ ≤ TMAX (see (1)) 194 206 mV TJ=25°C 20 50 nA Feedback current TMIN ≤ TJ ≤ TMAX (see (1)) 65 nA Reference drift 0.002 %/°C TJ=25°C 270 400 μA Supply current TMIN ≤ TJ ≤ TMAX (see (1)) 500 μA TJ=25°C 15

1.2 V ≤ VS ≤ 40 V μA

TMIN ≤ TJ ≤ TMAX (see (1)) 75 Supply current change TJ=25°C 15

1.3 V ≤ VS ≤ 40 V μA

TMIN ≤ TJ ≤ TMAX (see (1)) 75

6.5 Electrical Characteristics, LM10C

TJ=25°C unless otherwise specified(1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TJ=25°C 0.5 4 mV Input offset voltage TMIN ≤ TJ ≤ TMAX (see (1)) 5 mV TJ=25°C 0.4 2 nA Input offset current(2) TMIN ≤ TJ ≤ TMAX (see (1)) 3 nA TJ=25°C 12 30 nA Input bias current TMIN ≤ TJ ≤ TMAX (see (1)) 40 nA TJ=25°C 150 400 kΩ Input resistance TMIN ≤ TJ ≤ TMAX (see (1)) 115 kΩ VS = ±20 V, IOUT = 0 80 400 V/mV VOUT = ±19.95 V, TMIN ≤ TJ ≤ TMAX (see (1)) 50 V/mV VS = ±20 V, VOUT = ±19.4 V 25 130 V/mV IOUT = ±20 mA, TMIN ≤ TJ ≤ TMAX (see (1)) 15 V/mV Large signal voltage gain IOUT = ±15 mA, TMIN ≤ TJ ≤ TMAX (see (1)) 15 V/mV VS = ±0.6 V, IOUT = ±2 mA 1 3 V/mV VS = 0.65 V, IOUT = ±2 mA, TMIN ≤ TJ ≤ TMAX (see (1)) 1 3 V/mV VOUT = ±0.4 V, TMIN ≤ TJ ≤ TMAX (see (1)) 0.75 V/mV VOUT = ±0.3 V, VCM = −0.4 V, TMIN ≤ TJ ≤ TMAX (see (1)) 0.75 V/mV 1.2 V ≤ VOUT ≤ 40 V, RL = 1.1 kΩ 10 33 V/mV 1.3 V ≤ VOUT ≤ 40 V, RL = 1.1 kΩ, TMIN ≤ TJ ≤ TMAX (see (1)) 10 33 V/mV Shunt gain(3) 0.1 mA ≤ IOUT ≤ 5 mA, TMIN ≤ TJ ≤ TMAX (see (1)) 6 V/mV

1.5 V ≤ V+ ≤ 40 V, RL = 250 Ω 6 25 V/mV

0.1 mA ≤ IOUT ≤ 20 mA, TMIN ≤ TJ ≤ TMAX (see (1)) 4 V/mV (1) These specifications apply for V− ≤ VCM ≤ V+− 0.85 V, 1 V (TMIN ≤ TJ ≤ TMAX), 1.2 V, 1.3 V (TMIN ≤ TJ ≤ TMAX) < VS ≤ VMAX, VREF = 0.2 V and 0 ≤ IREF ≤ 1 mA, unless otherwise specified: VMAX = 40 V for the standard part and 6.5 V for the low voltage part. The full- temperature-range operation is −55°C to 125°C for the LM10, −25°C to 85°C for the LM10B(L) and 0°C to 70°C for the LM10C(L). The specifications do not include the effects of thermal gradients (τ1 ≃ 20 ms), die heating (τ2 ≃ 0.2 s) or package heating. Gradient effects are small and tend to offset the electrical error (see curves). (2) For TJ > 90°C, IOS may exceed 1.5 nA for VCM = V−. With TJ = 125°C and V− ≤ VCM ≤ V− + 0.1 V, IOS ≤ 5 nA. (3) This defines operation in floating applications such as the bootstrapped regulator or two-wire transmitter. Output is connected to the V+ terminal of the IC and input common mode is referred to V− (see System Examples). Effect of larger output-voltage swings with higher load resistance can be accounted for by adding the positive-supply rejection error.

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www.ti.com SNOSBH4E –MAY 1998–REVISED OCTOBER 2015 TJ=25°C unless otherwise specified(1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT −20 V ≤ VCM ≤ 19.15 V 90 102 dB Common-mode rejection −20 V ≤ VCM ≤ 19 V 90 102 dB VS = ±20 V, TMIN ≤ TJ ≤ TMAX (see (1)) 87 dB −0.2 V ≥ V− ≥ −39 V 87 96 dB V+ = 1 V, TMIN ≤ TJ ≤ TMAX (see (1)) 84 dB V+ = 1.1 V, TMIN ≤ TJ ≤ TMAX (see (1)) 84 dB Supply-voltage rejection 1 V ≤ V+ ≤ 39.8 V 93 106 dB 1.1 V ≤ V+ ≤ 39.8 V, TMIN ≤ TJ ≤ TMAX (see (1)) 93 106 dB V− = −0.2 V, TMIN ≤ TJ ≤ TMAX (see (1)) 90 dB Offset voltage drift 5 μV/°C Offset current drift 5 pA/°C Bias current drift TC < 100°C 90 pA/°C 1.2 V ≤ VS ≤ 40 V 0.001 0.008 %/V Line regulation 1.3 V ≤ VS ≤ 40 V, TMIN ≤ TJ ≤ TMAX (see (1)) 0.001 0.008 %/V 0 ≤ IREF ≤ 1 mA, VREF = 200 mV, TMIN ≤ TJ ≤ TMAX (see (1)) 0.01 %/V 0 ≤ IREF ≤ 1 mA 0.01% 0.15% Load regulation V+ − VREF ≥ 1 V, TMIN ≤ TJ ≤ TMAX (see (1)) 0.2% V+ − VREF≥ 1.1 V, TMIN ≤ TJ ≤ TMAX (see (1)) 0.2% TJ=25°C 25 70 V/mV Amplifier gain 0.2 V ≤ VREF ≤ 35 V TMIN ≤ TJ ≤ TMAX (see (1)) 15 V/mV TJ=25°C 190 200 210 mV Feedback sense voltage TMIN ≤ TJ ≤ TMAX (see (1)) 189 211 mV TJ=25°C 22 75 nA Feedback current TMIN ≤ TJ ≤ TMAX (see (1)) 90 nA Reference drift 0.003 %/°C TJ=25°C 300 500 μA Supply current TMIN ≤ TJ ≤ TMAX (see (1)) 570 μA TJ=25°C 15 TMIN ≤ TJ ≤ TMAX (see (1)) 75 Supply current change TJ=25°C 15 TMIN ≤ TJ ≤ TMAX (see (1)) 75 Copyright © 1998–2015, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: LM10

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6.6 Electrical Characteristics, LM10BL

TJ=25°C unless otherwise specified.(1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TJ=25°C 0.3 2 mV Input offset voltage TMIN ≤ TJ ≤ TMAX (see (1)) 3 mV TJ=25°C 0.1 0.7 nA Input offset current(2) TMIN ≤ TJ ≤ TMAX (see (1)) 1.5 nA TJ=25°C 10 20 nA Input bias current TMIN ≤ TJ ≤ TMAX (see (1)) 30 nA TJ=25°C 250 500 kΩ Input resistance TMIN ≤ TJ ≤ TMAX (see (1)) 150 kΩ VS = ±3.25 V, IOUT = 0 60 300 V/mV VOUT = ±3.2 V, TMIN ≤ TJ ≤ TMAX (see (1)) 40 V/mV VS = ±3.25 V, IOUT = 10 mA 10 25 V/mV VOUT = ±2.75 V, TMIN ≤ TJ ≤ TMAX (see (1)) 4 V/mV Large signal voltage gain VS = ±0.6 V, IOUT = ±2 mA 1.5 3 V/mV VS = 0.65 V, IOUT = ±2 mA, TMIN ≤ TJ ≤ TMAX (see (1)) 1.5 3 V/mV VOUT = ±0.4 V, VCM = −0.4 V, TMIN ≤ TJ ≤ TMAX (see (1)) 0.5 V/mV VOUT = ±0.3 V, VCM = −0.4 V, TMIN ≤ TJ ≤ TMAX (see (1)) 0.5 V/mV 1.5 V ≤ V +≤ 6.5 V, RL = 500 Ω 8 30 V/mV Shunt gain(3) 0.1 mA ≤ IOUT ≤ 10 mA, TMIN ≤ TJ ≤ TMAX (see (1)) 4 V/mV −3.25 V ≤ VCM ≤ 2.4 V 89 102 dB Common-mode rejection −3.25 V ≤ VCM ≤ 2.25 V, TMIN ≤ TJ ≤ TMAX (see (1)) VS = ±3.25 V, TMIN ≤ TJ ≤ TMAX (see (1)) 83 dB −0.2 V ≥ V− ≥ −5.4 V 86 96 dB V+ = 1 V, TMIN ≤ TJ ≤ TMAX (see (1)) 80 dB V+ = 1.2 V, TMIN ≤ TJ ≤ TMAX (see (1)) 80 dB Supply-voltage rejection 1 V ≤ V+ ≤ 6.3 V 94 106 dB 1.1 V ≤ V+ ≤ 6.3 V, TMIN ≤ TJ ≤ TMAX (see (1)) 94 106 dB V−=0.2 V, TMIN ≤ TJ ≤ TMAX (see (1)) 88 dB Offset voltage drift 2 μV/°C Offset current drift 2 pA/°C Bias current drift 60 pA/°C 1.2 V ≤ VS ≤ 6.5 V 0.001 0.01 %/V Line regulation 1.3 V ≤ VS ≤ 6.5 V, TMIN ≤ TJ ≤ TMAX (see (1)) 0.001 0.01 %/V 0 ≤ IREF ≤ 0.5 mA, VREF = 200 mV, TMIN ≤ TJ ≤ TMAX (see (1)) 0.02 %/V 0 ≤ IREF ≤ 0.5 mA 0.01% 0.1% Load regulation V+ − VREF ≥ 1 V, TMIN ≤ TJ ≤ TMAX (see (1)) 0.15% V+− VREF ≥ 1.1 V, TMIN ≤ TJ ≤ TMAX (see (1)) 0.15% TJ=25°C 30 70 V/mV Amplifier gain 0.2 V ≤ VREF ≤ 5.5 V TMIN ≤ TJ ≤ TMAX (see (1)) 20 V/mV TJ=25°C 195 200 205 mV Feedback sense voltage TMIN ≤ TJ ≤ TMAX (see (1)) 194 206 mV (1) These specifications apply for V− ≤ VCM ≤ V+− 0.85 V, 1 V (TMIN ≤ TJ ≤ TMAX), 1.2 V, 1.3 V (TMIN ≤ TJ ≤ TMAX) < VS ≤ VMAX, VREF = 0.2 V and 0 ≤ IREF ≤ 1 mA, unless otherwise specified: VMAX = 40 V for the standard part and 6.5 V for the low voltage part. The full- temperature-range operation is −55°C to 125°C for the LM10, −25°C to 85°C for the LM10B(L) and 0°C to 70°C for the LM10C(L). The specifications do not include the effects of thermal gradients (τ1 ≃ 20 ms), die heating (τ2 ≃ 0.2 s) or package heating. Gradient effects are small and tend to offset the electrical error (see curves). (2) For TJ > 90°C, IOS may exceed 1.5 nA for VCM = V−. With TJ=125°C and V− ≤ VCM ≤ V−+ 0.1 V, IOS ≤ 5 nA. (3) This defines operation in floating applications such as the bootstrapped regulator or two-wire transmitter. Output is connected to the V+ terminal of the IC and input common mode is referred to V− (see System Examples). Effect of larger output-voltage swings with higher load resistance can be accounted for by adding the positive-supply rejection error.

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www.ti.com SNOSBH4E –MAY 1998–REVISED OCTOBER 2015 TJ=25°C unless otherwise specified.(1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TJ=25°C 20 50 nA Feedback current TMIN ≤ TJ ≤ TMAX (see (1)) 65 nA Reference drift 0.002 %/°C TJ=25°C 260 400 μA Supply current TMIN ≤ TJ ≤ TMAX (see (1)) 500 μA

6.7 Electrical Characteristics, LM10CL

TJ=25°C unless otherwise specified.(1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TJ=25°C 0.5 4 mV Input offset voltage TMIN ≤ TJ ≤ TMAX (see (1)) 5 mV TJ=25°C 0.2 2 nA Input offset current(2) TMIN ≤ TJ ≤ TMAX (see (1)) 3 nA TJ=25°C 12 30 nA Input bias current TMIN ≤ TJ ≤ TMAX (see (1)) 40 nA TJ=25°C 150 400 kΩ Input resistance TMIN ≤ TJ ≤ TMAX (see (1)) 115 kΩ VS = ±3.25 V, IOUT = 0 40 300 V/mV VOUT = ±3.2 V, TMIN ≤ TJ ≤ TMAX (see (1)) 25 V/mV VS = ±3.25 V, IOUT = 10 mA 5 25 V/mV VOUT = ±2.75 V, TMIN ≤ TJ ≤ TMAX (see (1)) 3 V/mV Large signal voltage gain VS = ±0.6 V, IOUT = ±2 mA 1 3 V/mV VS = 0.65 V, IOUT = ±2 mA, TMIN ≤ TJ ≤ TMAX (see (1)) 1 3 V/mV VOUT = ±0.4 V, VCM = −0.4 V, TMIN ≤ TJ ≤ TMAX (see (1)) 0.75 V/mV VOUT = ±0.3 V, VCM = −0.4 V, TMIN ≤ TJ ≤ TMAX (see (1)) 0.75 V/mV 1.5 V ≤ V+ ≤ 6.5 V, RL= 500 Ω 6 30 V/mV Shunt gain(3) 0.1 mA ≤ IOUT ≤ 10 mA, TMIN ≤ TJ ≤ TMAX (see (1)) 4 V/mV −3.25 V ≤ VCM ≤ 2.4 V 80 102 dB Common-mode rejection −3.25 V ≤ VCM ≤ 2.25 V, TMIN ≤ TJ ≤ TMAX (see (1)) 80 102 dB VS = ±3.25 V, TMIN ≤ TJ ≤ TMAX (see (1)) 74 dB −0.2 V ≥ V– ≥ −5.4 V 80 96 dB V+ = 1 V, TMIN ≤ TJ ≤ TMAX (see (1)) 74 dB V+ = 1.2 V, TMIN ≤ TJ ≤ TMAX (see (1)) 74 dB Supply-voltage rejection 1 V ≤ V+ ≤ 6.3 V 80 106 dB 1.1 V ≤ V+ ≤ 6.3 V, TMIN ≤ TJ ≤ TMAX (see (1)) 80 106 dB V− = 0.2 V, TMIN ≤ TJ ≤ TMAX (see (1)) 74 dB Offset voltage drift 5 μV/°C Offset current drift 5 pA/°C Bias current drift 90 pA/°C (1) These specifications apply for V− ≤ VCM ≤ V+− 0.85 V, 1 V (TMIN ≤ TJ ≤ TMAX), 1.2 V, 1.3 V (TMIN ≤ TJ ≤ TMAX) < VS ≤ VMAX, VREF = 0.2 V and 0 ≤ IREF ≤ 1 mA, unless otherwise specified: VMAX = 40 V for the standard part and 6.5 V for the low voltage part. The full- temperature-range operation is −55°C to 125°C for the LM10, −25°C to 85°C for the LM10B(L) and 0°C to 70°C for the LM10C(L). The specifications do not include the effects of thermal gradients (τ1 ≃ 20 ms), die heating (τ2 ≃ 0.2 s) or package heating. Gradient effects are small and tend to offset the electrical error (see curves). (2) For TJ > 90°C, IOS may exceed 1.5 nA for VCM = V−. With TJ = 125°C and V− ≤ VCM ≤ V− + 0.1 V, IOS ≤ 5 nA. (3) This defines operation in floating applications such as the bootstrapped regulator or two-wire transmitter. Output is connected to the V+ terminal of the IC and input common mode is referred to V− (see System Examples). Effect of larger output-voltage swings with higher load resistance can be accounted for by adding the positive-supply rejection error. Copyright © 1998–2015, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: LM10

SNOSBH4E –MAY 1998–REVISED OCTOBER 2015 www.ti.com TJ=25°C unless otherwise specified.(1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 1.2 V ≤ VS ≤ 6.5 V 0.001 0.02 %/V Line regulation 1.3 V ≤ VS ≤ 6.5 V, TMIN ≤ TJ ≤ TMAX (see (1)) 0.001 0.02 %/V 0 ≤ IREF ≤ 0.5 mA, VREF = 200 mV, TMIN ≤ TJ ≤ TMAX (see (1)) 0.03 %/V 0 ≤ IREF ≤ 0.5 mA 0.01% 0.15% Load regulation V+− VREF ≥ 1 V, TMIN ≤ TJ ≤ TMAX (see (1)) 0.2% V+− VREF ≥ 1.1 V, TMIN ≤ TJ ≤ TMAX (see (1)) 0.2% TJ=25°C 20 70 V/mV Amplifier gain 0.2 V ≤ VREF ≤ 5.5 V TMIN ≤ TJ ≤ TMAX (see (1)) 15 V/mV TJ=25°C 190 200 210 mV Feedback sense voltage TMIN ≤ TJ ≤ TMAX (see (1)) 189 211 mV TJ=25°C 22 75 nA Feedback current TMIN ≤ TJ ≤ TMAX (see (1)) 90 nA Reference drift 0.003 %/°C TJ=25°C 280 500 μA Supply current TMIN ≤ TJ ≤ TMAX (see (1)) 570 μA

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6.8 Typical Characteristics

6.8.1 Typical Characteristics (Op Amp)

Figure 2. Common-Mode LimitsFigure 1. Input Current Figure 3. Output Voltage Drift Figure 4. Input Noise Voltage Figure 6. TransconductanceFigure 5. DC Voltage Gain

Figure 8. Output Saturation CharacteristicsFigure 7. Output Saturation Characteristics Figure 10. Minimum Supply VoltageFigure 9. Output Saturation Characteristics Figure 11. Minimum Supply Voltage Figure 12. Minimum Supply Voltage

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Figure 20. Rejection Slew LimitingFigure 19. Noise Rejection Figure 22. Thermal Gradient FeedbackFigure 21. Supply Current Figure 24. Shunt GainFigure 23. Thermal Gradient Cross-Coupling

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6.8.2 Typical Characteristics (Reference)

Figure 30. Line Regulation Figure 31. Load Regulation Figure 33. Minimum Supply VoltageFigure 32. Reference Noise Voltage Figure 35. Typical Stability RangeFigure 34. Output Saturation

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7 Detailed Description

7.1 Overview

The LM10 is a dual-operational amplifier combined with a voltage reference capable of a single-supply operation down to 1.1 V. It provides high overall performance, making it ideal for many general-purpose applications. The circuit can also operate in a floating mode, powered by residual voltage, independent of fixed supplies and it is well-protected from temperature drift.

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 Operating Characteristics

The LM10 is specified for operation from 1.2 V to 40 V. Many of the specifications apply from –55⁰C to 125⁰C. Parameters that can exhibit significant variance with regard to operating voltage or temperature are presented in electrical characteristics tables under Specifications and in the Typical Characteristics section.

7.3.2 Common-Mode Voltage Range

The input common-mode voltage range of the LM10 extends from the negative rail to 0.85 V less than the positive rail.

7.3.3 Operational Amplifier

The minimum operating voltage is reduced to nearly one volt and the current gain is less affected by temperature, resulting in a fairly flat bias current over temperature.

7.3.4 Voltage Reference

Second-order nonlinearities are compensated for which eliminates the bowed characteristics of conventional designs, resulting in better temperature stability.

7.4 Device Functional Modes

7.4.1 Floating Mode

To use the device in a floating mode, the operational amplifier output is shorted to V+ which disables the PNP portion of the output stage. Thus, with a positive input signal, neither halves of the output conducts and the current between the supply terminals is equal to the quiescent supply current. With negative input signals, the NPN portion of the output begins to turn on, reaching the short circuit current for a few hundred microvolts overdrive.

7.4.2 Linear Operation

This device can also operate linearly while in the floating mode. An example of this is shown in the Typical Application section. Copyright © 1998–2015, Texas Instruments Incorporated Submit Documentation Feedback 17 Product Folder Links: LM10

8 Application and Implementation

validate and test their design implementation to confirm system functionality.

8.1 Application Information

With heavy amplifier loading to V−, resistance drops in the V− lead can adversely affect reference regulation. close as possible to the package.

8.2 Typical Application

Figure 36. Shunt Voltage Regulator

8.2.1 Design Requirements

Table 1 lists the design parameters for this example. Table 1. Design Parameters

8.2.2 Detailed Design Procedure

0.15 V at 5 mA). The regulator is protected from shorts or overloads by current limiting and thermal shutdown.

18 Submit Documentation Feedback Copyright © 1998–2015, Texas Instruments Incorporated

requires an additional pair of precision resistors. is not as good as it might otherwise be.

8.2.3 Application Curve

Figure 37. Frequency Response

8.3 System Examples

Circuit descriptions available in application note AN-211 (SNOA638).

8.3.1 Operational Amplifier Offset Adjustment

Figure 38. Standard Figure 39. Limited Range

Figure 40. Limited Range With Boosted Reference

8.3.2 Positive Regulators

Figure 41. Low Voltage Figure 42. Best Regulation Use only electrolytic output capacitors. Figure 43. Zero Output Figure 44. Current Regulator

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*800°C Threshold Is Established By Connecting Balance To VREF. Figure 51. Flame Detector Figure 52. Light Level Sensor Figure 53. Remote Amplifier Figure 54. Remote Thermocouple Amplifier Figure 55. Transmitter for Bridge Sensor Figure 56. Precision Thermocouple Transmitter

22 Submit Documentation Feedback Copyright © 1998–2015, Texas Instruments Incorporated

Figure 61. Battery-level Indicator Figure 62. Battery-threshold Indicator Figure 63. Single-cell Voltage Monitor Figure 64. Double-ended Voltage Monitor Figure 65. Meter Amplifier Figure 66. Thermometer

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8.3.3 Reference and Internal Regulator

Figure 71. Reference and Internal Regulator

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9 Power Supply Recommendations

are presented in the Specifications section. Absolute Maximum Ratings table.

10 Layout

10.1 Layout Guidelines

10.2 Layout Example

Figure 72. Layout Example

SNOSBH4E –MAY 1998–REVISED OCTOBER 2015 www.ti.com

11 Device and Documentation Support

11.1 Device Support

11.1.1 Device Nomenclature

11.1.1.1 Definition of Terms

Input offset voltage:That voltage which must be applied between the input terminals to bias the unloaded output in the linear region. Input offset current:The difference in the currents at the input terminals when the unloaded output is in the linear region. Input bias current:The absolute value of the average of the two input currents. Input resistance:The ratio of the change in input voltage to the change in input current on either input with the other grounded. Large signal voltage gain:The ratio of the specified output voltage swing to the change in differential input voltage required to produce it. Shunt gain: The ratio of the specified output voltage swing to the change in differential input voltage required to produce it with the output tied to the V+ terminal of the IC. The load and power source are connected between the V+ and V− terminals, and input common-mode is referred to the V− terminal. Common-mode rejection:The ratio of the input voltage range to the change in offset voltage between the extremes. Supply-voltage rejection:The ratio of the specified supply-voltage change to the change in offset voltage between the extremes. Line regulation:The average change in reference output voltage over the specified supply voltage range. Load regulation:The change in reference output voltage from no load to that load specified. Feedback sense voltage: The voltage, referred to V−, on the reference feedback terminal while operating in regulation. Reference amplifier gain:The ratio of the specified reference output change to the change in feedback sense voltage required to produce it. Feedback current: The absolute value of the current at the feedback terminal when operating in regulation. Supply current:The current required from the power source to operate the amplifier and reference with their outputs unloaded and operating in the linear range.

11.2 Documentation Support

11.2.1 Related Documentation

For related documentation, see the following: AN-211 New Op Amp Ideas, SNOA638

11.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

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Product Folder Links: LM10

www.ti.com SNOSBH4E –MAY 1998–REVISED OCTOBER 2015

11.4 Trademarks

E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.

11.5 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

11.6 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Copyright © 1998–2015, Texas Instruments Incorporated Submit Documentation Feedback 29 Product Folder Links: LM10

www.ti.com 10-Nov-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) LM10CLN/NOPB Active Production PDIP (P) | 8 40 | TUBE Yes NIPDAU Level-1-NA-UNLIM 0 to 70 LM10CLN LM10CLN/NOPB.B Active Production PDIP (P) | 8 40 | TUBE Yes NIPDAU Level-1-NA-UNLIM 0 to 70 LM10CLN LM10CN/NOPB Active Production PDIP (P) | 8 40 | TUBE Yes NIPDAU Level-1-NA-UNLIM 0 to 70 LM 10CN LM10CN/NOPB.B Active Production PDIP (P) | 8 40 | TUBE Yes NIPDAU Level-1-NA-UNLIM 0 to 70 LM 10CN LM10CWM/NOPB Active Production SOIC (NPA) | 14 50 | TUBE Yes SN Level-3-260C-168 HR 0 to 70 LM10CWM LM10CWM/NOPB.B Active Production SOIC (NPA) | 14 50 | TUBE Yes SN Level-3-260C-168 HR 0 to 70 LM10CWM LM10CWMX/NOPB Active Production SOIC (NPA) | 14 1000 | LARGE T&R Yes SN Level-3-260C-168 HR 0 to 70 LM10CWM LM10CWMX/NOPB.B Active Production SOIC (NPA) | 14 1000 | LARGE T&R Yes SN Level-3-260C-168 HR 0 to 70 LM10CWM (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative Addendum-Page 1

www.ti.com 10-Nov-2025 and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 10-Aug-2026 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 10-Aug-2026 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM10CWMX/NOPB SOIC NPA 14 1000 356.0 356.0 36.0 Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 10-Aug-2026 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) LM10CLN/NOPB P PDIP 8 40 502 14 11938 4.32 LM10CLN/NOPB.B P PDIP 8 40 502 14 11938 4.32 LM10CN/NOPB P PDIP 8 40 502 14 11938 4.32 LM10CN/NOPB.B P PDIP 8 40 502 14 11938 4.32 LM10CWM/NOPB NPA SOIC 14 50 495 15 5842 7.87 LM10CWM/NOPB.B NPA SOIC 14 50 495 15 5842 7.87 Pack Materials-Page 3

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