LF444 Quad Low Power JFET Input Operational Amplifier datasheet (Rev. D)
Document overview
- Manufacturer or author: Texas Instruments, Incorporated [SNOSC04,D]
- PDF pages: 21
Technical content
www.ti.com SNOSC04D –MAY 1998–REVISED MARCH 2013 LF444QuadLowPowerJFETInputOperationalAmplifier Check forSamples: LF444 1FEATURES DESCRIPTION The LF444 quad low power operationalamplifier 23• ¼ Supply Currentofa LM148: 200 μA/Amplifier providesmany ofthesame AC characteristicsas the(max) industrystandardLM148 whilegreatlyimprovingthe• Low InputBias Current:50 pA (max) DC characteristicsof the LM148. The amplifierhas
- High Gain Bandwidth: 1 MHz thesame bandwidth,slewrate,and gain(10kΩ load) as the LM148 and onlydraws one fourththe supply• High Slew Rate:1 V/μs currentof the LM148. In additionthe wellmatched• Low Noise VoltageforLow Power 35 nV/√Hz highvoltageJFET inputdevicesoftheLF444 reduce
- Low InputNoise Current0.01pA/√Hz the inputbias and offsetcurrentsby a factorof 10,000 over the LM148. The LF444 alsohas a very• High InputImpedance: 1012Ω low equivalentinputnoisevoltagefora low power• High Gain:50k (min) amplifier. The LF444 ispincompatiblewiththeLM148 allowing an immediate 4 times reductionin power drainin many applications.The LF444 should be used wherever low power dissipationand good electrical characteristicsarethemajorconsiderations. SimplifiedSchematic Connection Diagram Figure1.1/4Quad Figure2.PDIP/SOIC Package Top View See Package Number NAK0014D, D0014A or NFF0014A These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates. Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2BI-FETisa trademarkofTexas Instruments. 3Allothertrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 1998–2013,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.
SNOSC04D –MAY 1998–REVISED MARCH 2013 www.ti.com AbsoluteMaximum Ratings(1)(2)(3) LF444A LF444 SupplyVoltage ±22V ±18V DifferentialInputVoltage ±38V ±30V InputVoltageRange (4) ±19V ±15V OutputShortCircuitDuration(5) Continuous Continuous Packages Power Dissipation(6)(7) 900 mW 670 mW Tjmax 150°C 115°C θjA (Typical) 100°C/W 85°C/W LF444A/LF444 OperatingTemperatureRange See (8) ESD Tolerance(9) Ratingtobe determined StorageTemperatureRange −65°C ≤ TA ≤ 150°C SolderingInformation Dual-In-LinePackages (Soldering,10 sec.) 260°C SmallOutlinePackage Vapor Phase (60sec.) 215°C Infrared(15sec.) 220°C (1) AbsoluteMaximum Ratingsindicatelimitsbeyond whichdamage tothedevicemay occur.Operatingratingsindicateconditionsfor whichthedeviceisfunctional,butdo notensurespecificperformancelimits.ElectricalCharacteristicsstateDC and AC electrical specificationsunderparticulartestconditionswhichensurespecificperformancelimits.Thisassumes thatthedeviceiswithinthe OperatingRatings.Specificationsarenotensuredforparameterswhere no limitisgiven,however,thetypicalvalueisa good indication ofdeviceperformance. (2) IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheTISalesOffice/Distributorsforavailabilityand specifications. (3) RefertoRETS444X forLF444MD militaryspecifications. (4) Unlessotherwisespecifiedtheabsolutemaximum negativeinputvoltageisequaltothenegativepower supplyvoltage. (5) Any oftheamplifieroutputscan be shortedtogroundindefinitely,however,more thanone shouldnotbe simultaneouslyshortedas the maximum junctiontemperaturewillbe exceeded. (6) Foroperatingatelevatedtemperature,thesedevicesmust be deratedbased on a thermalresistanceofθjA. (7) Max. Power Dissipationisdefinedby thepackage characteristics.OperatingthepartneartheMax. Power Dissipationmay cause the parttooperateoutsideensuredlimits. (8) The LF444A isavailableinboththecommercialtemperaturerange0°C ≤ TA ≤ 70°C and themilitarytemperaturerange−55°C ≤ TA ≤ 125°C. The LF444 isavailableinthecommercialtemperaturerangeonly.The temperaturerangeisdesignatedby thepositionjust beforethepackage typeinthedevicenumber.A “C ”indicatesthecommercialtemperaturerangeand an “M ”indicatesthemilitary temperaturerange.The militarytemperaturerangeisavailablein“NAK ”package only. (9) Human body model,1.5kΩ inserieswith100 pF. DC ElectricalCharacteristics(1) Symbol Parameter Conditions LF444A LF444 Units Min Typ Max Min Typ Max VOS InputOffsetVoltage R S = 10k,TA = 25°C 2 5 3 10 mV 0°C ≤ TA ≤ +70°C 6.5 12 mV −55°C ≤ TA ≤ +125°C 8 mV ΔVOS /ΔT AverageTC ofInputOffset R S = 10 kΩ 10 10 μV/°CVoltage IOS InputOffsetCurrent VS = ±15V (1)(2) Tj= 25°C 5 25 5 50 pA Tj= 70°C 1.5 1.5 nA Tj= 125°C 10 nA IB InputBiasCurrent VS = ±15V (1)(2) Tj= 25°C 10 50 10 100 pA Tj= 70°C 3 3 nA Tj= 125°C 20 nA (1) Unlessotherwisespecifiedthespecificationsapplyoverthefulltemperaturerangeand forVS = ±20V fortheLF444A and forVS = ±15V fortheLF444.VOS ,IB,and IOS aremeasured atVCM = 0. (2) The inputbiascurrentsarejunctionleakagecurrentswhichapproximatelydoubleforevery10°C increaseinthejunctiontemperature, Tj.Due tolimitedproductiontesttime,theinputbiascurrentsmeasured arecorrelatedtojunctiontemperature.Innormaloperationthe junctiontemperaturerisesabove theambienttemperatureas a resultofinternalpower dissipation,PD .Tj= TA + θjAPD where θjA isthe thermalresistancefromjunctiontoambient.Use ofa heatsinkisrecommended ifinputbiascurrentistobe kepttoa minimum.
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www.ti.com SNOSC04D –MAY 1998–REVISED MARCH 2013 DC ElectricalCharacteristics(1)(continued) Symbol Parameter Conditions LF444A LF444 Units Min Typ Max Min Typ Max R IN InputResistance Tj= 25°C 1012 1012 Ω AVOL LargeSignalVoltageGain VS = ±15V,VO = ±10V 50 100 25 100 V/mV R L = 10 kΩ,TA = 25°C Over Temperature 25 15 V/mV VO OutputVoltageSwing VS = ±15V,R L = 10 kΩ ±12 ±13 ±12 ±13 V VCM InputCommon-Mode ±16 +18 ±11 +14 V VoltageRange −17 −12 V CMRR Common-Mode R S ≤ 10 kΩ 80 100 70 95 dB RejectionRatio PSRR SupplyVoltage See (3) 80 100 70 90 dB RejectionRatio IS SupplyCurrent 0.6 0.8 0.6 1.0 mA (3) Supplyvoltagerejectionratioismeasured forbothsupplymagnitudesincreasingordecreasingsimultaneouslyinaccordancewith common practicefrom±15V to±5V fortheLF444 and from±20V to±5V fortheLF444A. AC ElectricalCharacteristics(1) Symbol Parameter Conditions LF444A LF444 Units Min Typ Max Min Typ Max Amplifier-to-Amplifier −120 −120 dB Coupling SR Slew Rate VS = ±15V,TA = 25°C 1 1 V/μs GBW Gain-BandwidthProduct VS = ±15V,TA = 25°C 1 1 MHz en EquivalentInputNoiseVoltage TA = 25°C, R S = 100Ω, 35 35 nV/√Hz f= 1 kHz in EquivalentInputNoiseCurrent TA = 25°C, f= 1 kHz 0.01 0.01 pA/√Hz (1) Unlessotherwisespecifiedthespecificationsapplyoverthefulltemperaturerangeand forVS = ±20V fortheLF444A and forVS = ±15V fortheLF444.VOS ,IB,and IOS aremeasured atVCM = 0. Copyright© 1998–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:LF444
SNOSC04D –MAY 1998–REVISED MARCH 2013 www.ti.com TypicalPerformance Characteristics InputBias Current InputBias Current Figure3. Figure4. PositiveCommon-Mode Supply Current InputVoltageLimit Figure5. Figure6. NegativeCommon-Mode InputVoltageLimit PositiveCurrentLimit Figure7. Figure8.
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www.ti.com SNOSC04D –MAY 1998–REVISED MARCH 2013 TypicalPerformance Characteristics(continued) NegativeCurrentLimit Output VoltageSwing Figure9. Figure10. Output VoltageSwing Gain Bandwidth Figure11. Figure12. Bode Plot Slew Rate Figure13. Figure14. Copyright© 1998–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:LF444
SNOSC04D –MAY 1998–REVISED MARCH 2013 www.ti.com TypicalPerformance Characteristics(continued) Distortion vs UndistortedOutput Frequency VoltageSwing Figure15. Figure16. Open Loop Common-Mode Frequency Response RejectionRatio Figure17. Figure18. Power Supply EquivalentInput RejectionRatio Noise Voltage Figure19. Figure20.
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www.ti.com SNOSC04D –MAY 1998–REVISED MARCH 2013 TypicalPerformance Characteristics(continued) Open Loop VoltageGain Output Impedance Figure21. Figure22. InverterSettlingTime Figure23. Copyright© 1998–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:LF444
SNOSC04D –MAY 1998–REVISED MARCH 2013 www.ti.com Pulse Response R L = 10 kΩ,C L = 10 pF Small SignalInverting Large SignalInverting Figure24. Figure25. Small SignalNon-Inverting Large SignalNon-Inverting Figure26. Figure27.
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www.ti.com SNOSC04D –MAY 1998–REVISED MARCH 2013 APPLICATION HINTS Thisdeviceisa quad low power op amp withJFET inputdevices(BI-FET™ ).These JFETs have largereverse breakdown voltagesfromgatetosourceand draineliminatingtheneed forclamps acrosstheinputs.Therefore, largedifferentialinputvoltagescan easilybe accommodated withouta largeincreasein inputcurrent.The maximum differentialinputvoltageisindependentofthesupplyvoltages.However,neitheroftheinputvoltages shouldbe allowedtoexceed thenegativesupplyas thiswillcause largecurrentstoflowwhich can resultina destroyedunit. Exceeding the negativecommon-mode limiton eitherinputwillforcethe outputto a high state,potentially causinga reversalofphase totheoutput.Exceedingthenegativecommon-mode limiton bothinputswillforce the amplifieroutputto a highstate.In neithercase does a latchoccursinceraisingthe inputback withinthe common-mode rangeagainputstheinputstageand thustheamplifierina normaloperatingmode. Exceedingthepositivecommon-mode limiton a singleinputwillnotchange thephase oftheoutput;however,if bothinputsexceed thelimit,theoutputoftheamplifierwillbe forcedtoa highstate. The amplifierswilloperatewitha common-mode inputvoltageequaltothepositivesupply;however,thegain bandwidthand slewratemay be decreasedinthiscondition.When thenegativecommon-mode voltageswings towithin3V ofthenegativesupply,an increaseininputoffsetvoltagemay occur. Each amplifierisindividuallybiasedto allownormal circuitoperationwithpower suppliesof ±3.0V.Supply voltageslessthanthesemay degradethecommon-mode rejectionand restricttheoutputvoltageswing. The amplifierswilldrivea 10 kΩ loadresistanceto±10V overthefulltemperaturerange.Iftheamplifierisforced todriveheavierloadcurrents,however,an increaseininputoffsetvoltagemay occuron thenegativevoltage swingand finallyreachan activecurrentlimiton bothpositiveand negativeswings. Precautionsshouldbe takentoensurethatthepower supplyfortheintegratedcircuitneverbecomes reversedin polarityorthattheunitisnotinadvertentlyinstalledbackwardsina socketas an unlimitedcurrentsurgethrough theresultingforwarddiodewithintheIC couldcause fusingoftheinternalconductorsand resultina destroyed unit. As withmost amplifiers,careshouldbe takenwithleaddress,component placementand supplydecouplingin ordertoensurestability.For example,resistorsfromtheoutputtoan inputshouldbe placedwiththebody close to the inputto minimize“pick-up” and maximize the frequencyof the feedback pole by minimizingthe capacitancefromtheinputtoground. A feedbackpoleiscreatedwhen the feedbackaround any amplifierisresistive.The parallelresistanceand capacitancefromtheinputofthedevice(usuallytheinvertinginput)toAC groundsetthefrequencyofthepole. Inmany instancesthefrequencyofthispoleismuch greaterthantheexpected3 dB frequencyoftheclosed loopgainand consequentlythereisnegligibleeffecton stabilitymargin.However, ifthefeedbackpoleisless thanapproximately6 timestheexpected3 dB frequencya leadcapacitorshouldbe placedfromtheoutputtothe inputoftheop amp. The valueoftheadded capacitorshouldbe such thattheRC timeconstantofthiscapacitor and theresistanceitparallelsisgreaterthanorequaltotheoriginalfeedbackpoletimeconstant. Copyright© 1998–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:LF444
SNOSC04D –MAY 1998–REVISED MARCH 2013 www.ti.com TypicalApplication Figure28. pH Probe Amplifier/TemperatureCompensator *ForR2 = 50k,R4 = 330k ±1% ForR2 = 100k,R4 = 75k ±1% ForR2 = 200k,R4 = 56k ±1% Polystyrene *FilmresistortypeRN60C To calibrate,insertprobeinpH =7 solution.Setthe“TEMPERATURE ADJUST ”pot,R2, tocorrespondtothesolution temperature:fullclockwisefor0°C, and proportionatelyforintermediatetemperatures,usinga turns-countingdial. Then set“CALIBRATE ”potso outputreads7V. Typicalprobe= IngoldElectrodes#465-35 DetailedSchematic Figure29. 1/4Quad
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REVISION HISTORY
Changes from RevisionC (March 2013)toRevisionD Page Copyright© 1998–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:LF444
www.ti.com 11-Nov-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) LF444ACN/NOPB Active Production PDIP (N) | 14 25 | TUBE Yes NIPDAU Level-1-NA-UNLIM 0 to 70 LF444ACN LF444ACN/NOPB.B Active Production PDIP (N) | 14 25 | TUBE Yes NIPDAU Level-1-NA-UNLIM 0 to 70 LF444ACN LF444CM/NOPB Active Production SOIC (D) | 14 55 | TUBE Yes SN Level-1-260C-UNLIM 0 to 70 LF444CM LF444CM/NOPB.B Active Production SOIC (D) | 14 55 | TUBE Yes SN Level-1-260C-UNLIM 0 to 70 LF444CM LF444CMX/NOPB Active Production SOIC (D) | 14 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM 0 to 70 LF444CM LF444CMX/NOPB.B Active Production SOIC (D) | 14 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM 0 to 70 LF444CM LF444CN/NOPB Active Production PDIP (N) | 14 25 | TUBE Yes NIPDAU Level-1-NA-UNLIM 0 to 70 LF444CN LF444CN/NOPB.B Active Production PDIP (N) | 14 25 | TUBE Yes NIPDAU Level-1-NA-UNLIM 0 to 70 LF444CN (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1
www.ti.com 11-Nov-2025 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2
PACKAGE MATERIALS INFORMATION www.ti.com 10-Aug-2026 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION www.ti.com 10-Aug-2026 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LF444CMX/NOPB SOIC D 14 2500 367.0 367.0 35.0 Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION www.ti.com 10-Aug-2026 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) LF444ACN/NOPB N PDIP 14 25 502 14 11938 4.32 LF444ACN/NOPB.B N PDIP 14 25 502 14 11938 4.32 LF444CM/NOPB D SOIC 14 55 495 8 4064 3.05 LF444CM/NOPB.B D SOIC 14 55 495 8 4064 3.05 LF444CN/NOPB N PDIP 14 25 502 14 11938 4.32 LF444CN/NOPB.B N PDIP 14 25 502 14 11938 4.32 Pack Materials-Page 3
www.ti.com PACKAGE OUTLINE C TYP6.2 5.8
1.75 MAX
12X 1.27 14X 0.51 0.31 7.62 TYP0.25 0.13 0 - 8 0.25 0.10 0.25 GAGE PLANE 1.27 0.40 A NOTE 3 8.75 8.55 B NOTE 4 4.0 3.8 4220718/A 09/2016 SOIC - 1.75 mm max heightD0014A SMALL OUTLINE INTEGRATED CIRCUIT NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm, per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm, per side. 5. Reference JEDEC registration MS-012, variation AB. 1 14
0.25 C A B
0.1 C SEE DETAIL A DETAIL A TYPICAL SCALE 1.800
www.ti.com EXAMPLE BOARD LAYOUT (5.4)
0.07 MAX
0.07 MIN
14X (1.55) 14X (0.6) 12X (1.27) (R0.05) TYP 4220718/A 09/2016 SOIC - 1.75 mm max heightD0014A SMALL OUTLINE INTEGRATED CIRCUIT SYMM SYMM LAND PATTERN EXAMPLE SCALE:8X 7 8 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METALSOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED
www.ti.com EXAMPLE STENCIL DESIGN (5.4) 12X (1.27) 14X (0.6) 14X (1.55) 4220718/A 09/2016 SOIC - 1.75 mm max heightD0014A SMALL OUTLINE INTEGRATED CIRCUIT NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SYMM SYMM 7 8 SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:8X
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