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LT3587 LINER

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Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
PDF pages: 24

Technical content

FEATURES

APPLICATIONS

DESCRIPTION

The L T®3587 provides a one chip solution for applications requiring two positive and one negative high voltage sup- plies. The L T3587 input voltage range of 2.5V to 6V makes it ideal for various battery-powered systems. A single resistor programs each of the three output voltage levels and the output current of Boost3. The intelligent soft- start allows for sequential soft-start of the Boost1 output followed by the negative output with a single capacitor . Internal sequencing circuitry also disables the inverter until the Boost1 output has reached 87% of its ﬁ nal value. The L T3587 integrates all the power switches, soft-start, and output-disconnect circuits into a small 3mm × 3mm QFN package. This high level of integration combined with small external components makes the L T3587 ideal for space constrained applications. L, L T , L TC and L TM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Li-Ion Powered Supply for CCD Imager and Six White Backlight LEDs n Ideal for CCD, LCD, LED Backlight and OLED n Easy Generation of 15V (50mA), –8V (100mA) and 20V (20mA) from a Li-Ion Cell n VVIN Range: 2.5V to 6V n Wide Output Ranges: Up to 32V for the Boosts and Up to –32V for the Inverter n Output Disconnect for the Boost Channels n Boost3 Allows Voltage Programming and/or Current Programming for a ‘One Wire Current Source’ n Overload Fault Protection with Fault I/O Pin Indicator n Combined Soft-Start and Enable Pins n Small 20-Pin 3mm × 3mm QFN Package n Digital Still and Video Cameras n Scanner and Display Systems n PDA, Cellular Phones and Handheld Computers n LED Backlight and OLED Display Drivers n CCD Imager Bias n General High Voltage Supply Bias Efﬁ ciency Curve15μH10μH

3587 TA01a

10μF VVIN 2.5V TO 6V 2.2μF 15μH1 5 μH CCD POSITIVE 15V , 50mA CCD NEGATIVE –8V , 100mA 8.06k 1μF LED DRIVER 20mA, UP TO 6 LEDS 2.2μF 22μF VVIN 2.5V TO 6V 2.7pF 6.8pF NORMALIZED CURRENT EFFICIENCY (%) POWER DISSIPATION (mW) 800 700 500 300 100 600 400 200

3587 TA01b

1.50.5 CDD+ = 50mA CDD– = 100mA LED = 20mA CDD+ CDD– LED ALL CHANNELS ENABLED POWER DISSIPATION ALL CHANNELS ENABLED

Operating Junction Temperature Range .. –40°C to 125°C (Note 1) 20 19 18 17 16 7 8 TOP VIEW UD PACKAGE 20-LEAD (3mm s 3mm) PLASTIC QFN 9 10 VOUT3 CAP3 SW3 GND FL T FB1 VOUT1 CAP1 GND SW1 VFB3 IFB3 EN/SS3 V IN EN/SS1 FB2 GND GND SW2 NC θJA = 68°C/W , θJC = 4.2°C/W EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB PARAMETER CONDITIONS MIN TYP MAX UNITS Operating Input Voltage Range 2.5 6 V Quiescent Current V EN/SS1 = 0V , VEN/SS3 = VVIN OR VEN/SS1 = VVIN, VEN/SS3 = 0V OR VEN/SS1 = VEN/SS3 = VVIN Not Switching 2.4 4 mA VEN/SS1 = VEN/SS3 = 0V , In Shutdown 5.5 9 μA Switching Frequency l 0.8 1 1.2 MHz Maximum Duty Cycle l 87 93 % Minimum On Time 50 70 ns Power Fault Delay from Any Output to FL T 16 ms FL T Input Threshold Low l 0.4 1.0 1.6 V FL T Leakage Current V FL T = 5V l ±1 μA FL T Voltage Output Low I FL T = 1mA l 0.4 V ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE L T3587EUD#PBF L T3587EUD#TRPBF LDNC 20-Lead (3mm × 3mm) Plastic QFN –40°C to 125°C Consult L TC Marketing for parts speciﬁ ed with wider operating temperature ranges. Consult L TC Marketing for information on non-standard lead based ﬁ nish parts. For more information on lead free part marking, go to: http://www.linear .com/leadfree/ For more information on tape and reel speciﬁ cations, go to: http://www.linear .com/tapeandreel/ PIN CONFIGURATION ELECTRICAL CHARACTERISTICS The l denotes the speciﬁ cations which apply over the full operating temperature range, otherwise speciﬁ cations are at TA = 25°C. VVIN = 3.6V , VEN/SS1 = VEN/SS3 = VVIN unless otherwise noted (Note 2, 3).

ELECTRICAL CHARACTERISTICS The l denotes the speciﬁ cations which apply over the full operating temperature range, otherwise speciﬁ cations are at TA = 25°C. VVIN = 3.6V , VEN/SS1 = VEN/SS3 = VVIN unless otherwise noted (Note 2, 3). PARAMETER CONDITIONS MIN TYP MAX UNITS Boost1 CAP1 Bias Current V CAP1 = 15V , VOUT1 = Open 60 150 μA FB1 Reference Voltage l 1.19 1.22 1.25 V VOUT1 Output Voltage R FB1 = 1MΩ l 14.25 15 15.75 V SW1 Current Limit 800 990 mA SW1 VCESAT ISW1 = 400mA 200 mV SW1 Leakage Current V SW1 = 15V 0.1 5 μA EN/SS1 for Full Inductor Current V FB1 = 1.1V , VFB2 = 0.1V 2.5 V EN/SS1 Shutdown Voltage Threshold l 0.2 V EN/SS1 Pin Bias Current V EN/SS1 = 0V –0.5 –1 –1.5 μA VOUT1 Current Limit V CAP1 = 15V 100 155 mA CAP1 to VOUT1 On-Resistance (RDISC1)V CAP1 = 15V , IVOUT1= 50mA 5 8 Ω VOUT1 Disconnect Leakage V VIN = VCAP1 = 6V , VVOUT1 = 0V 0.1 1 μA Inverter FB2 Reference Voltage l –10 5 20 mV Output Voltage R FB2 = 1MΩ l –7.5 –8 –8.5 V SW2 Current Limit 900 1090 mA SW2 VCESAT ISW2 = 600mA 250 mV SW2 Leakage Current V SW2 = 15V 0.1 5 μA FB1 Threshold to Start Negative Channel Percent of Final Regulation Value 87 90 % Boost3 CAP3 Bias Current V CAP3 = 15V , VOUT3 = Open 70 150 μA Boost3 Programmed Current R IFB3 = 8.06kΩ l 18 20 22 mA VFB3 Reference Voltage R VFB3 = 1MΩ, IVOUT3 = 20mA l 0.77 0.8 0.83 V VOUT3 Output Voltage R VFB3 = 1MΩ, IVOUT3 = 20mA l 14 15 16 V SW3 Current Limit 400 480 mA SW3 VCESAT ISW3 = 200mA 250 mV SW3 Leakage Current V SW3 = 15V 0.1 5 μA EN/SS3 for Full Inductor Current V VFB3 = VIFB3 = 0.6V 2 V EN/SS3 Shutdown Voltage Threshold l 0.2 V EN/SS3 Pin Bias Current V EN/SS3 = 0V –0.5 –1 –1.5 μA VOUT3 Current Limit V CAP3 = 15V , VIFB3 = 0V 70 110 mA CAP3 to VOUT3 On Resistance (RDISC3)V CAP3 = 15V , IVOUT3 = 20mA 10 15 Ω VOUT3 Disconnect Leakage V VIN = VCAP3 = 6V , VVOUT3 = 0V 0.1 1 μA CAP3 Pin Overvoltage Clamp 27 29 31 V Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All currents into pins are positive; all voltages are referenced to GND unless otherwise noted. Note 3: The L T3587 is guaranteed to meet speciﬁ ed performance from 0°C to 125°C. Speciﬁ cations over the –40°C to 125°C operating range are assured by design, characterization and correlation with statistical process controls.

TYPICAL PERFORMANCE CHARACTERISTICS Shutdown Quiescent Current vs Input Supply Voltage Quiescent Current When On But Not Switching vs Input Supply Voltage V IN UVLO Voltage vs Temperature FB1, VFB3 and IFB3 Regulation Voltage vs Temperature FB2 Regulation Voltage vs Temperature FB1, VFB3, IFB3 Bias Current in Regulation vs Temperature Speciﬁ cations are at TA = 25°C unless otherwise noted. FB2 Bias Current in Regulation vs Temperature INPUT VOL TAGE (V) 2.5 QUIESCENT CURRENT (μA) 43.5 5

3587 G01

65.53 4.5 125°C 90°C 25°C –40°C VVIN = 3.6V EN/SS1 = EN/SS3 = 0V INPUT VOL TAGE (V) 2.5 QUIESCENT CURRENT (mA) 3.5 3.0 2.5 2.0 1.5 43.5 5

3587 G02

65.53 4.5 125°C 90°C 25°C –40°C VVIN = EN/SS1 = EN/SS3 = 3.6V FB1 = VFB3 = 1.5V FB2 = IFB3 = 0V TEMPERATURE (°C) –50 UVLO VOL TAGE (V) 2.20 2.15 2.10 2.05 2.00 2507 5

3587 G03

125100–25 50 TEMPERATURE (°C) –50 REGULATION VOL TAGE (V) VIFB3, VVFB3 REGULATION VOL TAGE (V) 1.240 1.230 1.220 1.210 1.200 0.825 0.813 0.800 0.788 0.775 2507 5

3587 G04

125100–25 50 VFB3 VIFB3 FB1 VVIN = 3.6V RFB1 = RVFB3 = 1MΩ RIFB3 = 8.06kΩ IVOUT1 = 50mA IVOUT3 = 20mA TEMPERATURE (°C) –50 FB2 REGULATION VOL TAGE (mV) –10 2507 5

3587 G05

125100–25 50 VVIN = 3.6V RFB2 = 1MΩ IVNEG = 100mA TEMPERATURE (°C) –50 BIAS CURRENT (μA) IFB3 BIAS CURRENT (μA) 14.50 14.25 14.00 13.50 13.75 13.25 13.00 106 104 102 100 2507 5

3587 G06

125100–25 50 VVIN = 3.6V RFB1 = RVFB3 =1MΩ RIFB3 =8.06kΩ IVOUT1 = 50mA IVOUT3 = 20mA IVFB3 IFB1 IIFB3 TEMPERATURE (°C) –50 FB2 BIAS CURRENT (μA) –7.75 –7.85 –7.95 –8.15 –8.05 –8.25 2507 5

3587 G07

125100–25 50 VVIN = 3.6V RFB2 =1MΩ IVNEG = 100mA

TYPICAL PERFORMANCE CHARACTERISTICS Switching Frequency vs Temperature Switches V CESAT vs Current Switches Current Limit vs Temperature Speciﬁ cations are at TA = 25°C unless otherwise noted. SW1 and SW2 Current Limit vs EN/SS1 Voltage TEMPERATURE (°C) –50 FREQUENCY (MHz) 1.20 1.10 1.00 0.90 0.80 2507 5

3587 G08

125100–25 50 VVIN = 3.6V SW CURRENT (A) VCESAT (V) 0.5 0.4 0.3 0.2 0.1 0.40.2 0.8

3587 G09

1.210.6 VVIN = 3.6V SW1 SW2 SW3 TEMPERATURE (°C) –50 CURRENT LIMIT (A) 1.2 1.0 0.4 0.6 0.8 0.2 2507 5

3587 G10

125100–25 50 VVIN = 3.6V DUTY CYCLE = 60% SW1 SW2 SW3 DUTY CYCLE (%) CURRENT LIMIT (A) 2.5 2.0 1.0 1.5 0.5 60504020 30 80

3587 G11

VVIN = 3.6V SW1 SW2 SW3 EN/SS1 VOL TAGE (V) 0.5 CURRENT LIMIT (A) 1.6 1.2 0.4 0.8

3587 G12

2.52.30.7 1.9 VVIN = 3.6V DUTY CYCLE = 60% SW1 SW2 Switches Current Limit vs Duty Cycle SW3 Current Limit vs EN/SS3 Voltage EN/SS3 VOL TAGE (V) 0.5 CURRENT LIMIT (A) 0.5 0.4 0.2 0.1 0.3

3587 G13

2.52.30.7 1.9 VVIN = 3.6V SW3 EN/SS1, EN/SS3 Pull-Up Current In Shutdown vs Temperature TEMPERATURE (°C) –50 PULL-UP CURRENT (μA) 1.50 1.25 0.75 1.00 0.50 2507 5

3587 G16

125100–25 50 VVIN = 3.6V EN/SS1 = EN/SS3 = 0V Output Disconnects On Resistance vs Temperature (RDISC1, RDISC3) Output Disconnects Current Limit vs Temperature TEMPERATURE (°C) –50 ON RESISTANCE (Ω) 2507 5

3587 G14

125100–25 50 VVIN = 3.6V IVOUT1 = 50mA IVOUT3 = 20mA RDISC1 RDISC3 TEMPERATURE (°C) –50 OUTPUT DISCONNECTS CURRENT LIMIT (mA) 200.0 167.5 102.5 135.0 2507 5

3587 G15

125100–25 50 VVIN = 3.6V VVOUT1 = VVOUT3 = 15V IVOUT1 IVOUT3

VOUT3 (Pin 1): Boost3 Output Pin. This pin is the drain of an output disconnect PMOS transistor . CAP3 (Pin 2): Boost3 Output Capacitor Pin. This pin is the source of an output PMOS disconnect. Connect a capacitor from this pin to ground. SW3 (Pin 3): Boost3 Switch Pin. Connect an inductor from this pin to V IN. Minimize trace area at this pin to minimize EMI. GND (Pin 4, 7, 8, 12): Ground Pins. FL T (Pin 5): Fault Pin. This pin is a bidirectional open- drain pull-down pin. This pin pulls low when any of the enabled outputs fall out of regulation for more than 16ms. Each output is ignored during start-up until its respective enable/soft-start pin allows for full inductor current. This pin can also be externally forced low to disable all the supply outputs. Once this pin goes low (either due to an out of regulation condition or externally forced low), the pin latches low until the inputs to EN/SS1 and EN/SS3 are set low or the input supply pin is recycled. Pull up this pin to V IN with a 200k resistor when not used. FB2 (Pin 6): Inverter Output Voltage Feedback Pin. Con- nect a resistor RFB2 from this pin to the Inverter Output (VNEG) such that: R FB2 = |VNEG|/8μA Note that FB2 pin voltage is about 0V when in regulation. There is an internal 153k resistor from the FB2 pin to the internal reference. SW2 (Pin 9): Inverter Switch Pin. Connect an inductor between this pin and V IN, as well as the ﬂ ying capacitor from this pin to the anode of the lnverter ground return diode. Minimize trace area at this pin to minimize EMI. NC (Pin 10): No Connect Pin. Leave open or connect to ground. SW1 (Pin 11): Boost1 Switch Pin. Connect an inductor from this pin to V IN. Minimize trace area at this pin to minimize EMI. CAP1 (Pin 13): Boost1 Output Capacitor Pin. This pin is the source of an output PMOS disconnect. Connect a capacitor from this pin to ground. EN/SS1, EN/SS3 Shutdown Threshold vs Temperature CAP3 Overvoltage Clamp vs Temperature TYPICAL PERFORMANCE CHARACTERISTICSSpeciﬁ cations are at TA = 25°C unless otherwise noted. PIN FUNCTIONS TEMPERATURE (°C) –50 SHUTDOWN THRESHOLD VOL TAGE (V) 0.45 0.40 0.25 0.35 0.30 0.20 2507 5

3587 G17

125100–25 50 VVIN = 3.6V TEMPERATURE (°C) –50 CAP3 OV CLAMP VOL TAGE (V) 2507 5

3587 G18

125100–25 50 VVIN = 3.6V

VOUT1 (Pin 14): Boost1 Output Pin. This pin is the drain of an output disconnect PMOS transistor . FB1 (Pin 15): Boost1 Output Voltage Feedback Pin. Con- nect a resistor R FB1 from this pin to V OUT1 (or CAP1) such that: R FB1 = ((VVOUT1/1.22V) – 1) • 88.5k There is an internal 88.5k resistor from the FB1 pin to ground. EN/SS1 (Pin 16): Boost1/Inverter Shutdown and Soft-Start Pin. Boost1 and Inverter are enabled when the voltage on this pin is greater than 2.5V . They are disabled when the voltage is below 0.2V . An internal 1μA current source in conjunction with an external capacitor can be used to ramp this pin and provide soft-start. V IN (Pin 17): Input Supply Pin. Must be locally bypassed with an X5R or X7R type ceramic capacitor . EN/SS3 (Pin 18): Boost3 Shutdown and Soft-Start Pin. Boost3 is enabled when the voltage on this pin is greater than 2V. It is disabled when the voltage is below 0.2V . An internal 1μA current source in conjunction with an exter- nal capacitor can be used to ramp this pin and provide soft-start. I FB3 (Pin 19): Boost3 Output Current Programming Pin. Connect a resistor R IFB3 from this pin to ground such that: R IFB3 = 200 • (0.8V/IVOUT3) If Boost3 output is conﬁ gured as a voltage regulator, RIFB3 can be optionally used to limit the maximum output current to ILIMIT: R IFB3 = 200 • (0.8V/ILIMIT) Note: Tie IFB3 to GND when no current limit is desired. VFB3 (Pin 20): Boost3 Output Voltage Feedback Pin. Con- nect a resistor R VFB3 from this pin to V OUT3 (or CAP3) such that: R VFB3 = ((VVOUT3/0.8V) – 1) • 56.3k There is an internal 56.3k resistor from the V FB3 pin to ground. In the current regulator conﬁ guration, RVFB3 can be optionally used to limit the maximum output voltage to V CLAMP, such that: R VFB3 = ((VCLAMP/0.8V) – 1) • 56.3k Note: When no voltage clamp is desired in the current regulator conﬁ guration, tie VFB3 to GND. Exposed Pad (Pin 21): Ground Pin. Connect to PCB ground plane. Ground plane connection through multiple vias under the package is recommended for optimum electrical and thermal performance.

Figure 1. Block Diagram

3587 F01

All three channels of the L T3587 use a constant frequency, current mode control scheme to provide voltage and/or current regulation at the output. Operation can be best un- derstood by referring to the Block Diagram in Figure 1. If EN/SS1 is pulled higher than 200mV , the bandgap refer- ence, the start-up bias and the oscillator are turned on. At the start of each oscillator cycle, the SR latch X1 is set, which turns on the power switch Q1. A voltage proportional to the switch current is added to a stabilizing ramp and the resulting sum is fed into the positive terminal of the PWM comparator A3. When this voltage exceeds the level at the negative input of A3, the SR latch X1 is reset, turning off the power switch Q1. The level at the negative input of A3 is set by the error ampliﬁ er A1, which is simply an ampliﬁ ed version of the difference between the reference voltage of 1.22V and the feedback voltage. In this manner , the error ampliﬁ er sets the correct peak switch current level to keep the output voltage in regulation. If the error ampliﬁ er output increases, more current is delivered to the output; if it decreases, less current is delivered. The second channel is an inverting converter . This channel is also enabled through the EN/SS1 pin. The basic opera- tion of this second channel is the same as the positive channel. The SR latch X2 is also set at the start of each oscillator cycle. The power switch Q2 is turned on at the same time as Q1. Q2 turns off based on its own feedback loop, which consists of error ampliﬁ er A2 and PWM comparator A4. The reference voltage of this negative channel is ground. Voltage clamps (not shown) on the output of the error ampliﬁ ers A1 and A2 enforce current limit on Q1 and Q2 respectively. Similar to the ﬁ rst channel, the third channel is also a positive boost regulator . If EN/SS3 is pulled higher than 200mV , the bandgap reference, the start-up bias and the oscillators are also turned on. The SR latch X3 is set at the start of each oscillator cycle which turns on the power switch Q3. Q3 turns off based on its own feedback loop, which consists of error ampliﬁ er A5 and PWM comparator A6. The level at the negative input of A6 is set by the error ampliﬁ er A5, and is an ampliﬁ ed version of the difference between the reference voltage of 0.8V and the maximum of the two feedback voltages at V FB3 and IFB3. A separate comparator (not shown) sets the maximum current limit on Q3. The I FB3 pin is pulled up internally with a current that is (1/200) times the load current out of the V OUT3 pin. Therefore, an external resistor connected from this pin to ground generates a feedback voltage proportional to the V OUT3 output load current at the I FB3 pin. When the voltage at VFB3 is higher than the voltage at IFB3, the third channel regulates to the feedback voltage at VFB3, which in normal application is a divided down voltage from VOUT3. In this state, the third channel behaves as a boost voltage regulator . On the other hand if the voltage at I FB3 is higher , the third channel regulates to the feedback voltage at IFB3, which therefore regulates the VOUT3 output load current to a particular value. In this state, the third channel behaves as a boost current regulator . PMOS M1 is used as an output disconnect pass transistor for the ﬁ rst channel. M1 disconnects the load (V OUT1) from the input as long as the voltage between CAP1 and V IN is less than 2.5V (typical) and the voltage between CAP1 and V OUT1 is less than 10V (typ). Similarly, PMOS M3 is used as an output disconnect pass transistor for the third channel. M3 disconnects the load (V OUT3) from the input when the third channel is in shutdown (EN/SS3 voltage is lower than 200mV) and the voltage between CAP3 and V OUT3 is less than 10V (typical).

Performance Characteristics curves). S3 to charge the output capacitor C4. C2 and returning through the Schottky diode DS2. as having a ﬁ xed 0.6V drop. Table 1. Inrush Peak Current age drop and diode capacitance need to be considered.

Figure 3. Boost3 Conﬁ gured as a Voltage Table 2. Recommended Schottky Diodes end of the ﬂ ying capacitor C2 as shown in Figure 2. Schottky diodes in Table 2 can be used for D3. voltage regulation or voltage limit on current regulation. Figure 2. Inverter Conﬁ gured with a Schottky

3587 F02

3587 F03

Figure 4. Boost3 Waveform in an Output Current Boost3 loop regulates the voltage at the IFB3 pin to 0.8V . the output load is disconnected. Figure 5. Boost3 Output Open-Circuit Waveform with

3587 F04a

3587 F04b

3587 F05a

3587 F05b

the Boost3 output current (1% is recommended). is pulled up internally with a 1μA current source. negative voltage is generated at the inverter output. soft-start capacitor , and with a 10nF soft-start capacitor . Figure 6. V EN/SS1, VOUT1, VNEG, IVIN with No Soft-Start

3587 F06a

3587 F06b

Figure 1. When turned on, M1 is driven hard in the linear 10V , the output current is then again limited to 155mA. Figure 7. VCAP1,VVOUT1, IVOUT1 and IL1 During a Short-Circuit Event Figure 8. V CAP3, VVOUT3, IVOUT3 and I L4 During a Short-Circuit

3587 F07

3587 F08a

3587 F08b

the Boost3 regulation loop is disabled. across the output disconnect PMOS transistors.

Figure 10. Waveforms During Fault the Fault pin is pulled low. 16ms as well as the subsequent resetting of the part.

3587 F10

Figure 9. Feedback Connection Using the VOUT and CAP Pins

3587 F09

Figure 12. Dimming Using a DAC and a Resistor the subsequent resetting of the part. appreciable error for accurate dimming control. the output disconnect current limit to 110mA (typ). allows dimming of the LEDs without changing the color .

3587 F12

Figure 11. Waveforms When the

3587 F11

IFB3 or by using a PWM signal. tion for using this method is shown in Figure 12.

Figure 14. PWM Dimming Waveforms LED current is either zero or a constant value. the string and ground as shown in Figure 13. the output capacitor . This allows the LEDs to turn on faster . Figure 13. Six White LEDs Driver With PWM Dimming

3587 F13

3587 F14

6 LEDs

Figure 16. Dimming Range Comparison requires a ﬁ xed amount of time to reach its ﬁ nal current. settling is a larger proportion of the average current. approximately 320μs for a 3.6V input voltage. to be varied from 20mA down to less than 1μA.

3587 F16

Figure 15. Average LED Current Variation with

3587 F15

Figure 17. 2 AA Cells Providing CCD Positive and Negative Supply

3587 F17

battery, resulting in higher efﬁ ciency.

Figure 19. Recommended Component Placement Figure 18. High Current Paths paid to the PCB board layout and component placement. switching path is essential. the switches. Figure 18 outlines the critical paths.

3587 F18

switching regulator to minimize interplane coupling. component placement is shown in Figure 19.

3587 F19

Li-Ion Powered Supply for CCD Imager and Five White Backlight LEDs 15μH 10μH

3587 TA02

VFB3 VOUT3 CAP3 SW3 V IN SW1 1μF 10μF CFB1 2.7pF RFB1 CCD POSITIVE 15V , 50mA VVIN 2.5V TO 6V 2.2μFL2 15μH 15μH RFB2 CCD NEGATIVE –8V , 100mA LED DRIVER 20mA UP TO 24V VVIN 2.5V TO 6V 22μF DS2 DS3 2.2μF RVFB3 1.65M (OPTIONAL) DS1RIFB3 8.06k 100nF 100nF C1: MURATA GRM21BR61C106KE15L C2: MURATA GRM188R61C225KE15D C3, C5: MURATA GRM033R60J104KE19D C4: MURATA GRM21BR71E225KA73L C6: MURATA GRM155R61A105KE15D C7: TAIYO YUDEN LMK212BJ226MG-T C FB1: MURATA GRM1555C1H2R7BZ01D CFB2: MURATA GRM1555C1H6R8BZ01D L1, L2, L3: SUMIDA CDRH2D18/HP-150N L4: TOKO 1071AS-100M D S1, DS2, DS3: IR IR05H40CSPTR CFB2 6.8pF

Driver For a CCD Imager and an OLED Display Panel with Soft-Start Extending the High Voltage Range and the Number of Independently Controlled Regulated Outputs 15μH 15μH

3587 TA04

1μF SUPPL Y 1: 18V , 50mA VVIN 3V TO 6V 2.2μF D3 RFB2 2.26M RIFB3 10.7k 2.2μF SUPPL Y 3: 25V , 1mA TO 10mA VVIN 3V TO 6V 22μF DS1 C1 10μF CFB1 2.2pF RFB1 1.21M DS3 100nF 100nF DS2D9 22μH C1: MURATA GRM31CR71E106KA12L C2, C8, C11: MURATA GCM21BR71E225KA73L C3, C5: MURATA GRM033R60J104KE19D C4: MURATA GRM21BR71E225KA73L C6: MURATA GRM155R61A105KE15D C7: MURATA GRM32ER61E226KE15L C9, C12: MURATA GRM31CR71H225KA55L C10, C13: MURATA GRM21BR71H105KA12L C FB1: MURATA GRM1555C1H2R2BZ01D CFB2: MURATA GRM1555C1H2R7BZ01D L1, L4: COILCRAFT LPS4018-153 L2, L3: COILCRAFT LPS4018-223 D S1, DS2, DS3, D3, D4, D5, D6, D7, D9, D10: IR IR05H40CSPTR D8: DIODES INC DDZ9709T RVFB3 1.74M SUPPL Y 2: –18V , 50mA CFB2 2.7pF INOUT SHDNADJ L T3014 GND 3.24M 100k C13 1μF SUPPL Y 5: 40V , 5mA C12 2.2μF 2.2μF D7 D5 SUPPL Y 1 SUPPL Y 2 C11 2.2μF 2.2μF IN OUT SHDN ADJ L T1964 GND R5 100k 1.21M C10 1μF 24V SUPPL Y 4: –40V , 5mA D10 15μH 10μH

3587 TA03

1μF CCD POSITIVE 15V , 50mA VVIN 2.5V TO 6V 2.2μF D3 RFB2 CCD NEGATIVE –8V , 100mA RIFB3 7.15k (OPTIONAL) 1μF OLED DRIVER 16V , 20mA VVIN 2.5V TO 6V 22μF DS1 4.7μF RFB1 DS3 100nF CFB2 6.8pF 100nF DS2 15μH C1: TAIYO YUDEN TMK212BJ475KG-T C2: TAIYO YUDEN EMK107BJ225KA-T C3, C5: TAIYO YUDEN JMK063BJ104KP-F C4: TAIYO YUDEN GMK107BJ105KA-T C6: TAIYO YUDEN LMK105BJ105KV-F C7: TAIYO YUDEN LMK212BJ226MG-T C FB1: TAIYO YUDEN EMK105SK2R7JW-F CFB2: TAIYO YUDEN EMK105SH6R8JW-F L1, L2: SUMIDA CDRH2D18/HP-150N L4: TOKO 1071AS-100M D S1, DS2, DS3, D3: NXP PMEG2005EB RVFB3 1.07M CFB1 2.7pF

Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However , no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. 3.00 ± 0.10 (4 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 1.65 ± 0.05 NOTE: 1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE PIN 1 TOP MARK (NOTE 6) 0.40 ± 0.10 BOTTOM VIEW—EXPOSED PAD 1.65 ± 0.10 (4-SIDES) 0.75 ± 0.05 R = 0.115 TYP R = 0.05 TYP 0.20 ± 0.05 PIN 1 NOTCH R = 0.20 TYP OR 0.25 × 45° CHAMFER 19 20

0.40 BSC

0.200 REF

2.10 ± 0.05 3.50 ± 0.05 (4 SIDES) 0.70 ±0.05 0.00 – 0.05 (UD20) QFN 0306 REV A 0.20 ±0.05 20-Lead Plastic QFN (3mm × 3mm) (Reference L TC DWG # 05-08-1720 Rev A)

Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear .com © LINEAR TECHNOLOGY CORPORATION 2008 LT 0109 REV C • PRINTED IN USA RELATED PARTS TYPICAL APPLICATION PART NUMBER DESCRIPTION COMMENTS L T1944 Dual Output, Boost/Inverter , 350mA I SW, High Efﬁ ciency Boost-Inverting DC/DC Converter VIN(MIN) = 1.2V , VIN(MAX) = 15V , VOUT(MAX) = ±34V , IQ = 20, ISD < 1μA, L T1945 Dual Output, Boost/Inverter , 350mA I SW, High Efﬁ ciency Boost-Inverting DC/DC Converter VIN(MIN) = 1.2V , VIN(MAX) = 15V , VOUT(MAX) = ±34V , IQ = 20, ISD < 1μA, L T3463/L T3463A Dual Output, Boost/Inverter , 250mA I SW, Constant Off- Time, High Efﬁ ciency Step-Up DC/DC Converter with Integrated Schottkys V IN(MIN) = 2.3V , VIN(MAX) = 15V , VOUT(MAX) = 40V , IQ = 40μA, ISD < 1μA, 3 × 3 DFN-10 Package L T3466/L T3466-1 Dual Constant Current, 2MHz, High Efﬁ ciency White LED Boost Regulator with Integrated Schottky Diode VIN(MIN) = 2.7V , VIN(MAX) = 24V , VOUT(MAX) = 40V , IQ = 5mA, ISD < 16μA, 3 × 3 DFN-10 Package L T3471 Dual Output, Boost/Inverter , 1.3A I SW, 1.2MHz, High Efﬁ ciency Boost-Inverting DC/DC Converter VIN(MIN) = 2.4V , VIN(MAX) = 16V , VOUT(MAX) = 40V , IQ = 2.5mA, ISD < 1μA, 3 × 3 DFN-10 Package L T3472/L T3472A Dual Output, Boost/Inverter , 400mA I SW, 1.2MHz, High Efﬁ ciency Boost-Inverting DC/DC Converter VIN(MIN) = 2.2V , VIN(MAX) = 16V , VOUT(MAX) = ±34V IQ = 2.8mA, ISD < 1μA, 3 × 3 DFN-10 Package L T3473/L T3473A 40V , 1A, 1.2MHz Micropower Low Noise Boost Converter with Output Disconnect VIN(MIN) = 2.2V , VIN(MAX) = 16V , VOUT(MAX) = 36V , IQ = 150μA, ISD < 1μA, 3 × 3 DFN-12 Package L T3494/L T3494A 40V , 180mA/350mA Micropower Low Noise Boost Converter with Output Disconnect VIN(MIN) = 2.3V , VIN(MAX) = 16V , VOUT(MAX) = 40V , IQ = 65μA, ISD < 1μA, 3 × 2 DFN-8 Package L T3497 Dual 2.3MHz, Full Function LED Driver with Integrated Schottkys and 250:1 T rue Color PWM Dimming VIN(MIN) = 2.5V , VIN(MAX) = 10V , VOUT(MAX) = 32V , IQ = 6mA, ISD < 12μA, 2 × 3 DFN-10 Package L T3580 40V , 2A, 2.5MHz Boost/Inverter DC/DC Converter V IN: 2.5V to 32V , VOUT(MAX) = 40V , IQ = 1mA, ISD < 1μA, MSOP-8E, 3mm × 3mm DFN-8 Packages General Purpose High Voltage Supplies Generator 15μH 10μH

3587 TA05

1μF SUPPL Y 1: 15V , 50mA VVIN 2.5V TO 6V 2.2μF RFB2 CFB2 2.2pF SUPPL Y 2: –16V , 50mA RIFB3 6.34k 2.2μF SUPPL Y 3: 25V SUPPL Y WITH SAFETY CURRENT LIMIT AT 25mA VVIN 2.5V TO 6V 22μF DS1 C1 10μF RFB1 DS3 100nF 100nF DS2DS4 22μH 22μH C1: MURATA GRM31CR71E106KA12L C2: MURATA GRM21BR71E225KA73L C3, C5: MURATA GRM033R60J104KE19D C4: MURATA GRM21BR71E225KA73L C6: MURATA GRM155R61A105KE15D C7: MURATA GRM32ER61E226KE15L C FB1: MURATA GRM1555C1H2R7BZ01D CFB2: MURATA GRM1555C1H2R2BZ01D L1: COILCRAFT LPS4018-153 L2, L3: COILCRAFT LPS4018-223 L4: TOKO 1071AS-100M D S1, DS2, DS3, DS4: IR IR05H40CSPTR RVFB3 1.74M CFB1 2.7pF

Selected Specification

Linear Technology LDNC overview.

Summary

High Voltage Monolithic Inverter and Dual Boost

Description

High Voltage Monolithic Inverter and Dual Boost

Source title LDNC Datasheet(PDF) - Linear Technology

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