LCZM

LTC2641 LINER

Document overview

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Technical content

FEATURES

APPLICATIONS

DESCRIPTION

16-/14-/12-Bit VOUT DACs in 3mm × 3mm DFN The LTC®2641/LTC2642 are families of 16-, 14- and 12-bit unbuffered voltage output DACs. These DACs operate from a single 2.7V to 5.5V supply and are guaranteed monotonic over temperature. The LTC2641-16/LTC2642-16 provide 16-bit performance (±2LSB INL and ±1LSB DNL) over temperature. Unbuffered DAC outputs result in low supply current of 120μA and a low offset error of ±1LSB. Both the LTC2641 and LTC2642 feature a reference input range of 2V to V DD. VOUT swings from 0V to V REF. For bipolar operation, the LTC2642 includes matched scaling resistors for use with an external precision op amp (such as the LT1678), generating a ±V REF output swing at RFB. The LTC2641/LTC2642 use a simple SPI/MICROWIRE compatible 3-wire serial interface which can be operated at clock rates up to 50MHz and can interface directly with optocouplers for applications requiring isolation. A power-on reset circuit clears the LTC2641’s DAC output to zero scale and the LTC2642’s DAC output to midscale when power is initially applied. A logic low on the ⎯C⎯L⎯R pin asynchronously clears the DAC to zero scale (LTC2641) or midscale (LTC2642). These DACs are all specifi ed over the commercial and industrial ranges. ■ Tiny 3mm × 3mm 8-Pin DFN Package ■ Maximum 16-Bit INL Error: ±2LSB over Temperature ■ Low 120μA Supply Current ■ Guaranteed Monotonic over Temperature ■ Low 0.5nV•sec Glitch Impulse ■ 2.7V to 5.5V Single Supply Operation ■ Fast 1μs Settling Time to 16 Bits ■ Unbuffered Voltage Output Directly Drives 60k Loads ■ 50MHz SPI TM/QSPITM/MICROWIRETM Compatible Serial Interface ■ Power-On Reset Clears DAC Output to Zero Scale (LTC2641) or Midscale (LTC2642) ■ Schmitt-Trigger Inputs for Direct Optocoupler Interface ■ Asynchronous ⎯C⎯L⎯R Pin ■ 8-Lead MSOP and 3mm × 3mm DFN Packages (LTC2641) ■ 10-Lead MSOP and 3mm × 3mm DFN Packages (LTC2642) ■ High Resolution Offset and Gain Adjustment ■ Process Control and Industrial Automation ■ Automatic Test Equipment ■ Data Aquisition Systems , LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Bipolar 16-Bit DAC 16-BIT DATA LATCH CONTROL LOGIC 16-BIT DAC 1/2 LT1678 INV RFBVDD VREF 2V TO VDD BIPOLAR VOUT –VREF TO VREF 0.1μF 5pF REF 2.7V TO 5.5V VOUT GND

26412 TA01a

1μF0.1μF LTC2642 POWER-ON RESET CS SCLK DIN CLR CODE –1.0 INL (LSB) –0.8 –0.4 –0.2 1.0 0.4 16384 32768 LT1372 • G10 –0.6 0.6 0.8 0.2 49152 65535 VDD = 5V VREF = 2.5V ±2.5V RANGE INL 25°C INL 90°C INL –45°C LTC2642-16 Integral Nonlinearity

⎯C⎯S, SCLK, DIN, (Note 1) LTC2641 TOP VIEW DD PACKAGE 8-LEAD (3mm × 3mm) PLASTIC DFN 1REF CS SCLK DIN GND VDD VOUT CLR TJMAX = 125°C (NOTE 2), θJA = 43°C/W EXPOSED PAD (PIN 9) IS GND, MUST BE SOLDERED TO PCB REF CS SCLK DIN GND V DD VOUT CLR TOP VIEW MS8 PACKAGE 8-LEAD PLASTIC MSOP TJMAX = 125°C (NOTE 2), θJA = 200°C/W LTC2642 TOP VIEW DD PACKAGE 10-LEAD (3mm × 3mm) PLASTIC DFN

1 GND

V OUT REF CS SCLK DIN CLR TJMAX = 125°C (NOTE 2), θJA = 43°C/W EXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB REF CS SCLK DIN CLR GND V DD RFB INV V OUT TOP VIEW MS PACKAGE 10-LEAD PLASTIC MSOP TJMAX = 125°C (NOTE 2), θJA = 120°C/W PIN CONFIGURATION Operating Temperature Range

LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC2641CDD-16#PBF LTC2641CDD-14#PBF LTC2641CDD-12#PBF LTC2641CDD-16#TRPBF LTC2641CDD-14#TRPBF LTC2641CDD-12#TRPBF LCZP LCZN LCZM 8-Lead (3mm × 3mm) Plastic DFN 8-Lead (3mm × 3mm) Plastic DFN 8-Lead (3mm × 3mm) Plastic DFN 0°C to 70°C 0°C to 70°C 0°C to 70°C LTC2641IDD-16#PBF LTC2641IDD-14#PBF LTC2641IDD-12#PBF LTC2641IDD-16#TRPBF LTC2641IDD-14#TRPBF LTC2641IDD-12#TRPBF LCZP LCZN LCZM 8-Lead (3mm × 3mm) Plastic DFN 8-Lead (3mm × 3mm) Plastic DFN 8-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C –40°C to 85°C –40°C to 85°C LTC2641CMS8-16#PBF LTC2641CMS8-14#PBF LTC2641CMS8-12#PBF LTC2641CMS8-16#TRPBF LTC2641CMS8-14#TRPBF LTC2641CMS8-12#TRPBF LTCZS LTCZR LTCZQ 8-Lead Plastic MSOP 8-Lead Plastic MSOP 8-Lead Plastic MSOP 0°C to 70°C 0°C to 70°C 0°C to 70°C LTC2641IMS8-16#PBF LTC2641IMS8-14#PBF LTC2641IMS8-12#PBF LTC2641IMS8-16#TRPBF LTC2641IMS8-14#TRPBF LTC2641IMS8-12#TRPBF LTCZS LTCZR LTCZQ 8-Lead Plastic MSOP 8-Lead Plastic MSOP 8-Lead Plastic MSOP –40°C to 85°C –40°C to 85°C –40°C to 85°C LTC2642 LTC2642CDD-16#PBF LTC2642CDD-14#PBF LTC2642CDD-12#PBF LTC2642CDD-16#TRPBF LTC2642CDD-14#TRPBF LTC2642CDD-12#TRPBF LCZW LCZV LCZT 10-Lead (3mm × 3mm) Plastic DFN 10-Lead (3mm × 3mm) Plastic DFN 10-Lead (3mm × 3mm) Plastic DFN 0°C to 70°C 0°C to 70°C 0°C to 70°C LTC2642IDD-16#PBF LTC2642IDD-14#PBF LTC2642IDD-12#PBF LTC2642IDD-16#TRPBF LTC2642IDD-14#TRPBF LTC2642IDD-12#TRPBF LCZW LCZV LCZT 10-Lead (3mm × 3mm) Plastic DFN 10-Lead (3mm × 3mm) Plastic DFN 10-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C –40°C to 85°C –40°C to 85°C LTC2642CMS-16#PBF LTC2642CMS-14#PBF LTC2642CMS-12#PBF LTC2642CMS-16#TRPBF LTC2642CMS-14#TRPBF LTC2642CMS-12#TRPBF LTCZZ LTCZY LTCZX 10-Lead Plastic MSOP 10-Lead Plastic MSOP 10-Lead Plastic MSOP 0°C to 70°C 0°C to 70°C 0°C to 70°C LTC2642IMS-16#PBF LTC2642IMS-14#PBF LTC2642IMS-12#PBF LTC2642IMS-16#TRPBF LTC2642IMS-14#TRPBF LTC2642IMS-12#TRPBF LTCZZ LTCZY LTCZX 10-Lead Plastic MSOP 10-Lead Plastic MSOP 10-Lead Plastic MSOP –40°C to 85°C –40°C to 85°C –40°C to 85°C Consult LTC Marketing for parts specifi ed with wider operating temperature ranges. *The temperature grade is identifi ed by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based fi nish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifi cations, go to: http://www.linear.com/tapeandreel/

ELECTRICAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Reference Input V REF Reference Input Range ● 2.0 V DD V RREF Reference Input Resistance (Note 5) Unipolar Mode (LTC2641) Bipolar Mode (LTC2642) 8.5 14.8 11.4 kΩ kΩ Dynamic Performance—VOUT SR Voltage Output Slew Rate Measured from 10% to 90% 15 V/μs Output Settling Time To ±0.5LSB of FS 1 μs DAC Glitch Impulse Major Carry Transition 0.5 nV•s Digital Feedthrough Code = 0000hex; NCS = V DD; SCLK, DIN 0V to VDD Levels 0.2 nV•s Dynamic Performance—Reference Input BW Reference –3dB Bandwidth Code = FFFFhex 1.3 MHz Reference Feedthrough Code = 0000hex, V REF = 1VP-P at 100kHz 1 mV P-P SNR Signal-to-Noise Ratio 92 dB CIN(REF) Reference Input Capacitance Code = 0000hex Code = FFFFhex 120 pF pF Digital Inputs V IH Digital Input High Voltage V CC = 3.6V to 5.5V VCC = 2.7V to 3.6V 2.4 2.0 V V VIL Digital Input Low Voltage V CC = 4.5V to 5.5V VCC = 2.7V to 4.5V 0.8 0.6 V V The ● denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. VDD = 3V or 5V, VREF = 2.5V, CL = 10pF, GND = 0, RL = ∞ unless otherwise specified. SYMBOL PARAMETER CONDI TIONS LTC2641-12 LTC2642-12 LTC2641-14 LTC2642-14 LTC2641-16 LTC2642-16 UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX Static Peformance N Resolution ● 12 14 16 Bits Monotonicity ● 12 14 16 Bits DNL Differential Nonlinearity (Note 2) ● ±0.5 ±0.5 ±1 ±0.5 ±1 LSB INL Integral Nonlinearity (Note 2) ● ±0.5 ±0.5 ±1 ±0.5 ±2 LSB ZSE Zero Code Offset Error Code = 0 ● 122 L S B ZSTC Zero Code Tempco ±0.05 ±0.05 ±0.05 ppm/°C GE Gain Error ● ±0.5 ±2 ±1 ±4 ±2 ±5 LSB GETC Gain Error Tempco ±0.1 ±0.1 ±0.1 ppm/°C ROUT DAC Output Resistance (Note 4) 6.2 6.2 6.2 k Ω Bipolar Resistor Matching (LTC2642) R FB/RINV 111 Ratio Error (Note 7) ● ±0.1 ±0.03 ±0.015 % BZE Bipolar Zero Offset Error (LTC2642) ● ±0.5 ±2 ±0.5 ±4 ±2 ±5 LSB BZSTC Bipolar Zero Tempco (LTC2642) ±0.1 ±0.1 ±0.1 ppm/°C PSR Power Supply Rejection ΔVDD = ±10% ● ±0.5 ±0.5 ±1 LSB The ● denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. VDD = 3V or 5V, VREF = 2.5V, CL = 10pF, GND = 0, RL = ∞ unless otherwise specified.

Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: Continuous operation above the specifi ed maximum operating junction temperature may impair device reliability. Note 3: LTC2641-16/LTC2642-16 ±1LSB = ±0.0015% = ±15.3ppm of full scale. LTC2641-14/LTC2642-14 ±1LSB = ±0.006% = ±61ppm of full scale. LTC2641-12/LTC2642-12 ±1LSB = ±0.024% = ±244ppm of full scale. ELECTRICAL CHARACTERISTICS The ● denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. VDD = 3V or 5V, VREF = 2.5V, CL = 10pF, GND = 0, RL = ∞ unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS IIN Digital Input Current V IN = GND to VCC ● ±1 μA CIN Digital Input Capacitance (Note 6) ● 31 0 p F VH Hysteresis Voltage 0.15 V Power Supply VDD Supply Voltage ● 2.7 5.5 V IDD Supply Current, VDD Digital Inputs = 0V or VDD ● 120 200 μA PD Power Dissipation Digital Inputs = 0V or V DD, VDD = 5V Digital Inputs = 0V or VDD, VDD = 3V 0.60 0.36 mW mW TIMING CHARACTERISTICS The ● denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. VDD = 3V or 5V, VREF = 2.5V, CL = 10pF, GND = 0, RL = ∞ unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS t1 DIN Valid to SCLK Setup Time ● 10 ns t2 DIN Valid to SCLK Hold Time ● 0n s t3 SCLK Pulse Width High ● 9n s t4 SCLK Pulse Width Low ● 9n s t5 ⎯C⎯S Pulse High Width ● 10 ns t6 LSB SCLK High to ⎯C⎯S High ● 8n s t7 ⎯C⎯S Low to SCLK High ● 8n s t8 ⎯C⎯S High to SCLK Positive Edge ● 8n s t9 ⎯C⎯L⎯R Pulse Width Low ● 15 ns fSCLK SCLK Frequency 50% Duty Cycle ● 50 MHz VDD High to ⎯C⎯S Low (Power-Up Delay) 30 μs Note 4: ROUT tolerance is typically ±20%. Note 5: Reference input resistance is code dependent. Minimum is at 871Chex (34,588) in unipolar mode and at 671Chex (26, 396) in bipolar mode. Note 6: Guaranteed by design and not production tested. Note 7: Guaranteed by gain error and offset error testing, not production tested.

TYPICAL PERFORMANCE CHARACTERISTICS Integral Nonlinearity (INL) Integral Nonlinearity (INL) vs Supply (VDD) INL vs VREF Differential Nonlinearity (DNL) Differential Nonlinearity (DNL) vs Supply (VDD) DNL vs VREF INL vs Temperature DNL vs Temperature Bipolar Zero Error vs Temperature CODE –1.0 INL (LSB) –0.8 –0.4 –0.2 1.0 0.4 16384 32768

26412 G01

–0.6 0.6 0.8 0.2 49152 65535 LTC2642-16 VREF = 2.5V VDD = 5V VDD (V) –1.0 INL (LSB) –0.8 –0.4 –0.2 1.0 0.4 3 4

26412 G02

–0.6 0.6 0.8 0.2 5 6 VREF = 2.5V +INL –INL VREF (V) –1.0 INL (LSB) –0.8 –0.4 –0.2 1.0 0.4 3 4

26412 G03

–0.6 0.6 0.8 0.2 5 6 VDD = 5.5V +INL –INL CODE –1.0 DNL (LSB) –0.8 –0.4 –0.2 1.0 0.4 16384 32768

26412 G04

–0.6 0.6 0.8 0.2 49152 65535 LTC2642-16 VREF = 2.5V VDD = 5V VDD (V) –1.0 DNL (LSB) –0.8 –0.4 –0.2 1.0 0.4 3 4

26412 G05

–0.6 0.6 0.8 0.2 5 6 VREF = 2.5V +DNL –DNL VREF (V) –1.0 DNL (LSB) –0.8 –0.4 –0.2 1.0 0.4 3 4

26412 G06

–0.6 0.6 0.8 0.2 5 6 VDD = 5.5V +DNL –DNL TEMPERATURE (°C) –40 INL (LSB) 0.2 0.6

26412 G07

–0.2 –0.6 0.4 0.8 1.0 –0.4 –0.8 –1.0 –15 10 35 85 VREF = 2.5V VDD = 5V +INL –INL TEMPERATURE (°C) –40 DNL (LSB) 0.2 0.6

26412 G08

–0.2 –0.6 0.4 0.8 1.0 –0.4 –0.8 –1.0 –15 10 35 85 VREF = 2.5V VDD = 5V +DNL –DNL TEMPERATURE (°C) –40 BZE (LSB)

26412 G09

–15 10 35 85 VREF = 2.5V VDD = 5V

TYPICAL PERFORMANCE CHARACTERISTICS Bipolar Gain Error vs Temperature Unbuffered Zero Scale Error vs Temperature (LTC2641-16) Unbuffered Full-Scale Error vs Temperature (LTC2641-16) 14-Bit Integral Nonlinearity (INL) (LTC2642-14) IREF vs Code (Unipolar LTC2641) 14-Bit Differential Nonlinearity (DNL) (LTC2642-14) 12-Bit Integral Nonlinearity (INL) (LTC2642-12) 12-Bit Differential Nonlinearity (DNL) (LTC2642-12) TEMPERATURE (°C) –40 BGE (LSB)

26412 G10

–15 10 35 85 VREF = 2.5V VDD = 5V TEMPERATURE (°C) –40 ZSE (LSB) 1.0 0.8 0.6 0.4 0.2 –0.2 –0.4 –0.6 –0.8

26412 G11

–1.0 –15 10 35 85 TEMPERATURE (°C) –40 FSE (LSB)

26412 G12

–15 10 35 85 1.0 0.8 0.6 0.4 0.2 –0.2 –0.4 –0.6 –0.8 –1.0 CODE IREF (μA) 100 150 65535

26412 G15

VREF = 2.5V CODE –1.0 INL (LSB) –0.8 –0.4 –0.2 1.0 0.4 1024 2048

26412 G16

–0.6 0.6 0.8 0.2 3072 4095 LTC2642-12 VREF = 2.5V VDD = 5V CODE –1.0 DNL (LSB) –0.8 –0.4 –0.2 1.0 0.4 1024 2048

26412 G17

–0.6 0.6 0.8 0.2 3072 4095 LTC2642-12 VREF = 2.5V VDD = 5V CODE IREF (μA) 100 150 65535

26412 G18

VREF = 2.5V IREF vs Code (Bipolar LTC2642) CODE –1.0 INL (LSB) –0.8 –0.4 –0.2 1.0 0.4 4096 8192

26412 G13

–0.6 0.6 0.8 0.2 12288 16383 LTC2642-14 VREF = 2.5V VDD = 5V CODE –1.0 DNL (LSB) –0.8 –0.4 –0.2 1.0 0.4 4096 8192

26412 G14

–0.6 0.6 0.8 0.2 12288 16383 LTC2642-14 VREF = 2.5V VDD = 5V

TYPICAL PERFORMANCE CHARACTERISTICS Supply Current (IDD) vs Temperature Supply Current (IDD) vs Supply Voltage (VDD) Supply Current (IDD) vs VREF, VDD = 5V Supply Current (IDD) vs VREF, VDD = 3V Midscale Glitch Impulse Full-Scale Transition Full-Scale Settling (Zoomed In) VOUT vs VDD = 0V to 5.5V (POR Function) LTC2641 Supply Current (IDD) vs Digital Input Voltage TEMPERATURE (°C) –40 IDD (μA) 100 125 150 –15 10 35 60

26412 G19

VREF = 2.5V VDD = 5V VDD = 3V VDD (V) 2.5 IDD (μA) 100 150 3 3.5 4 4.5

26412 G20

5 5.5 125 VREF = 2.5V DIGITAL INPUT VOLTAGE (V) IDD (μA) 100 300 400 500 3 3.5 4 4.5 900

26412 G21

0.5 1 1.5 2 2.5 5 600 700 800 VDD = 5V VDD = 3V VREF (V) IDD (μA) 100 23 4 5

26412 G22

1.5 2.5 3.5 4.5 VDD = 5V VREF (V) IDD (μA) 100 1.5 2 2.5 3

26412 G23

150 VDD = 3V

26412 G24

C L = 10pF CS 5V/DIV VOUT 1V/DIV 500ns/DIV

26412 G25

C L = 10pF VREF = 2.5V VDD = 5V CS 5V/DIV SETTLE RESIDUE 250μV/DIV 500ns/DIVLTC2641-16 VREF = 2.5V CONSULT FACTORY FOR MEASUREMENT CIRCUIT

26412 G26

VDD = VREF 0V TO 5.5V 2V/DIV 50ms/DIV

26412 G27

C L = 10pF

REF (Pin 1): Reference Voltage Input. Apply an external reference at REF between 2V and VDD. ⎯C⎯S (Pin 2): Serial Interface Chip Select/Load Input. When ⎯C⎯S is low, SCLK is enabled for shifting in data on DIN. When ⎯C⎯S is taken high, SCLK is disabled, the 16-bit input word is latched and the DAC is updated. SCLK (Pin 3): Serial Interface Clock Input. CMOS and TTL compatible. DIN (Pin 4): Serial Interface Data Input. Data is applied to DIN for transfer to the device at the rising edge of SCLK. ⎯C⎯L⎯R (Pin 5): Asynchronous Clear Input. A logic low clears the DAC to code 0. VOUT (Pin 6): DAC Output Voltage. The output range is 0V to VREF. VDD (Pin 7): Supply Voltage. Set between 2.7V and 5.5V. GND (Pin 8): Circuit Ground. Exposed Pad (DFN Pin 9): Circuit Ground. Must be sol- dered to PCB ground. LTC2642 REF (Pin 1): Reference Voltage Input. Apply an external reference at REF between 2V and VDD. ⎯C⎯S (Pin 2): Serial Interface Chip Select/Load Input. When ⎯C⎯S is low, SCLK is enabled for shifting in data on DIN. When ⎯C⎯S is taken high, SCLK is disabled, the 16-bit input word is latched and the DAC is updated SCLK (Pin 3): Serial Interface Clock Input. CMOS and TTL compatible. DIN (Pin 4): Serial Interface Data Input. Data is applied to DIN for transfer to the device at the rising edge of SCLK. ⎯C⎯L⎯R (Pin 5): Asynchronous Clear Input. A logic low clears the DAC to midscale. VOUT (Pin 6): DAC Output Voltage. The output range is 0V to VREF. INV (Pin 7): Center Tap of Internal Scaling Resistors. Connect to an external amplifi er’s inverting input in bipolar mode. R FB (Pin 8): Feedback Resistor. Connect to an external amplifi er’s output in bipolar mode. The bipolar output range is –V REF to VREF. VDD (Pin 9): Supply Voltage. Set between 2.7V and 5.5V. GND (Pin 10): Circuit Ground. Exposed Pad (DFN Pin 11): Circuit Ground. Must be soldered to PCB ground.

The LTC2641/LTC2642 family of 16-/14-/12-bit voltage output DACs offer full 16-bit performance with less than ±2LSB integral linearity error and less than ±1LSB differen- tial linearity error, guaranteeing monotonic operation. They operate from a single supply ranging from 2.7V to 5.5V, consuming 120μA (typical). An external voltage reference of 2V to V DD determines the DAC’s full-scale output volt- age. A 3-wire serial interface allows the LTC2641/LTC2642 to fi t into a small 8-/10-pin MSOP or DFN 3mm × 3mm package. Digital-to-Analog Architecture The DAC architecture is a voltage switching mode resis- tor ladder using precision thin-fi lm resistors and CMOS switches. The LTC2641/LTC2642 DAC resistor ladders are composed of a proprietary arrangement of matched DAC sections. The four MSBs are decoded to drive 15 equally weighted segments, and the remaining lower bits drive successively lower weighted sections. Major carry glitch impulse is very low at 500pV•sec, C L = 10pF, ten times lower than previous DACs of this type.

to ensure that the DAC ouput comes up in a known state. binary code tables for 16-bit, 14-bit and 12-bit operation.

26412 F02

Figure 2. 16-Bit Unipolar Output (LTC2641-16) Unipolar VOUT = 0V to VREF

a bipolar output swing from –VREF to VREF at the RFB pin. Figure 3. 16-Bit Bipolar Output (LTC2642-16) VOUT = –VREF to VREF

fastest settling time and minimum power consumption. part, is typically less than ±20%. LSB and 65,536 is rounded to 66k. 3pF corresponds to 1μs settling to 1/2LSB.

26412 F04

Figure 4. VOUT Pin Equivalent Circuit REF output range (Figure 3).

such as the LTC6078 is suitable, if the application does not require linear operation very near to GND, or zero scale (Figure 2). The LTC6078 typically swings to within 1mV of GND if it is not required to sink any load current. For an LSB size of 38μV, 1mV represents 26 missing codes near zero scale. Linearity will be degraded over a somewhat larger range of codes above GND. It is also unavoidable that settling time and transient performance will degrade whenever a single supply amplifi er is operated very close to GND, or to the positive supply rail. The small LSB size of a 16-bit DAC, coupled with the tight accuracy specifi cations on the LTC2641/LTC2642, means that the accuracy and input specifi cations for the external op amp are critical for overall DAC performance. Op Amp Specifi cations and Unipolar DAC Accuracy Most op amp accuracy specifi cations convert easily to DAC accuracy. Op amp input bias current on the noninverting (+) input is equivalent to an I L loading the DAC VOUT pin and therefore produces a DAC zero-scale error (ZSE) (see Unbuffered Operation): ZSE = –I B(IN+) • ROUT [Volts] In 16-bit LSBs: ZSE I IN k k V LSBB REF = () Op amp input impedance, R IN, is equivalent to an R L loading the LTC2641/LTC2642 VOUT pin, and produces a gain error of: GE k k R LSB IN + ⎛ []– 1 62 Op amp offset voltage, VOS, corresponds directly to DAC zero code offset error, ZSE: ZSE V k V LSBOS REF = []• 66 Temperature effects also must be considered. Over the –40°C to 85°C industrial temperature range, an offset voltage temperature coeffi cient (referenced to 25°C) of 0.6μV/°C will add 1LSB of zero-scale error. Also, IBIAS and the VOFFSET error it causes, will typically show signifi cant relative variation over temperature. Op amp open-loop gain, A VOL, contributes to DAC gain error (GE): GE k A LSB VOL = []66 Op amp input common mode rejection ratio (CMRR) is an input-referred error that corresponds to a combination of gain error (GE) and INL, depending on the op amp archi- tecture and operating conditions. A conservative estimate of total CMRR error is: Error V V CMRR CMRR RANGE RE 10 20 • _ FF kL S B⎛ ⎠⎟ []•6 6 where VCMRR_RANGE is the voltage range that CMRR (in dB) is specifi ed over. Op amp Typical Performance Charac- teristics graphs are useful to predict the impact of CMRR errors on DAC performance. Typically, a precision op amp will exhibit a fairly linear CMRR behavior (corresponding to DAC gain error only) over most of the common mode input range (CMR), and become nonlinear and produce signifi cant errors near the edge of the CMR. Rail-to-rail input op amps are a special case, because they have 2 distinct input stages, one with CMR to GND and the other with CMR to V +. This results in a “crossover” CM input region where operation switches between the two input stages. The LTC6078 rail-to-rail input op amp typically exhibits remarkably low crossover linearity error, as shown in the V OS vs VCM Typical Performance Characteristics graphs (see the LTC6078 data sheet). Crossover occurs at CM inputs about 1V below V +, and an LTC6078 operating as a unipolar DAC buffer with V REF = 2.5V and V+ = 5V will typically add only about 1LSB of GE and almost no INL error due to CMRR. Even in a full rail-to-rail application, with V REF = V+ = 5V, a typical LTC6078 will add only about 1LSB of INL at 16-bits.

Op Amp Specifi cations and Bipolar DAC Accuracy The op amp contributions to unipolar DAC error discussed above apply equally to bipolar operation. The bipolar ap- plication circuit gains up the DAC span, and all errors, by a factor of 2. Since the LSB size also doubles, the errors in LSBs are identical in unipolar and bipolar modes. One added error in bipolar mode comes from I B (IN–), which fl ows through RFB to generate an offset. The full bias current offset error becomes: V OFFSET = (IB (IN–) • RFB – IB (IN+) • ROUT • 2) [Volts] So: V I IN k I IN k k VOFFSET B B REF = () Settling Time with Op Amp Buffer When using an external op amp, the output settling time will still include the single pole settling on the LTC2641/LTC2642 V OUT node, with time constant ROUT • (COUT + CL) (see Un- buffered VOUT Settling Time). CL will include the buffer input capacitance and PC board interconnect capacitance. The external buffer amplifi er adds another pole to the output response, with a time constant equal to (fbandwidth/2π). For example, assume that C L is maintained at the same value as above, so that the V OUT node time constant is 83ns = 1μs/12. The output amplifi er pole will also have a time constant of 83ns if the closed-loop bandwidth equals (1/2π • 83ns) = 1.9MHz. The effective time constant of two cascaded single-pole sections is approximately the root square sum of the individual time constants, or √

• 83ns = 117ns, and 1/2 LSB settling time will be ~12 • 117ns = 1.4μs. This represents an ideal case, with no slew limiting and ideal op amp phase margin. In practice, it will take a considerably faster amplifi er, as well as careful attention to maintaining good phase margin, to approach the unbuffered settling time of 1μs. The output settling time for bipolar applications (Figure 3) will be somewhat increased due to the feedback resistor network R FB and RINV (each 28k nominal). The parasitic capacitance, CP, on the op amp (–) input node will introduce a feedback loop pole with a time constant of (CP • 28k/2). A small feedback capacitor, C1, should be included, to introduce a zero that will partially cancel this pole. C1 should nominally be <C P, typically in the range of 5pF to 10pF. This will restore the phase margin and improve coarse settling time, but a pole-zero doublet will unavoid- ably leave a slower settling tail, with a time constant of roughly (C P + C1) • 28k/2, which will limit 16-bit settling time to be greater than 2μs. Reference and GND Input The LTC2641/LTC2642 operates with external voltage refer- ences from 2V to VDD, and linearity, offset and gain errors are virtually unchanged vs VREF. Full 16-bit performance can be maintained if appropriate guidelines are followed when selecting and applying the reference. The LTC2641/ LTC2642’s very low gain error tempco of 0.1ppm/°C, typi- cal, corresponds to less than 0.5LSB variation over the –40°C to 85°C temperature range. In practice, this means that the overall gain error tempco will be determined almost entirely by the external reference tempco. The DAC voltage-switching mode “inverted” resistor ladder architecture used in the LTC2641/LTC2642 exhibits a refer- ence input resistance (R REF) that is code dependent (see the Typical Performance curves IREF vs Input Code). In unipolar mode, the minimum R REF is 14.8k (at code 871Chex, 34,588 decimal) and the the maximum RREF is 300k at code 0000hex (zero scale). The maximum change in I REF for a 2.5V reference is 160μA. Since the maximum occurs near midscale, the INL error is about one half of the change on V REF, so maintaining an INL error of <0.1LSB requires a reference load regulation of (1.53ppm • 2/160μA) = 19 [ppm/mA]. This implies a reference output impedance of 48mΩ, including series wiring resistance. To prevent output glitches from occuring when resistor ladder branches switch from GND to V REF, the reference input must maintain low impedance at higher frequencies. A 0.1μF ceramic capacitor with short leads between REF and GND provides high frequency bypassing. A surface mount ceramic chip capacitor is preferred because it has the lowest inductance. An additional 1μF between REF and GND provides low frequency bypassing. The circuit will benefi t from even higher bypass capacitance, as long as the external reference remains stable with the added capacative loading. APPLICATIONS INFORMATION

Digital Inputs and Interface Logic All of the digital inputs include Schmitt-trigger buffers to accept slow transition interfaces. This means that op- tocuplers can interface directly to the LTC2641/LTC2642 without additional external logic. Digital input hysteresis is typically 150mV. The digital inputs are compatible with TTL/CMOS-logic levels. However, rail-to-rail (CMOS) logic swings are preferred, because operating the logic inputs away from the supply rails generates additional I DD and GND current, (see Typical Performance Characteristic graph Supply Current vs Logic Input Voltage). Digital feedthrough is only 0.2nV•s typical, but it is always preferred to keep all logic inputs static except when loading a new code into the DAC. Board Layout for Precision Even a small amount of board leakage can degrade ac- curacy. The 6nA leakage current into V OUT needed to generate 1LSB offset error corresponds to 833MΩ leakage resistance from a 5V supply. The VOUT node is relatively sensitive to capacitive noise coupling, so minimum trace length, appropriate shielding and clean board layout are imperative here. Temperature differences at the DAC, op amp or reference pins can easily generate tens of microvolts of thermo- couple voltages. Analog signal traces should be short, close together and away from heat dissipating compo- nents. Air currents across the board can also generate thermocouples. The PC board should have separate areas for the analog and digital sections of the circuit. A single, solid ground plane should be used, with analog and digital signals carefully routed over separate areas of the plane. This keeps digital signals away from sensitive analog signals and minimizes the interaction between digital ground currents and the analog section of the ground plane. A “star ground” area should be established by attaching the LTC2641/LTC2642 GND pin, V REF GND and the DAC VOUT GND reference terminal to the same area on the GND plane. Care should be taken to ensure that no large GND return current paths fl ow through the “star GND” area. In particular, the resistance from the LTC2641 GND pin to the point where the V REF input source connects to the ground plane should be as low as possible. Excessive resistance here will be multiplied by the code dependent I REF current to produce an INL error similar to the error produced by V REF source resistance. Sources of ground return current in the analog area include op amp power supply bypass capacitors and the GND connection for single supply amps. A useful technique for minimizing errors is to use a separate board layer for power ground return connections, and reserve one ground plane layer for low current “signal” GND connec- tions. The “signal”, or “star” GND plane must connected to the “power” GND plane at a single point, which should be located near the LTC2641/LTC2642 GND pin. If separate analog and digital ground areas exist it is neces- sary to connect them at a single location, which should be fairly close to the DAC for digital signal integrity. In some systems, large GND return currents can fl ow between the digital and analog GNDs, especially if different PC boards are involved. In such cases the digital and analog ground connection point should not be made right at the “star” GND area, so the highly sensitive analog signals are not corrupted. If forced to choose, always place analog ground quality ahead of digital signal ground. (A few mV of noise on the digital inputs is imperceptible, thanks to the digital input hysteresis) Just by maintaining separate areas on the GND plane where analog and digital return currents naturally fl ow, good results are generally achieved. Only after this has been done, it is sometimes useful to interrupt the ground plane with strategically placed “slots”, to prevent the digital ground currents from fringing into the analog portion of the plane. When doing this, the gap in the plane should be only as long as it needs to be to serve its purpose. Caution: if a GND plane gap is improperly placed, so that it interrupts a signifi cant GND return path, or if a signal traces crosses over the gap, then adding the gap may greatly degrade performance! In this case, the GND and signal return currents are forced to fl ow the long way around the gap, and then are typically channeled directly into the most sensitive area of the analog GND plane. APPLICATIONS INFORMATION

3.00 ±0.10 (4 SIDES) NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON TOP AND BOTTOM OF PACKAGE 0.38 ± 0.10 BOTTOM VIEW—EXPOSED PAD 1.65 ± 0.10 (2 SIDES) 0.75 ±0.05 R = 0.115 TYP 2.38 ±0.10 (2 SIDES) PIN 1 TOP MARK (NOTE 6)

0.200 REF

0.00 – 0.05 (DD) DFN 1203 0.25 ± 0.05 2.38 ±0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 1.65 ±0.05 (2 SIDES)2.15 ±0.05 0.50 BSC 0.675 ±0.05 3.5 ±0.05 PACKAGE OUTLINE 0.25 ± 0.05

0.50 BSC

3.00 ±0.10 (4 SIDES) NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2). CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 0.38 ± 0.10 BOTTOM VIEW—EXPOSED PAD 1.65 ± 0.10 (2 SIDES) 0.75 ±0.05 R = 0.115 TYP 2.38 ±0.10 (2 SIDES) 106 PIN 1 TOP MARK (SEE NOTE 6) 0.00 – 0.05 (DD) DFN 1103 0.25 ± 0.05 2.38 ±0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 1.65 ±0.05 (2 SIDES)2.15 ±0.05 0.50 BSC 0.675 ±0.05 3.50 ±0.05 PACKAGE OUTLINE 0.25 ± 0.05 8-Lead Plastic DFN (3mm × 3mm) (Reference LTC DWG # 05-08-1698) 10-Lead Plastic DFN (3mm × 3mm) (Reference LTC DWG # 05-08-1699)

Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. PACKAGE DESCRIPTION 8-Lead Plastic MSOP (Reference LTC DWG # 05-08-1660 Rev F) MSOP (MS8) 0307 REV F 0.53 ± 0.152 (.021 ± .006) SEATING PLANE NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 0.18 (.007) 0.254 (.010) 1.10 (.043) MAX 0.22 – 0.38 (.009 – .015) TYP 0.1016 ± 0.0508 (.004 ± .002) 0.86 (.034) REF 0.65 (.0256) BSC 0° – 6° TYP DETAIL “A” DETAIL “A” GAUGE PLANE 12 3 4 4.90 ± 0.152 (.193 ± .006) 8 7 6 5 3.00 ± 0.102 (.118 ± .004) (NOTE 3) 3.00 ± 0.102 (.118 ± .004) (NOTE 4) 0.52 (.0205) REF 5.23 (.206) MIN 3.20 – 3.45 (.126 – .136) 0.889 ± 0.127 (.035 ± .005) RECOMMENDED SOLDER PAD LAYOUT 0.42 ± 0.038 (.0165 ± .0015) TYP 0.65 (.0256) BSC 10-Lead Plastic MSOP (Reference LTC DWG # 05-08-1661 Rev E) MSOP (MS) 0307 REV E 0.53 ± 0.152 (.021 ± .006) SEATING PLANE 0.18 (.007) 1.10 (.043) MAX 0.17 – 0.27 (.007 – .011) TYP 0.86 (.034) REF 0.50 (.0197) BSC 12 3 45 4.90 ± 0.152 (.193 ± .006) 0.497 ± 0.076 (.0196 ± .003) REF8910 7 6 3.00 ± 0.102 (.118 ± .004) (NOTE 3) 3.00 ± 0.102 (.118 ± .004) (NOTE 4) NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 0.254 (.010) 0° – 6° TYP DETAIL “A” DETAIL “A” GAUGE PLANE 5.23 (.206) MIN 3.20 – 3.45 (.126 – .136) 0.889 ± 0.127 (.035 ± .005) RECOMMENDED SOLDER PAD LAYOUT 0.305 ± 0.038 (.0120 ± .0015) TYP 0.50 (.0197) BSC 0.1016 ± 0.0508 (.004 ± .002)

Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2007 LT 0707 • PRINTED IN USA RELATED PARTS TYPICAL APPLICATION PART NUMBER DESCRIPTION COMMENTS DACs LTC1588/LTC1589 LTC1592 12-/14-/16-Bit SoftSpan TM Current Output DACs Software Programmable Output Ranges up to ±10V LTC1595/LTC1596 Serial 16-Bit Current Output DACs Low Glitch, ±1LSB Maximum INL, DNL LTC1591/LTC1597 Parallel 14-/16-Bit Current Output DACs ±1LSB Max INL, DNL, ±10V Output LTC1599 16-Bit Current Output DAC ±1LSB Max INL, DNL, ±10V Output LTC1650 16-Bit Voltage Output DAC 2nV•s Glitch Impulse, 30nV/√Hz Noise LTC2621/LTC2611 LTC2601 12-/14-/16-Bit Serial Voltage Output DACs Single DACs, Single Supply, 0V to 5V Outputs in DFN10 LTC2704-12 LTC2704-14 LTC2704-16 12-/14-/16-Bit Quad Voltage Output DACs Software Programmable Output Ranges up to ±10V, Serial I/O Op Amps LT ®1678 Dual Low Noise Rail-to-Rail Precision Op Amp 3.9nV/√Hz at 1MHz LTC2054 Micropower Zero Drift Op Amp 3μV Maximum Offset LT6010 150μA 8nV/√Hz Rail-to-Rail Output Precision Op Amp Micropower LTC6078 Dual CMOS Rail-to-Rail Input/Output Amplifi er 54μA per Amp, 16nV/√Hz Input Noise Voltage References LT1019 Precision Bandgap Reference 0.005% Max, 5ppm/°C Max SoftSpan is a trademark of Linear Technology Corporation. Wide Range Current Load Sinks 0A to 2.5A +16-BIT DAC LTC2054HV 10V VREF 2.5V ISINK 0A TO 2.5A VDD LTC2641-16 4.7μF 0.1μF 0.033μF 10W IRLZ44 REF VOUT GND

26412 TA02

0.1μF0.1μF 2 CS SCLK DIN CLR LT1019CS8-2.5 GND OUT 5V IN 10k