LCT1414

LTC2356-12_12 LINER

Document overview

• Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 18

Technical content

FEATURES

APPLICATIONS

DESCRIPTION

Serial 12-Bit/14-Bit, 3.5Msps Sampling ADCs with Shutdown The L TC®2356-12/L TC2356-14 are 12-bit/14-bit, 3.5Msps serial ADCs with differential inputs. The devices draw only 5.5mA from a single 3.3V supply and come in a tiny 10-lead MSOP package. A Sleep shutdown feature further reduces power consumption to 13µW . The com- bination of speed, low power and tiny package makes the L TC2356-12/L TC2356-14 suitable for high speed, portable applications. The 80dB common mode rejection allows users to eliminate ground loops and common mode noise by measuring signals differentially from the source. The devices convert –1.25V to 1.25V bipolar inputs differentially. The absolute voltage swing for A IN+ and AIN– extends from ground to the supply voltage. The serial interface sends out the conversion results during the 16 clock cycles following a CONV rising edge for com- patibility with standard serial interfaces. If two additional clock cycles for acquisition time are allowed after the data stream in between conversions, the full sampling rate of 3.5Msps can be achieved with a 63MHz clock. L, L T , L TC, L TM, Linear Technology and the Linear logo are registered trademarks and SoftSpan is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. n 3.5Msps Conversion Rate n 74.1dB SINAD at 14-Bits, 71.1dB SINAD at 12-Bits n Low Power Dissipation: 18mW n 3.3V Single Supply Operation n 2.5V Internal Bandgap Reference can be Overdriven n 3-Wire SPI-Compatible Serial Interface n Sleep (13µW) Shutdown Mode n Nap (4mW) Shutdown Mode n 80dB Common Mode Rejection n ±1.25V Bipolar Input Range n Tiny 10-Lead MSOP Package n Communications n Data Acquisition Systems n Uninterrupted Power Supplies n Multiphase Motor Control n Multiplexed Data Acquisition n RFID THD, 2nd and 3rd vs Input Frequency for Differential Input Signals 2356 BD S & H GND EXPOSED PAD L TC2356-14 VREF 10µF AIN– AIN+ 14-BIT ADC 3.3V 10µF 14-BIT LATCH THREE- STATE SERIAL OUTPUT PORT 2.5V REFERENCE TIMING LOGIC VDD SDO CONV SCK 5 6 11 FREQUENCY (MHz) 0.1 –80THD, 2nd, 3rd (dB) –74 –68 –62 –56 1 10 100

2356 G02

–86 –92 –98 –104 –50 THD 2nd 3rd

(Notes 1, 2) Analog and VREF Input Voltages Operation Temperature Range ABSOLUTE MAXIMUM RATINGSABSOLUTE MAXIMUM RATINGS CONVERTER CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. With internal reference. VDD = 3.3V . PARAMETER CONDITIONS L TC2356-12 L TC2356-14 UNITSMIN TYP MAX MIN TYP MAX Resolution (No Missing Codes) l 12 14 Bits Integral Linearity Error (Notes 4, 5, 18) l –2 ±0.25 2 –4 ±0.5 4 LSB Offset Error (Notes 4, 18) l –10 ±1 10 –30 ±2 30 LSB Gain Error (Note 4, 18) l –40 ±5 40 –80 ±10 80 LSB Gain Tempco Internal Reference (Note 4) External Reference ±15 ±15 ppm/°C ppm/°C ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE L TC2356CMSE-12#PBF L TC2356CMSE-12#TRPBF L TCWN 10-Lead Plastic MSOP 0°C to 70°C L TC2356IMSE-12#PBF L TC2356IMSE-12#TRPBF L TCWN 10-Lead Plastic MSOP –40°C to 85°C L TC2356CMSE-14#PBF L TC2356CMSE-14#TRPBF L TCVF 10-Lead Plastic MSOP 0°C to 70°C L TC2356IMSE-14#PBF L TC2356IMSE-14#TRPBF L TCVF 10-Lead Plastic MSOP –40°C to 85°C Consult L TC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container . Consult L TC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear .com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear .com/tapeandreel/ PIN CONFIGURATION A IN+ AIN– VREF GND GND CONV SCK SDO V DD GND TOP VIEW MSE PACKAGE 10-LEAD PLASTIC MSOP TJMAX = 125°C, θJA = 40°C/W EXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB

DYNAMIC ACCURACY The l denotes the specifications which apply over the full operating temperature range, DC. Differential signal drive with VCM = 1.5V at AIN+ and AIN– ANALOG INPUT The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. With internal reference. VDD = 3.3V . SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VIN Analog Differential Input Range (Notes 3, 8, 9) 3.1V ≤ VDD ≤ 3.6V l –1.25 to 1.25 V VCM Analog Common Mode + Differential Input Range (Note 10) 0 to VDD V IIN Analog Input Leakage Current l 1 µA CIN Analog Input Capacitance (Note 19) 13 pF tACQ Sample-and-Hold Acquisition Time (Note 6) l 39 ns tAP Sample-and-Hold Aperture Delay Time 1 ns tJITTER Sample-and-Hold Aperture Delay Time Jitter 0.3 ps CMRR Analog Input Common Mode Rejection Ratio fIN = 1MHz, VIN = 0V to 3V fIN = 100MHz, VIN = 0V to 3V –60 –15 dB dB SYMBOL PARAMETER CONDITIONS L TC2356-12 L TC2356-14 UNITSMIN TYP MAX MIN TYP MAX SINAD Signal-to-Noise Plus Distortion Ratio 100kHz Input Signal (Note 19) 1.4MHz Input Signal (Note 19) l 71.1 71.1 74.1 72.3 dB dB THD Total Harmonic Distortion 100kHz First 5 Harmonics (Note 19) 1.4MHz First 5 Harmonics (Note 19) l –86 –82 –76 –86 –82 –78 dB dB SFDR Spurious Free Dynamic Range 100kHz Input Signal (Note 19) 1.4MHz Input Signal (Note 19) dB dB IMD Intermodulation Distortion 0.625V P-P to 1.4MHz Summed with 0.625VP-P 1.56MHz into AIN+ and Inverted into AIN– –82 –82 dB Code-to-Code T ransition Noise V REF = 2.5V (Note 18) 0.25 1 LSBRMS Full Power Bandwidth VIN = 2.5VP-P, SDO = 11585LSBP-P (Note 15) 50 50 MHz Full Linear Bandwidth S/(N + D) ≥ 68dB 5 5 MHz PARAMETER CONDITIONS MIN TYP MAX UNITS VREF Output Voltage IOUT = 0 2.5 V VREF Output Tempco 15 ppm/°C VREF Line Regulation VDD = 3.1V to 3.6V , VREF = 2.5V 600 µV/V VREF Output Resistance Load Current = 0.5mA 0.2 Ω VREF Settling Time CREF = 10µF 2 ms External VREF Input Range 2.55 VDD V INTERNAL REFERENCE CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VDD = 3.3V .

POWER REQUIREMENTS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 17) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VDD Supply Voltage 3.1 3.3 3.6 V IDD Supply Current Active Mode Nap Mode Sleep Mode (L TC2356-12) Sleep Mode (L TC2356-14) l l 5.5 1.1 1.5 mA mA µA µA P D Power Dissipation Active Mode with SCK in Fixed State (Hi or Lo) 18 mW DIGITAL INPUTS AND DIGITAL OUTPUTS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VDD = 3.3V . SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VIH High Level Input Voltage VDD = 3.6V l 2.4 V VIL Low Level Input Voltage VDD = 3.1V l 0.6 V IIN Digital Input Current VIN = 0V to VDD l ±10 µA CIN Digital Input Capacitance 5 pF VOH High Level Output Voltage VDD = 3.3V , IOUT = –200µA l 2.5 2.9 V VOL Low Level Output Voltage VDD = 3.1V , IOUT= 160µA VDD = 3.1V , IOUT = 1.6mA l 0.05 0.10 0.4 V V I OZ Hi-Z Output Leakage DOUT VOUT = 0V to VDD l ±10 µA COZ Hi-Z Output Capacitance DOUT 1 pF ISOURCE Output Short-Circuit Source Current VOUT = 0V , VDD = 3.3V 20 mA ISINK Output Short-Circuit Sink Current VOUT = VDD = 3.3V 15 mA

Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to GND. Note 3: When these pins are taken below GND or above V DD, they will be clamped by internal diodes. This product can handle input currents greater than 100mA below GND or greater than VDD without latchup. Note 4: Offset and full-gain specifications are measured for a single-ended A IN+ input with AIN– grounded and using the internal 2.5V reference. Note 5: Integral linearity is tested with an external 2.55V reference and is defined as the deviation of a code from the straight line passing through the actual endpoints of a transfer curve. The deviation is measured from the center of quantization band. Note 6: Guaranteed by design, not subject to test. Note 7: Recommended operating conditions. Note 8: The analog input range is defined for the voltage difference between A IN+ and AIN–. Performance is specified with AIN– = 1.5V DC while driving AIN+. Note 9: The absolute voltage at AIN+ and AIN– must be within this range. Note 10: If less than 3ns is allowed, the output data will appear one clock cycle later . It is best for CONV to rise half a clock before SCK, when running the clock at rated speed. The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VDD = 3.3V . SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS fSAMPLE(MAX) Maximum Sampling Rate per Channel (Conversion Rate) l 3.5 MHz tTHROUGHPUT Minimum Sampling Period (Conversion + Acquisiton Period) l 286 ns tSCK Clock Period (Note 16) l 15.872 10000 ns tCONV Conversion Time (Note 6) 16 18 SCLK cycles t1 Minimum High or Low SCLK Pulse Width (Note 6) 2 ns t2 CONV to SCK Setup Time (Notes 6, 10) 3 ns t3 Nearest SCK Edge Before CONV (Note 6) 0 ns t4 Minimum High or Low CONV Pulse Width (Note 6) 4 ns t5 SCK↑ to Sample Mode (Note 6) 4 ns t6 CONV↑ to Hold Mode (Notes 6, 11) 1.2 ns t7 16th SCK↑ to CONV≠ Interval (Affects Acquisition Period) (Notes 6, 7, 13) 45 ns t8 Delay from SCK to Valid Data (Notes 6, 12) 8 ns t9 SCK↑ to Hi-Z at SDO (Notes 6, 12) 6 ns t10 Previous SDO Bit Remains Valid After SCK (Notes 6, 12) 2 ns t12 VREF Settling Time After Sleep-to-Wake T ransition (Note 14) 2 ms Note 11: Not the same as aperture delay. Aperture delay is smaller (1ns) because the 2.2ns delay through the sample-and-hold is subtracted from the CONV to Hold mode delay. Note 12: The rising edge of SCK is guaranteed to catch the data coming out into a storage latch. Note 13: The time period for acquiring the input signal is started by the 16th rising clock and it is ended by the rising edge of convert. Note 14: The internal reference settles in 2ms after it wakes up from Sleep mode with one or more cycles at SCK and a 10µF capacitive load. Note 15: The full power bandwidth is the frequency where the output code swing drops to 3dB with a 2.5V P-P input sine wave. Note 16: Maximum clock period guarantees analog performance during conversion. Output data can be read with an arbitrarily long clock. Note 17: VDD = 3.3V , fSAMPLE = 3.5Msps. Note 18: The L TC2356-14 is measured and specified with 14-bit resolution (1LSB = 152µV) and the L TC2356-12 is measured and specified with 12-bit resolution (1LSB = 610µV). Note 19: The sampling capacitor at each input accounts for 4.1pF of the input capacitance.

TYPICAL PERFORMANCE CHARACTERISTICS SINAD vs Input Frequency SFDR vs Input Frequency THD, 2nd and 3rd vs Input Frequency SNR vs Input Frequency 1.4MHz Sine Wave 8192 Point FFT Plot 100kHz Sine Wave 8192 Point FFT Plot FREQUENCY (MHz) 0.1 SINAD (dB) 1 10 100

2356 G01

FREQUENCY (MHz) 0.1 –80THD, 2nd, 3rd (dB) –74 –68 –62 –56 1 10 100 –86 –92 –98 –104 –50 THD 2nd 3rd FREQUENCY (MHz) 0.1 SFDR (dB) 1 10 100

2356 G03

FREQUENCY (MHz) 0.1 SNR (dB) 1 10 100

2356 G04

FREQUENCY (Hz) MAGNITUDE (dB) –90 –30 –20 –10 500k 1M 1.25M

2356 G05

–110 –50 –70 –100 –40 –120 –60 –80 250k 750k 1.5M 1.75M FREQUENCY (Hz) MAGNITUDE (dB) –90 –30 –20 –10 500k 1M 1.25M

2356 G06

–110 –50 –70 –100 –40 –120 –60 –80 250k 750k 1.5M 1.75M TA = 25°C, VDD = 3.3V (L TC2356-14)

2356 G07

–1.0 DIFFERENTIAL LINEARITY (LSB) –0.8 –0.4 –0.2 1.0 0.4 4096 8192 –0.6 0.6 0.8 0.2 12288 16384 OUTPUT CODE INTEGRAL LINEARITY (LSB) 16384

2356 G08

CONVERSION RATE (Msps) 2.0 SINAD (dB) 3.6

2356 G10

CONVERSION RATE (Msps) 2.0 LINEARITY (LSB) 3.6

2356 G09

FREQUENCY (Hz) 1M 10M 100M 1G –18AMPLITUDE (dB) –12

2356 G11

–24 –30 –36 FREQUENCY (Hz) 100 CMRR (dB) –20 –40 –60 –80 –100 –120 1k 10k 100k 1M

2356 G12

TYPICAL PERFORMANCE CHARACTERISTICS SINAD vs Conversion Rate, Input Frequency = 1.4MHz Differential and Integral Linearity vs Conversion Rate 2.5V P-P Power Bandwidth CMRR vs Frequency Differential Linearity vs Output Code Integral Linearity vs Output Code TA = 25°C, VDD = 3.3V (L TC2356-14)

CONVERSION RATE (Mps) VDD SUPPL Y CURRENT (mA) 0.5 1.5 2.5 3.5 5.5 0.5 1 1.5 2

2356 G16

2.5 3.5 3 4 4.5 VDD (V)

2.4890 VREF (V)

2.4894 2.4898 2.4902 2.4892 2.4896 2.4900 2.8 3.0 3.2 3.4

2356 G15

2.6 3.6 FREQUENCY (Hz) 1 10 –50PSRR (dB) –45 –40 –35 –30 100 1k 10k 100k 1M

2356 G13

–55 –60 –65 –70 –25 LOAD CURRENT (mA) 0.4 0.8 1.2 1.6

2356 G14

2.4894 2.4898 2.4902 2.4892 2.4896 2.4900 TYPICAL PERFORMANCE CHARACTERISTICSTA = 25°C, VDD = 3.3V (L TC2356-12 and L TC2356-14) Internal Reference Voltage vs Load Current Internal Reference Voltage vs VDD VDD Supply Current vs Conversion Rate PSRR vs Frequency

S & H GND EXPOSED PAD L TC2356-14 VREF 10µF AIN– AIN+ 14-BIT ADC 3.3V 10µF 14-BIT LATCH THREE- STATE SERIAL OUTPUT PORT 2.5V REFERENCE TIMING LOGIC VDD SDO CONV SCK 5 6 11 PIN FUNCTIONS AIN+ (Pin 1): Noninverting Analog Input. A IN+ operates fully differentially with respect to A IN– with a –1.25V to 1.25V differential swing with respect to AIN– and a 0V to VDD common mode swing. AIN– (Pin 2): Inverting Analog Input. A IN– operates fully differentially with respect to AIN+ with a 1.25V to –1.25V differential swing with respect to A IN+ and a 0V to V DD common mode swing. VREF (Pin 3): 2.5V Internal Reference. Bypass to GND and to a solid analog ground plane with a 10µF ceramic capacitor (or 10µF tantalum in parallel with 0.1µF ceramic). Can be overdriven by an external reference between 2.55V and V DD. GND (Pins 4, 5, 6, 11): Ground and Exposed Pad. These ground pins and the exposed pad must be tied directly to the solid ground plane under the part. Keep in mind that analog signal currents and digital output signal currents flow through these pins. V DD (Pin 7): 3.3V Positive Supply. This single power pin supplies 3.3V to the entire device. Bypass to GND and to a solid analog ground plane with a 10µF ceramic capacitor (or 10µF tantalum in parallel with 0.1µF ceramic). Keep in mind that internal analog currents and digital output signal currents flow through this pin. Care should be taken to place the 0.1µF bypass capacitor as close to Pins 6 and 7 as possible. SDO (Pin 8): Three-State Serial Data Output. Each set of output data words represents the difference between A IN+ and AIN– analog inputs at the start of the previous conversion. The output format is 2’s complement. SCK (Pin 9): External Clock Input. Advances the conver- sion process and sequences the output data on the rising edge. Responds to TTL (≤3.3V) and 3.3V CMOS levels. One or more pulses wake from sleep. CONV (Pin 10): Convert Start. Holds the analog input signal and starts the conversion on the rising edge. Responds to TTL (≤3.3V) and 3.3V CMOS levels. T wo CONV pulses with SCK in fixed high or fixed low state start Nap mode. Four or more CONV pulses with SCK in fixed high or fixed low state start Sleep mode. BLOCK DIAGRAM

Nap Mode and Sleep Mode Waveforms SCK to SDO Delay L TC2356-12 Timing Diagram L TC2356-14 Timing Diagram SCK CONV INTERNAL S/H STATUS SDO t7t3 t1 1 18 17 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 t4 t5 t8 t9 tACQ SAMPLE HOLD HOLD Hi-Z Hi-Z tCONV 14-BIT DATA WORD SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION *BITS MARKED "X" AFTER D0 SHOULD BE IGNORED. tTHROUGHPUT

2356 TD01

D11 D10 D8 D7 D6 D5 D4 D3 D2 D1 D0 X* X*D9 SAMPLE SCK CONV INTERNAL S/H STATUS SDO t7t3 t1 1 18 17 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 t4 t5 t8 t9 tACQ SAMPLE HOLD HOLD Hi-Z Hi-Z tCONV 14-BIT DATA WORD SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION tTHROUGHPUT

2356 TD01b

D13 D12 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0D11 SAMPLE SCK CONV NAP SLEEP VREF t12 NOTE: NAP AND SLEEP ARE INTERNAL SIGNALS

2356 TD02

2356 TD03

90% 10%

The differential analog inputs of the L TC2356-12/L TC2356-14 may be driven differentially or as a single-ended input (i.e., the AIN– input is set to VCM). Both differential analog inputs, AIN+ and A IN–, are sampled at the same instant. Any unwanted signal that is common to both inputs of each input pair will be reduced by the common mode rejec - tion of the sample-and-hold circuit. The inputs draw only one small current spike while charging the sample- and-hold capacitors at the end of conversion. During conversion, the analog inputs draw only a small leakage current. If the source impedance of the driving circuit is low, then the L TC2356-12/L TC2356-14 inputs can be driven directly. As source impedance increases, so will acquisition time. For minimum acquisition time with high source impedance, a buffer amplifier must be used. The main requirement is that the amplifier driving the analog input(s) must settle after the small current spike before the next conversion starts (settling time must be 39ns for full throughput rate). Also keep in mind while choosing an input amplifier the amount of noise and harmonic distortion added by the amplifier . CHOOSING AN INPUT AMPLIFIER Choosing an input amplifier is easy if a few requirements are taken into consideration. First, to limit the magnitude of the voltage spike seen by the amplifier from charging the sampling capacitor , choose an amplifier that has a low output impedance (<100Ω) at the closed-loop bandwidth frequency. For example, if an amplifier is used with a gain of 1 and has a unity-gain bandwidth of 50MHz, then the output impedance at 50MHz must be less than 100Ω. The second requirement is that the closed-loop bandwidth must be greater than 40MHz to ensure adequate small-signal settling for full throughput rate. If slower op amps are used, more time for settling can be provided by increasing the time between conversions. The best choice for an op amp to drive the L TC2356-12/ L TC2356-14 will depend on the application. Generally, ap- plications fall into two categories: AC applications where dynamic specifications are most critical and time domain applications where DC accuracy and settling time are most critical. The following list is a summary of the op amps that are suitable for driving the L TC2356-12/L TC2356-14. (More APPLICATIONS INFORMATION detailed information is available in the Linear Technology Databooks and our website at www.linear .com.) L TC1566-1: Low Noise 2.3MHz Continuous Time Low- Pass Filter . LT ®1630: Dual 30MHz Rail-to-Rail Voltage FB Amplifier . 2.7V to ±15V supplies. Very high AVOL, 500µV offset and 520ns settling to 0.5LSB for a 4V swing. THD and noise are –93dB to 40kHz and below 1LSB to 320kHz (AV = 1, 2VP-P into 1kΩ, VS = 5V), making the part excellent for AC applications (to 1/3 Nyquist) where rail-to-rail perfor- mance is desired. Quad version is available as L T1631. L T1632: Dual 45MHz Rail-to-Rail Voltage FB Amplifier . 2.7V to ±15V supplies. Very high AVOL, 1.5mV offset and 400ns settling to 0.5LSB for a 4V swing. It is suitable for applications with a single 5V supply. THD and noise are –93dB to 40kHz and below 1LSB to 800kHz (A V = 1, 2VP-P into 1kΩ, VS = 5V), making the part excellent for AC applications where rail-to-rail performance is desired. Quad version is available as L T1633. L T1813: Dual 100MHz 750V/µs 3mA Voltage Feedback Amplifier . 5V to ±5V supplies. Distortion is –86dB to 100kHz and –77dB to 1MHz with ±5V supplies (2VP-P into 500Ω). Excellent part for fast AC applications with ±5V supplies. L T1801: 80MHz GBWP , –75dBc at 500kHz, 2mA/Amplifier , 8.5nV/√Hz. L T1806/L T1807: 325MHz GBWP , –80dBc Distortion at 5MHz, Unity-Gain Stable, R-R In and Out, 10mA/Ampli - fier , 3.5nV/√Hz. L T1810: 180MHz GBWP , –90dBc Distortion at 5MHz, Unity- Gain Stable, R-R In and Out, 15mA/Amplifier , 16nV/√Hz. L T1818/L T1819: 400MHz, 2500V/µs,9mA, Single/Dual Voltage Mode Operational Amplifier . L T6200: 165MHz GBWP , –85dBc Distortion at 1MHz, Unity-Gain Stable, R-R In and Out, 15mA/Amplifier , 0.95nV/√Hz. L T6203: 100MHz GBWP , –80dBc Distortion at 1MHz, Unity-Gain Stable, R-R In and Out, 3mA/Amplifier , 1.9nV/√Hz. L T6600-10: Amplifier/Filter Differential In/Out with 10MHz Cutoff.

2356 F03

2356 F01

51Ω source resistor to limit the input bandwidth to 47MHz. Figure 1. RC Input Filter Figure 2. AC Coupling of AC Signals with 1kHz Figure 3. Overdriving VREF Pin with an External Reference

2356 F06a

2356 F05

2356 F04

Figure 3. The voltage of the external reference must be load of 0.75mA and as much as 3mA during conversion. 0.1% of the common mode voltage. Figure 4. CMRR vs Frequency Figure 5. L TC2356-12/L TC2356-14 T ransfer Characteristic

2356 F07

2356 F06b

wires should be kept matched. using three-state buffers to isolate the ADC data bus. can start an accurate conversion within a clock cycle. ence (VREF ) takes 2ms to slew and settle with a 10µF load. Figure 7. Recommended Layout

Note that, using sleep mode more frequently than every 2ms, compromises the settled accuracy of the internal reference. Note that, for slower conversion rates, the Nap and Sleep modes can be used for substantial reductions in power consumption. DIGITAL INTERFACE The L TC2356-12/L TC2356-14 has a 3-wire SPI-compatible (Serial Protocol Interface) interface. The SCK and CONV inputs and SDO output implement this interface. The SCK and CONV inputs accept swings from 3.3V logic and are TTL compatible, if the logic swing does not exceed V DD. A detailed description of the three serial port signals follows. Conversion Start Input (CONV) The rising edge of CONV starts a conversion, but subse- quent rising edges at CONV are ignored by the L TC2356-12/ L TC2356-14 until the following 16 SCK rising edges have occurred. It is necessary to have a minimum of 16 rising edges of the clock input SCK between rising edges of CONV . But to obtain maximum conversion speed (with a 63MHz SCK), it is necessary to allow two more clock periods between conversions to allow 39ns of acquisition time for the internal ADC sample-and-hold circuit. With 16 clock periods per conversion, the maximum conversion rate is limited to 3.5Msps to allow 39ns for acquisition time. In either case, the output data stream comes out within the first 16 clock periods to ensure compatibility with processor serial ports. The duty cycle of CONV can be arbitrarily chosen to be used as a frame sync signal for the processor serial port. A simple approach to generate CONV is to create a pulse that is one SCK wide to drive the L TC2356-12/L TC2356-14 and then buffer this signal with the appropriate number of inverters to ensure the cor - rect delay driving the frame sync input of the processor serial port. It is good practice to drive the L TC2356-12/ L TC2356-14 CONV input first to avoid digital noise inter- ference during the sample-to-hold transition triggered by CONV at the start of conversion. It is also good practice to keep the width of the low portion of the CONV signal greater than 15ns to avoid introducing glitches in the front end of the ADC just before the sample-and-hold goes into hold mode at the rising edge of CONV . Minimizing Jitter on the CONV Input In high speed applications where high amplitude sine waves above 100kHz are sampled, the CONV signal must have as little jitter as possible (10ps or less). The square wave output of a common crystal clock module usually meets this requirement . The challenge is to generate a CONV signal from this crystal clock without jitter corruption from other digital circuits in the system. A clock divider and any gates in the signal path from the crystal clock to the CONV input should not share the same integrated circuit with other parts of the system. As shown in Figure 8, the SCK and CONV inputs should be driven first, with digital buffers used to drive the serial port interface. Also note that the master clock in the DSP may already be corrupted with jitter , even if it comes directly from the DSP crystal. Another problem with high speed processor clocks is that they often use a low cost, low speed crystal (i.e., 10MHz) to generate a fast, but jittery, phase-locked-loop system clock (i.e., 40MHz). The jitter in these PLL-generated high speed clocks can be several nanoseconds. Note that if you choose to use the frame sync signal generated by the DSP port, this signal will have the same jitter of the DSP’s master clock. The Typical Application Figure on page 16 shows a cir - cuit for level-shifting and squaring the output from an RF signal generator or other low-jitter source. A single D-type flip flop is used to generate the CONV signal to the L TC2356-12/L TC2356-14. Re-timing the master clock signal eliminates clock jitter introduced by the controlling device (DSP , FPGA, etc.) Both the inverter and flip flop must be treated as analog components and should be powered from a clean analog supply. Serial Clock Input (SCK) The rising edge of SCK advances the conversion process and also udpates each bit in the SDO data stream. After CONV rises, the third rising edge of SCK starts clocking out the 12/14 data bits with the MSB sent first. A simple approach is to generate SCK to drive the L TC2356-12/ L TC2356-14 first and then buffer this signal with the appropriate number of inverters to drive the serial clock input of the processor serial port. Use the falling edge of the clock to latch data from the Serial Data Output (SDO)

into your processor serial port. The 14-bit serial data will be received right justified, in a 16-bit word with 16 or more clocks per frame sync. It is good practice to drive the L TC2356-12/L TC2356-14 SCK input first to avoid digi- tal noise interference during the internal bit comparison decision by the internal high speed comparator . Unlike the CONV input, the SCK input is not sensitive to jitter because the input signal is already sampled and held constant. Serial Data Output (SDO) Upon power-up, the SDO output is automatically reset to the high impedance state. The SDO output remains in high impedance until a new conversion is started. SDO sends out 12/14 bits in 2’s complement format in the output data stream beginning at the third rising edge of SCK after the rising edge of CONV . SDO is always in high impedance mode when it is not sending out data bits. Please note the delay specification from SCK to a valid SDO. SDO is always guaranteed to be valid by the next rising edge of SCK. The 16-bit output data stream is compatible with the 16-bit or 32-bit serial port of most processors. Loading on the SDO line must be minimized. SDO can directly drive most fast CMOS logic inputs directly. How- ever , the general purpose I/O pins on many programmable logic devices (FPGAs, CPLDs) and DSPs have excessive capacitance. In these cases, a 100Ω resistor in series with SDO can isolate the input capacitance of the receiv- ing device. If the receiving device has more than 10pF of input capacitance or is located far from the L TC2356- 12/L TC2356-14, an NC7SVU04P5X inverter can be used to provide more drive. APPLICATIONS INFORMATION NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 6. EXPOSED PAD DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD SHALL NOT EXCEED 0.254mm (.010") PER SIDE. 0.53 ±0.152 (.021 ±.006) 0.18 (.007) 0.254 (.010) 0° – 6° TYP DETAIL “A” DETAIL “A” GAUGE PLANE 5.23 (.206) MIN 3.20 – 3.45 (.126 – .136) 0.889 ±0.127 (.035 ±.005) RECOMMENDED SOLDER PAD LAYOUT 1.68 ±0.102 (.066 ±.004) 1.88 ±0.102 (.074 ±.004) 0.50 (.0197) BSC 0.305 ± 0.038 (.0120 ±.0015) TYP BOTTOM VIEW OF EXPOSED PAD OPTION 1.68 (.066) 1.88 (.074) 1 2 3 4 5 4.90 ±0.152 (.193 ±.006) 0.497 ±0.076 (.0196 ±.003) REF8 9 107 6 3.00 ±0.102 (.118 ±.004) (NOTE 3) 3.00 ±0.102 (.118 ±.004) (NOTE 4) MSOP (MSE) 0911 REV H SEATING PLANE 1.10 (.043) MAX 0.17 –/uni00A00.27 (.007 – .011) TYP 0.86 (.034) REF 0.50 (.0197) BSC 0.1016 ±0.0508 (.004 ±.002) DETAIL “B” DETAIL “B” CORNER TAIL IS PART OF THE LEADFRAME FEATURE. FOR REFERENCE ONL Y NO MEASUREMENT PURPOSE

0.05 REF

0.29 REF 10-Lead Plastic MSOP, Exposed Die Pad (Reference LTC DWG # 05-08-1664 Rev H) Please refer to http://www.linear .com/designtools/packaging/ for the most recent package drawings.

Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However , no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

REVISION HISTORY

REV DATE DESCRIPTION PAGE NUMBER A 01/10 Revise Values in Pin Configuration Section 2 B 06/12 Changed straight binary to 2’s complement 13

Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear .com  LINEAR TECHNOLOGY CORPORATION 2006 LT 0612 REV B • PRINTED IN USA PRE VCC 1k50/uni03A9 VCC NL17SZ74 CONVERT ENABLE NC7SVU04P5X MASTER CLOCK 0.1µF CONV LTC2356 CONTROL LOGIC (FPGA, CPLD, DSP, ETC.) D Q Q CONV SCK SDO 100/uni03A9 NC7SVU04P5X CLR

2356 TA03

PART NUMBER DESCRIPTION COMMENTS ADCs L TC1402 12-Bit, 2.2Msps Serial ADC 5V or ±5V Supply, 4.096V or ±2.048V Span L TC1403/L TC1403A 12-/14-Bit, 2.8Msps Serial ADC 3V , 14mW , Unipolar Inputs, MSOP Package L TC1403-1/L TC1403A-1 12-/14-Bit, 2.8Msps Serial ADC 3V , 14mW , Bipolar Inputs, MSOP Package L TC1405 12-Bit, 5Msps Parallel ADC 5V , Selectable Spans, 115mW L TC1407/L TC1407A 12-/14-Bit, 3Msps Simultaneous Sampling ADC 3V , 2-Channel Differential, Unipolar Inputs, 14mW , MSOP Package L TC1407-1/L TC1407A-1 12-/14-Bit, 3Msps Simultaneous Sampling ADC 3V , 2-Channel Differential, Bipolar Inputs, 14mW , MSOP Package L TC1411 14-Bit, 2.5Msps Parallel ADC 5V , Selectable Spans, 80dB SINAD L TC1412 12-Bit, 3Msps Parallel ADC ±5V Supply, ±2.5V Span, 72dB SINAD LCT1414 14-Bit, 2.2Msps Parallel ADC ±5V Supply, ±2.5V Span, 78dB SINAD L TC1420 12-Bit, 10Msps Parallel ADC 5V , Selectable Spans, 71dB SINAD L TC1604 16-Bit, 333ksps Parallel ADC ±5V Supply, ±2.5V Span, 90dB SINAD L TC1608 16-Bit, 500ksps Parallel ADC ±5V Supply, ±2.5V Span, 90dB SINAD L TC1609 16-Bit, 200ksps Serial ADC 5V , Configurable Bipolar/Unipolar Inputs L TC1864/L TC1865 16-Bit, 250ksps Serial ADCs 5V Supply, 1 and 2 Channel, 4.3mW , MSOP Package L TC2355-12/L TC2355-14 12-/14-Bit, 3.5Msps Serial ADC 3.3V 14mW , 0V to 2.5V Span, MSOP Package DACs L TC1666/L TC1667/L TC1668 12-/14-/16-Bit, 50Msps DACs 87dB SFDR, 20ns Settling Time L TC1592 16-Bit, Serial SoftSpan™ I OUT DAC ±1LSB INL/DNL, Software Selectable Spans References L T1790-2.5 Micropower Series Reference in SOT-23 0.05% Initial Accuracy, 10ppm Drift L T1461-2.5 Precision Voltage Reference 0.04% Initial Accuracy, 3ppm Drift L T1460-2.5 Micropower Series Voltage Reference 0.075% Initial Accuracy, 10ppm Drift Low-Jitter Clock Timing with RF Sine Generator Using Clock Squaring/Level Shifting Circuit and Re-Timing Flip-Flop RELATED PARTS TYPICAL APPLICATION