LCS700

LCS700 POWERINT

Document overview

• Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 26

Technical content

Features

• LLC half-bridge power stage incorporating controller, high and low-side gate drives, and high-voltage power MOSFETs
• Eliminates up to 30 external components
• High maximum operating frequency of 1 MHz
• Nominal steady-state operation up to 500 kHz
• Dramatically reduces magnetics size and allows use of SMD ceramic output capacitors
• Precise duty symmetry balances output rectifier current, improving efficiency
• 50% ±0.3% typical at 300 kHz
• Comprehensive fault handling and current limiting
• Programmable brown-in/out thresholds and hysteresis
• Undervoltage (UV) and overvoltage (OV) protection
• Programmable over-current protection (OCP)
• Short-circuit protection (SCP)
• Over-temperature protection (OTP)
• Programmable dead-time for optimized design
• Programmable burst mode maintains regulation at no-load and improves light load efficiency
• Programmable soft-start time and delay before soft-start
• Accurate programmable minimum and maximum frequency limits
• Single package designed for high-power and high-frequency
• Reduces assembly cost and reduces PCB layout loop areas
• Simple single clip attachment to heat sink
• Exposed thermal pad connected to ground potential – no insulators required between package and heat sink
• Staggered pin arrangement for simple PC board routing and high-voltage creepage requirements
• Paired with HiperPFS PFC product gives complete, high efficiency, low part count PSU solutions

Applications

• High-efficiency power supplies (80 PLUS Silver, Gold and Platinum)
• LCD TV power supplies
• LED street and area lighting
• Printer power supplies
• Audio amplifier

Figure 1. Typical Application Circuit – LCD TV and PC Main Power Supply.

Description

The HiperLCS is an integrated LLC power stage incorporating a multi-function controller, high-side and low-side gate drivers, plus two power MOSFETs in a half-bridge configuration. Figure 1 shows a simplified schematic of a HiperLCS based power stage where the LLC resonant inductor is integrated into the transformer. The variable frequency controller provides high efficiency by switching the power MOSFETs at zero voltage (ZVS), eliminating switching losses. Output Power Table Product Maximum Practical Power1 LCS700HG 110 W LCS701HG 170 W LCS702HG 220 W LCS703HG 275 W LCS705HG 350 W LCS708HG 440 W Table 1. Output Power Table.

1. Maximum practical power is the power the part can deliver when properly

mounted to a heat sink and a maximum heat sink temperature of 90 °C.

Figure 2. Block Diagram.

3 LLC CLOCK

7 CONSECUTIVE

helps provide filtering and improves noise immunity. the B- bus and not to the GROUND pin. connected to the SOURCE pins to provide a star connection. nor to the B- bus, in the PCB layout . pin down to ground will implement a remote-off function. start-up frequency, soft-start time, and delay before start-up. reaching the pin, provided the reverse current is limited to <5 mA. Figure 3. Pin Numbering and Designation. the PFC bulk capacitor or input high-voltage DC return. lower MOSFET turns on or its body diode conducts. the B+ from the PFC bulk capacitor or input high-voltage DC bus.

Figure 4. 150 W Laser-Jet Printer Power Supply.

1 FL1

25 V C5

250 VAC

Rev. B 062011 LCS700-708 www.powerint.com HiperLCS Basic Operation The HiperLCS is designed for half-bridge LLC converters, which are high-efficiency resonant, variable frequency converters. The HiperLCS is an LLC controller chip with built-in drivers and half-bridge MOSFETs. LLC converters require a fixed dead-time between switching half-cycles. The dead-time, maximum frequency at start-up, and burst threshold frequencies, are programmed with a resistor divider on the DT/BF pin from the VREF to the GROUND pins. The FEEDBACK (FB) pin is the frequency control input for the feedback loop. Frequency is proportional to FEEDBACK pin current. The FEEDBACK pin V-I characteristic resembles a diode to ground. Burst Mode If the frequency commanded by the FEEDBACK pin current exceeds the upper burst threshold frequency (f STOP, ISTOP) programmed by the resistor divider on the DT/BF pin, the output MOSFETs will turn off, and will resume switching when the current drops below the value which corresponds to the frequency equal to the lower burst threshold frequency (f START, ISTART). As a first approximation, burst mode control resembles a hysteretic controller where the frequency ramps from f START to fSTOP, stops and repeats. An external component network connected from the VREF pin to the FEEDBACK pin determines the minimum and start-up FEEDBACK pin currents, and thus the minimum and start-up switching frequencies. A soft-start capacitor in this network determines soft-start timing. The VREF pin provides a nominal 3.4 V as a reference for this FEEDBACK pin external network and other functions. Maximum current from this pin must be ≤4 mA. The Dead-Time/Burst Frequency (DT/BF) pin also has a diode-to- ground V-I characteristic. A resistor divider from VREF to GROUND programs dead-time, maximum start-up switching frequency (fMAX), and the burst threshold frequencies. The current flowing from the resistor divider to the DT/BF pin determines fMAX. The ratio of the resistors selects from 3 discrete, burst threshold frequency ratios, which are fixed fractions of fMAX. The OV/UV pin senses the high-voltage B+ input through a resistor divider. It implements brown-in, brown-out, and OV with hysteresis. The ratios of these voltages are fixed; the user must select the resistor divider ratio such that the brown-in voltage is below the minimum nominal bulk (input) voltage regulation set-point to ensure start-up, and the OV (lower) restart voltage is above the maximum nominal bulk voltage set-point, to ensure that the LCS will restart after a voltage swell event that triggers the OV upper threshold. If different brown-in to brown-out to OV ratios are required, external circuitry needs to be added to the resistor divider. VCC Pin UVLO The VCC pin has an internal UVLO function with hysteresis. The HiperLCS will not start until the voltage exceeds the VCC start threshold VUVLO(+). HiperLCS will turn off when the VCC drops to the VCC Shutdown Threshold VUVLO(-). VCCH Pin UVLO The VCCH pin is the supply pin for the high-side driver. It also has a UVLO function similar to the VCC pin, with a threshold lower than the VCC pin. This is to allow for a VCCH voltage that is slightly lower than VCC because the VCCH pin is fed by a bootstrap diode and series current-limiting resistor from the VCC supply. Start-Up and Auto-Restart Before start-up the FEEDBACK pin is internally pulled up to the VREF pin to discharge the soft-start capacitor and to keep the output MOSFETs off. When start-up commences the internal pull-up transistor turns off, the soft-start capacitor charges, the outputs begin switching at f MAX, the FEEDBACK pin current diminishes, the switching frequency drops, and the PSU output rises. When the output reaches the voltage set-point, the optocoupler will conduct, closing the loop and regulating the output. Whenever the VCC pin is powered up, the DT/BF pin goes into high impedance mode for 500 ms in order to sense the voltage divider ratio and select the Burst Threshold. This setting is stored until the next VCC recycle. The DT/BF pin then goes into normal mode, resembling a diode to ground, and the sensed current continuously sets the fMAX frequency. The burst threshold frequencies are fixed fractions of f MAX. The internal oscillator runs the internal counters at fMAX whenever the FEEDBACK pin internal pull-up is on. When a fault is detected on the IS, OV/UV, or VCC pin (UVLO), the internal FEEDBACK pin pull-up transistor turns on for 131,072 clock cycles, to discharge the soft-start capacitor completely, then a restart is attempted. The first power-up after a VCC recycle only waits 1024 cycles, including the condition where the OV/UV pin rises above the brown-in voltage for the first time, after VCC is powered up. Remote-Off Remote-off can be invoked by pulling down the OV/UV pin to ground, or by pulling up the IS pin to >0.9 V. Both will invoke a 131,072 cycle restart cycle. VCC can also be pulled down to shut the device off, but when it is pulled up, the FEEDBACK pin is pulled up to the VREF pin to discharge the soft-start capacitor for only 1024 fMAX clock cycles. If this scheme is used, the designer must ensure that the time the VCC is pulled down, plus 1024 cycles, is sufficient to discharge the soft-start capacitor, or if not, that the resulting lower starting frequency is high enough so as not to cause excessive primary currents that may cause the over-current protection to trip. Current Sense The IS pin senses the primary current. It resembles a reverse diode to the GROUND pin. It is tolerant of negative voltages provided the negative current is limited to <5 mA. Therefore it must be connected to the current sense resistor (or primary capacitive voltage divider + sense resistor) via a series current limiting resistor of >220 W. Thus it can accept an AC waveform and does not need a rectifier or peak detector circuit. If the IS pin senses a nominal positive peak voltage of 0.5 V for 7 consecutive cycles, an auto-restart will be invoked. The IS pin also has a second, higher threshold at nominally 0.9 V, which will invoke an auto-restart with a single pulse. The minimum

increase the dv/dt (capacitive) coupling to low-voltage circuits. resistance must be considered in the thermal design. output need to be intertwined. Figure 9. Placement of B+ and B- High-Voltage Bypass Capacitors.

Rev. B 062011 LCS700-708 www.powerint.com Key Design Details The LLC converter is a variable frequency resonant converter. As input voltage decreases, the frequency must decrease in order to maintain output regulation. To a lesser extent, as load reduces the frequency must increase. When the converter is operating at the series resonant frequency, the frequency changes very little with load. The minimum operating frequency required occurs at brownout (minimum input voltage), at full load. Operating Frequency Selection For lowest cost, and smallest transformer size with the least amount of copper, the recommended nominal operating frequency is ~250 kHz. This allows the use of low-cost ceramic output capacitors in place of electrolytic capacitors, especially at higher output voltages (≥12 V). If the core and bobbin used exhibits too much leakage inductance for 250 kHz, operation at 180 kHz also results in excellent performance. For optimal efficiency at 250 kHz, AWG #44 (0.05 mm) Litz is recommended for the primary, and AWG #42 (0.07 mm) for the secondary winding. Thicker gauge lower cost Litz can be used at the expense of increased copper loss and lower efficiency. Litz gauge (AWG #38 or 0.1 mm) is optimal for very low frequencies (60-70 kHz), requires much larger transformers and greater lengths of Litz wire. For nominal operating frequencies even as low as 130 kHz, the use of PC44 or equivalent core material is recommended for reduced losses. For a given transformer design, shifting the frequency up (by substituting a smaller resonant capacitor), will reduce core loss (due to reduced AC flux density B AC) and increase copper loss. Core loss is a stronger function of flux density than of frequency. The increased frequency increases copper loss due to eddy current losses. Nominal operating frequencies >300 kHz start to lose significant efficiency due to increased eddy current losses in the copper, and due to the fact that a more significant percentage of time is spent on the primary slew time (ZVS transition time) which erodes the percentage of time that power is transferred to the secondary. Resonant Tank and Transformer Design Please refer to the Application Note AN-55 for guidance on using the PIXls HiperLCS spreadsheet which assists in the entire design process. Primary Inductance The optimal powertrain design for the HiperLCS uses a primary inductance that results in minimal loss of ZVS at any steady- state condition. Some loss of ZVS during non-steady-state conditions is acceptable. Reducing primary inductance produces higher magnetizing current which increases the range of ZVS operation, but the increased magnetizing current increases losses and reduces efficiency. The calculation of the primary inductance to be used for a first-pass design is based on device size, rated load, minimum input voltage, and desired operating frequency. It is provided in the PIXls spreadsheet. LPRI is the primary inductance of an integrated transformer (high leakage inductance), or in the case of the use of an external series inductance, the sum of this inductance and the transformer primary inductance. Leakage Inductance The parameter KRATIO is a function of leakage inductance: K L L 1RATIO RES PRI The recommended K RATIO is from 2.5 - 7. This determines the acceptable range of leakage inductance. LRES is the leakage inductance in an integrated transformer; if a separate series inductor is used, it is the sum of this inductance and the leakage inductance of the transformer. A low KRATIO (high leakage inductance) may not be capable of regulation at the minimum input voltage, and may show increased transformer copper losses due to the leakage flux. A high KRATIO (low leakage inductance) will have high peak and RMS currents at low-line, and require a lower primary inductance to achieve ZVS operation over a suitably wide range, which increases the resonant circulating current, reducing efficiency. The core and bobbin designs available to the designer may limit the adjustability of leakage inductance. Fortunately, excellent performance can be achieved over a relatively wide range of leakage inductance values. The KRATIO directly affects the frequency range that the LLC needs to operate in order to maintain regulation over the input voltage range. Increasing KRATIO increases this frequency range, lowering fMIN. A low fMIN is only a potential problem for low frequency designs which typically run at higher nominal B AC. This may allow the core to reach saturation when operating at f MIN. Operating at fMIN occurs when the input voltage is at a minimal (input brown-out). For a design with a separate resonant inductor, running the inductance on the low side of the range (K RATIO = 7), minimizes the size and cost of the inductor. Adjusting Leakage Inductance Sectioned bobbins (separated primary and secondary) are commonly used for LLC converters. Increasing or decreasing both primary and secondary turns (while maintaining turns ratio) will change the leakage inductance proportionally to the square of primary turns. If the leakage inductance is too high, one possible solution is to use a 3-section bobbin, where the secondary is in the middle section, and the primary winding is split into 2 halves connected in series. Lastly, if the leakage inductance is too low an external inductor may be added.

Rev. B 062011 LCS700-708 www.powerint.com Resonant Frequency The series resonant frequency is a function of L RES and CRES, the resonant capacitor. For any given value of L RES, the value of CRES can be adjusted for the desired series resonant frequency fRES. For best efficiency the resonant frequency is set close to the target operating frequency at nominal input voltage. Operating Frequency and Frequency Ratio The operating to resonant frequency ratio f RATIO is defined as: f f f RATIO RES SW fRATIO = 1 signifies the converter is operating at the series resonant frequency. The main determinant of f RATIO is the transformer turns ratio. Increasing primary turns lowers f RATIO for a given input and output voltage. The recommended f RATIO at nominal input voltage is 0.92 – 0.97. Operating at resonance often yields the highest efficiency for the resonant powertrain if output rectifier selection is ignored. However, operating slightly below resonance (which puts the rectifiers in discontinuous conduction mode), allows the use of lower voltage diodes or synchronous MOSFETs, which have lower losses, increasing overall efficiency. This is because at high-line, when the converter needs to operate above resonance, the rectifiers operate less deeply in continuous mode, reducing the magnitude of their current commutation, reducing their stray inductance voltage spikes. (The stray inductance is comprised of the leakage inductance between secondary phases and the stray inductance in the connections to the rectifiers and output capacitors). Conversely, operating at a very low f RATIO (<0.8) results in higher RMS and peak currents. In some cases, this may result in an optimal design because it allows the use of lower voltage rating, lower VF rectifier as they do not operate in continuous conduction mode even at high-line, results in no voltage spikes enabling a lower voltage rating. An LLC half-bridge converter will operate at resonance when this equation is true: OUTV V IN EQ= Where nEQ is the transformer equivalent circuit turns ratio. Note that the nEQ of an integrated transformer is lower than its physical turns ratio NPRI / NSEC. The secondary turns is that of each half-secondary. VOUT in the above equation is equal to output voltage + diode drop. The divisor “2” is due to the half-bridge configuration – each half-cycle conducts half the input voltage to each secondary half. Note that if the resonant capacitor or inductance value is changed, both switching frequency and resonant frequency change, but fRATIO changes little. For a given design, the input voltage at which the LLC operates at resonance is VINPUT(RESONANCE) . Below this voltage, the LLC operates at a lower frequency (below resonance). Thus for the recommended fRATIO ≈ 0.95 at nominal input voltage, VINPUT(RESONANCE) will be slightly higher than the nominal voltage. For a design with a variable nominal input voltage (e.g. no PFC pre-regulator), it is recommended that the initial turns ratio be set so that VINPUT(RESONANCE) is at about halfway between maximum and minimum input voltage. For a design with a variable output voltage (e.g. constant current regulated output), it is recommended that the initial turns ratio be set to operate the LLC at resonance at a point halfway between minimum and maximum output voltages. Dead-Time Selection The vast majority of designs using HiperLCS, regardless of power and operating frequency, work very well with a dead-time of between 290 and 360 ns. Designs that require a low V BROWNOUT tend to require shorter dead-times. The dead-time setting is a compromise between low-line / full load (low frequency), and minimum-load / high-line (high- frequency) conditions. Low-line / full load operation has short optimal dead-times, while minimum load / high-line has long optimal dead-times. A dead-time setting that is longer than optimal for low-line / full load operation, exhibiting partial loss of ZVS, is acceptable if the condition does not occur during steady-state operation – i.e. appears only during transient conditions, such as hold-up time. Operation with loss of ZVS during steady-state operation leads to high internal power dissipation and should be avoided. A dead-time setting that is shorter than optimal for high-line / minimum-load operation, will tend to cause the feedback sign to invert and force the HiperLCS to enter burst mode. This is acceptable if the resulting burst mode operation is acceptable (i.e. repetition rate does not produce audible noise and if the large signal transients, wherein the HiperLCS enters and exits burst mode, is acceptable). Note that with a PFC pre-regulated front end, a load dump (e.g. 100% to 1% load step) will exhibit a transient input voltage condition only temporarily (e.g. Input voltage to LLC stage will increase from 380 V to 410 V and relatively slowly return to 380 V). Note also that the Burst Threshold frequency setting is another variable available to the designer to tune burst mode. OV/UV Pin The HiperLCS OV/UV pin which monitors the input (B+) voltage, has a brown-out shutdown threshold (V SD(L)) of nominally 79% of the brown-in (turn-on) threshold (VSD(H)), which in turn, is nominally 2.4 V. The overvoltage (OV) lockout shutdown threshold (V OV(H)) is nominally 131% of the brown-in start-up threshold, and the OV restart point (VOV(L)) at nominally 126%. The ratios of these thresholds are fixed and selected for maximum utility in a design with a PFC pre-regulator front-end with a fixed output voltage set-point. The resistor divider ratio has to be selected so that brown-in point is always below the PFC output set-point, and so that the OV restart (lower) threshold, is always above it, including component tolerances. During hold-up time, the voltage will drop from the nominal value, down to the brown-out threshold, whereby the HiperLCS will stop switching.

gives adequate margin against the device max VDS rating of 530 V. maximizes hold-up time for a given bulk capacitor value. senses the pin voltage, before the HiperLCS starts switching. For proper selection, set the ratio of RBURST to RFMAX as per Table 3. Table 3. Burst Threshold Selection Table. The Burst Threshold setting is stored until VCC is powered down. determines the dead-time and the maximum frequency f MAX. same characteristic), is show in Figure 16. as set by the resistor divider ratio on the DT/BF pin. Table 4. Burst Start and Stop Frequencies as Ratios of fMAX. Figure 14. OV/UV Pin Voltage Thresholds, at Minimum and Maximum Divider Ratios, for 385 V Nominal Input Voltage.

495 V VOVH

376 V VSDH

298 V VSDL

475 V VOVL

436 V VOVH

331 V VSDH

262 V VSDL

418 V VOVL

Figure 15. DT/BF Pin Divider.

capacitor, in preparation for soft-start. state remains for 131,072 clock cycles. restart is invoked, with a restart delay of 164 ms. DT/BF pin current at start-up, an additional delay is introduced. commence when the FEEDBACK pin voltage drops below 2.0 V. Thus the designer can add an additional start-up delay if desired. controlling the switching frequency thus the output voltage. over-current protection to trip. and thus pin noise rejection, for a given RC pole frequency.

0.5 V. It will also invoke a restart if a single pulse exceeds 0.9 V.

pulses must be higher than the threshold voltage for >30 ns. Figure 22. Typical Start-up Waveform. Observe Initial Current Spike ‘A’ to Ensure Current at VBROWNOUT at Full Load.

Figure 26. Zoom in of Last Few Switching Cycles of Burst Pulse Train of Figure 24. Primary Inductance Ringing with the MOSFET Capacitance.

Rev. B 062011 LCS700-708 www.powerint.com Parameter Symbol Conditions SOURCE = 0 V; TJ = 0 to 100 °C VCC = 12 V, VCCH = 12 V (Unless Otherwise Specified) Min Typ Max Units Half-Bridge OFF-State Current IDSS Measured from D to HB or from HB to S TJ = 100 °C, VCC =

12 V, VCCH = 12 V,

VD = 424 V LCS700 60 mA LCS701 60 LCS702 65 LCS703 80 LCS705 120 LCS708 200 ON-State Resistance RDS(ON) Measured from D to HB or from HB to S VCC = 12 V, VCCH =

12 V, TJ = 25 °C

LCS700, I = 0.8 A 1.53 1.82 W LCS701, I = 1.2 A 1.00 1.24 LCS702, I = 1.6 A 0.74 0.92 LSC703, I = 2.0 A 0.60 0.73 LCS705, I = 3.0 A 0.40 0.49 LCS708, I = 4.8 A 0.26 0.31 Thermal Resistance Junction to Case Thermal Resistance (1,3): Junction to heat sink Thermal Resistance (1,2): Hottest Junction to OT Sensor Thermal Offset (1,2,4): Notes: 1. Both power switches each dissipating half the total power. 2. Mounted to an aluminum heat sink with uniform coverage of Thermalloy thermal paste. Mounting clip with normal force >30 N applied to the center of the package. 3. Junction to case thermal resistance is based on hottest junction, case temperature measured at center of package back surface. 4. Temperature difference between hottest junction and over- temperature sensor. 5. Thermal resistance values are preliminary and subject to change. Absolute Maximum Ratings Notes: 1. Voltage referenced to S. 2. Voltage referenced to HB. 3. Voltage referenced to G. 4. 1/16 inch from case for 5 seconds. 5. One-cycle peak current can exceed repetitive maximum current for t < 460 ns if TJ < 100 °C and drain voltage ≤ 400 VDC.

Rev. B 062011 LCS700-708 www.powerint.com Parameter Symbol Conditions SOURCE = 0 V; TJ = 0 to 100 °C VCC = 12 V, VCCH = 12 V (Unless Otherwise Specified) Min Typ Max Units Half-Bridge (cont.) ON-State Resistance RDS(ON) Measured from D to HB or from HB to S VCC = 12 V, VCCH =

12 V, TJ = 100 °C

LCS700, I = 0.8 A 2.15 2.63 W LCS701, I = 1.2 A 1.42 1.78 LCS702, I = 1.6 A 1.05 1.33 LCS703, I = 2.0 A 0.85 1.06 LCS705, I = 3.0 A 0.58 0.71 LCS708, I = 4.8 A 0.36 0.45 Half-Bridge Capacitance CHB Effective half-bridge capacitance. VHB swinging from

0 V to 400 V or

400 V to 0 V,

TJ = 125 °C LCS700, I = 0.8 A 1.15 V LCS701, I = 1.2 A 1.15 LCS702, I = 1.6 A 1.15 LSC703, I = 2.0 A 1.15 LCS705, I = 3.0 A 1.15 LCS708, I = 4.8 A 1.15 Power Supply VCC Supply Voltage Range VCC See Note C 11.4 12 15 V VCCH Supply Voltage Range VCCH See Note C 11.4 12 15 V Start-Up Current ICC(OFF) Undervoltage lockout state: VCC = 8 V 0.85 1 mA Inhibit Current ICC(INHIBIT) VCC = 12 V, OV/UV < VSD(L) 1.35 1.7 mA VCC Operating Current ICC(ON) Typical at VCC = 12 V Maximum at VCC =

15 V Measured at

300 kHz, HB Open and VD = 15 V LCS700 4.0 5.2 mA LCS701 4.4 5.8 LCS702 4.9 6.5 LCS703 5.4 7.1 LCS705 6.6 8.8 LCS708 8.8 11.8 VCCH Operating Current ICCH(ON) Typical at VCCH = 12 V Maximum at VCCH = 300 kHz, HB Open and VD = 15 V LCS700 3.4 4.6 mA LCS701 3.9 5.2 LCS702 4.3 5.8 LSC703 4.7 6.4 LCS705 5.8 7.9 LCS708 7.8 10.7 VCC Supply Undervoltage Lockout VCC Start Threshold VUVLO(+) Device exits UVLO state when VCC exceeds UVLO+ 10 10.7 11.4 V VCC Shutdown Threshold VUVLO(-) Device enters UVLO state when VCC falls below UVLO+ 9.1 9.8 10.5 V VCC Start-Up/Shut- down Hysteresis VUVLO(HYST) 0.70 0.90 1.20 V

Rev. B 062011 LCS700-708 www.powerint.com Parameter Symbol Conditions SOURCE = 0 V; TJ = 0 to 100 °C VCC = 12 V, VCCH = 12 V (Unless Otherwise Specified) Min Typ Max Units VCCH Supply Undervoltage Lockout VCCH Start Threshold VUVLO(H+) Driver exits UVLO state when VCCH exceeds UVLOH+ 8.2 8.5 8.9 V VCCH Shutdown Threshold VUVLO(H-) Driver enters UVLO state when VCCH falls below UVLOH- 7.4 7.5 8.1 V VCCH Start-Up/ Shutdown Hysteresis VUVLO(H)HYST 0.65 0.75 1.00 V High-Voltage Supply Undervoltage/Overvoltage Enable OV/UV Overvoltage Shutdown Threshold VOV(H) Overvoltage assertion threshold 129 131 133 % of VSD(H) OV/UV Overvoltage Recovery Threshold VOV(L) Overvoltage de-assertion threshold 124 126 128 % of VSD(H) OV/UV Undervoltage Start Threshold VSD(H) Undervoltage de-assertion threshold 2.35 2.40 2.45 V OV/UV Undervoltage Shutdown Threshold VSD(L) Undervoltage assertion threshold 77 79 81 % of VSD(H) OV/UV Pin Input Resistance RIN(OVUV) OV/UV pin resistance to G 3.0 5.0 6.6 MW Reference Reference Voltage VREF IREF = 4 mA 3.25 3.40 3.50 V Current Source Capability of VREF Pin IREF 4 mA VREF Capacitance CREF Required external coupling on VREF pin 1 mF LLC Oscillator Frequency Range FRANGE 25 1000 kHz Accuracy of Minimum Frequency Limit FMIN(ACC) RFB = 37.9 kW to VREF , 180 kHz -5.0 5.0 FMIN(ACL) RFB = 154 kW to VREF , 50 kHz -7.5 7.5 Accuracy of Maximum Frequency Limit FMAX(ACC) IFB = IDT/BF, RFMAX = 12.5 kW, FMAX = 510 kHz -7.5 7.5 % Duty Balance DLLC Duty symmetry of the half-bridge wave- form, CFB = 4.7 nF, CDT/BF = 4.7 nF, 250 kHz. Use recommended layout 49 51 % Dead-TimeB tD RFMAX = 7 kW, RBURST = 39.6 kW 330 ns DT/BF Control Current Range IDT/BF 30 430 mA IFB Threshold to Stop LLC Switching ISTOP1 Threshold applies after exiting soft-start mode for burst setting BT1 49.8 % of IDT/BFISTOP2 Threshold applies after exiting soft-start mode for burst setting BT2 43.9 ISTOP3 Threshold applies after exiting soft-start mode for burst setting BT3 37.1

Rev. B 062011 LCS700-708 www.powerint.com Parameter Symbol Conditions SOURCE = 0 V; TJ = 0 to 100 °C VCC = 12 V, VCCH = 12 V (Unless Otherwise Specified) Min Typ Max Units LLC Oscillator (cont.) IFB Threshold Hysteresis IBURST(HYST) ISTART is IBURST(HYST) below ISTOP 5 6.25 8 % of IDT/BF DT/BF Voltage to Program Burst Setting VBT1 Required VDT/BF at start-up to enable burst setting BT1 93.5 95 96.3 % of VREFVBT2 Required VDT/BF at start-up to enable burst setting BT2 88.5 90 91.3 VBT3 Required VDT/BF at start-up to enable burst setting BT3 83.5 85 86.3 Time Constant for the Combination of RFMAX, RBURST and the Decoup- ling Cap on DT/BF RCDT/BF This time constant must be less than the specified maximum to ensure correct setting of burst mode. 100 ms FB Current Maximum IFB Determines the maximum control frequency that can be set by IFB. 100 %IDT/BF FB Control Current Range IFB IFB is limited by the current into DT/BF 15 430 mA FB Virtual Voltage VFB FB input appears as RIN(FB) in series with VFB. 30 mA < IFB < IDT/BF 0.65 V FB Input Resistance RIN(FB) FB input appears as RIN(FB) in series with VFB. 30 mA < IFB < IDT/BF 2.5 kW FB Input Resistance During Soft-Start RFB(SS) FB input appears as RFB(SS) in series with VREF during the soft-start delay interval or when OV/UV < VSD or OV/UV > VOV 750 W Over-Current Protection Fast Over-Current Fault Voltage Threshold4 VIS(F) 0.855 0.905 0.955 V Slow Over-Current Fault Voltage Threshold VIS(S) 7 LLC clock cycle debounce 0.455 0.505 0.555 V Over-Current Fault Pulse Width tIS Minimum time VIS exceeds VIS(F)/VIS(S) per cycle to trigger fault protection 30 ns Over-Temperature Protection Over-Temperature Shutdown ThresholdA TOT 140 °C NOTES: A. Guaranteed by design. B. Typical apparent dead-time at the HB pin under resonant ZVS conditions. C. VCC/VCCH operating range to achieve power capabilities specified in data sheet power table.

Rev. B 062011 LCS700-708 www.powerint.com PI-5639-031011 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M-1994. 2. Dimensions noted are determined at the outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs, and interlead flash, but including any mismatch between the top and bottom of the plastic body. Maximum mold protrusion is 0.007 [0.18] per side. 3. Dimensions noted are inclusive of plating thickness. 4. Does not include interlead flash or protrusions. 5. Controlling dimensions in inches (mm). 0.628 (15.95) Ref. 0.019 (0.48) Ref. 0.060 (1.52) Ref. 10° Ref. All Around 0.021 (0.53) 0.019 (0.48) 0.048 (1.22) 0.046 (1.17) 0.027 (0.70) 0.023 (0.58) 0.038 (0.97) 0.076 (1.93) 0.118 (3.00)

0.029 Dia Hole

0.062 Dia Pad

0.020 (0.50) 0.016 (0.41) Ref. Detail A 0.118 (3.00) 0.140 (3.56) 0.120 (3.05) 0.081 (2.06) 0.077 (1.96) 13×0.016 (0.41) 0.011 (0.28) 0.020 M 0.51 M C 0.290 (7.37) Ref. 0.047 (1.19) C 1 3 4 5 6 7 8 9 10 11 13 14 16 0.653 (16.59) 0.647 (16.43) 0.325 (8.25) 0.320 (8.13) A B Pin 1 I.D. 0.214 (5.44) Ref. 0.076 (1.93) 0.012 (0.30) Ref. 0.210 (5.33) Ref. 0.207 (5.26) 0.187 (4.75) 13×0.024 (0.61) 0.019 (0.48) 0.010 M 0.25 M C A B 0.519 (13.18) Ref. FRONT VIEW SIDE VIEW BACK VIEW Detail A (Scale = 9×) PCB FOOT PRINT END VIEW eSIP-16C (H Package) Dimensions in inches, (mm). All dimensions are for reference.

Rev. B 062011 LCS700-708 www.powerint.com Part Ordering Information

• Hiper Product Family
• LCS Series Number
• Package Identifier H Plastic eSIP-16C
• Pin Finish G Halogen Free and RoHS Compliant
• Tape & Reel and Other Options Blank Standard ConfigurationsLCS 700 H G - TL

For the latest updates, visit our website: www.powerint.com Power Integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. Power Integrations does not assume any liability arising from the use of any device or circuit described herein. POWER INTEGRATIONS MAKES NO WARRANTY HEREIN AND SPECIFICALLY DISCLAIMS ALL WARRANTIES INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF THIRD PARTY RIGHTS. Patent Information The products and applications illustrated herein (including transformer construction and circuits external to the products) may be covered complete list of Power Integrations patents may be found at www.powerint.com. Power Integrations grants its customers a license under certain patent rights as set forth at http://www.powerint.com/ip.htm. Life Support Policy POWER INTEGRATIONS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF POWER INTEGRATIONS. As used herein: 1. A Life support device or system is one which, (i) is intended for surgical implant into the body, or (ii) supports or sustains life, and (iii) whose failure to perform, when properly used in accordance with instructions for use, can be reasonably expected to result in significant injury or death to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. The PI logo, TOPSwitch, TinySwitch, LinkSwitch, DPA-Switch, PeakSwitch, CAPZero, SENZero, LinkZero, HiperPFS, HiperTFS, HiperLCS, Qspeed, EcoSmart, Clampless, E-Shield, Filterfuse, StakFET, PI Expert and PI FACTS are trademarks of Power Integrations, Inc. Other trademarks are property of their respective companies. ©2011, Power Integrations, Inc. Power Integrations Worldwide Sales Support Locations World Headquarters

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