LC7869E Datasheet | DigiCamel IC Datasheet

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LC7868E SANYO

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[Ordering number : EN4520 CMOS LSI [nose] LC7868E, 7869E SANKYO Digital Signal Processor for Compact Disc Players Overview + The LC7868/69 sets the C2 flags by referencing the C1 The LC7868E and the LC7869E are CMOS LSIs for signal £1288 and the C2 check result, and uses the C2 flags for Processing and servo control in compact disk players, laser erin a four interplanen athe oom force te disk players, and CD-V and CD-I products. Only the digital . . . filtering blocks differ between the LC7868E and the | {a0 2er0 when the C? lags are ap amesine row. LC7869E. These products perform signal processing such . i * as demodulation of the EFM signal from the optical pickup, ane the apnoea eee onané Seianat non ine de-interleaving, error detection and correction, and digital micr PP! 8-bit serial input), filtering that can contribute to end product cost reduction. . Festus onehip digital ont. Put). Furthermore, these products also process commands from . . - + 5 the system microprocessor directed at the servo system. + Can Perform the desired track counting. High-speed These products also support direct interface with the Sanyo . Uses sere cross ravting 1.078815 and LC78816 serial input D/A converters. + Oversampling and digital filtering provide a D/A Functions converter signal with improved output data continuity + HF signals that are input are sliced at an accurate level, . STROBE ODP. ree (8fsDF). converted to EFM signals, and undergo phase- . Bullsindigintdecmpiass comparison with VCO for PLL playback at an average . te det ora 318 Mz. Play e . peatures on-chip digital level meter and peak meter + Through external connection of a 16.9344 MHz crystal . Sunpone bit I functi oscillator, all required timing signals can be generated ‘upports bilingual function. on-chip, including the standard clock. Features + Frame phase difference signals made from the playback conpas and space-saving 64-pin QFP package clock and the ref lock can control the speed of ° “ 7 the dise moter relerence clock can © specdon Silicon-gate CMOS design (low power dissipation) * Performs detection, protection, and interleaving of * Single 5 V power supply (Suitable for portable sets) frame synchronization signals, ensuring stable data ° DEMO pin for improved operability in adjustment reading. Package Dimensions +» Demodulates EFM signals and performs conversion to . ig 8-bit symbol data. unit: mm + Separates subcodes from EFM demodulation signals for 3159-QFP64E Output to an external microprocessor. + After CRC checking, Q subcode signals are output to 1 the microprocessor by the serial I/O interface (LSB-first , toa a2, o. 0. o.8 ho output selectable). ; He a + On-chip RAM performs buffering for EFM |} L seURAA BADR ARARED Fe demodulation signals, as well as absorbing up to +4 | = frames of jitter due to fluctuations in the speed of disc = = rotation. 9 = = + Performs unscrambling and deinterleaving for = = rearranging the EFM demodulation signals into the =| = specified sequence. oe TUNOUUUUUTTN OUD” + Performs detection and correction of error signals, as 0.35 27 a well as error flag processing (double C1 and double C2 " error correction system). SANYO Electric Co., Ltd. Semiconductor Business Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ucno, Taito-ku, TOKYO, 110 JAPAN D2593JN B8-0298, 0299 No. 4520-1/22

LC7868E, 7869E Equivalent Circuit Block names in parentheses are for the LC7869E. wwaye i ff 8 2 2 & BERBER 8 8 Gob e228 ¢ weeee 8 2 TT. LL icrasse, 7a60e| | ' RAM generator ' [EFM demodulator I ion and teers Fsea * Se erpolation a ursy | (bitingual function) [] Roxour cuvs O Coane 1 and C2 error H cwv-O eter | detection and correction | vO Flag processing , sasy.srsv [}— redundancy check | wno.saouT [}—(Microprocessor il Level meter and Digital out CJ pour mio | — Tak 1) | 7 com corn conver re Awe Q Crystal oscillator and output interface 1) DFO! O |Servocontrolier timing generator deemphasis pewo F} ] (oF iN Lp dbdddo be -DOOO-t+- (1}+—--0000000 J BBEag 2 F ezae ¢ 5 25 8 RES eX XG Siaa 3s Gea ¢ & ES g Eee eX 4a olla 33 Fz ae § © § g 6 580 82g 8 eogge 9 o gee 3558 s eS zZ e 3 @ 8 e PoE ~ a = 5 3 2 6 3 » oe Ey u sores Pin Assignment a@ cE “5 ge x5 xe ox xr ory 38 > z 5525 Se Sasukb Puan zZ 8258 Besrrashaesterzgede aezrunsssesSha5eR S (40 47 46 45 44 43 42 44 20 39 38 37 36.35 34 33 | roxer4s 32 Le reste isysciio waa e750 St se ncLK (TEST7) auc ofS? 30-2 prorr saour e [52 38 re EMPH Gorn 0 88 BB re tests ack o—54 277 DEMO RES. elss Lo7ees 27 uP- ‘in names in parentheses ots? 24 LASER oT are for the LC7869E Tyee seme Se eS peTest3 ane pe cere THUD cont o> 0 aie Tot Tests of 64 20Te torr Teo 62 18 ersea xine f68 10 Le pex xout e840) 17Lotes Lote 2 ¢ £ ¢ 2 rs r eeeeeee pi tgseeess BoB R Eg r2zeseegzessFsaRe & eet a rt As eek = rd wHedas 7 2 r wre A0t4as No. 4520-2/22

LC7868E, 7869E Specifications Absolute Maximum Ratings at Ta = 25°C, Vg, = 0 V [__Parameser Symbol J Conaiton Rang nit Tain Sup voage [Vooman[ eg TV | Maximum npr vage [vee [= Wg = 0 Vg v0 Maximum euputvoage [Wourmax] SSS Y Vag 081 pg 08 Allowable power dissipation a [Seeing tenperwre «| Ctope [SSCS | [Swasewnpeae «dita SSCS TSC ts | | Allowable Operating Ranges at Ta = 25°C, Vsg = 0 V Parametor Genaton ee Supa oiage [Woo [vo ss TEST1 to 5, Al, F2D, HFL, DEMO, DFOFF, Input high level voltage Mw @)_| SBCK, RWC. COIN, COCK, CS a Viv(9)_ EF A [wt [res 08 vp VP TEST1 10 5, Al, FZD, HFL, DEMO, DFOFF, Input ow level voltage SBCK, AWC, COIN, COCK, CS [vss | Toe Tv CN AS CZ [vat [tes gg 0200 [Data sewptime setup | COIN, RWC: Figure t [ao fs [Dano ime | thoid | RWC: Figure 1 | High level clock pulse width | twen | SBCK, COCK: Figures 1, 2and3 | 4o | | |ons | Low level clock pulse width COCK, SBCK: Figures 1,2 and3 [| ao | | [rs | AWG: Feu # [00 [oe] Sub-0 read rable iro Figure 2, no RWG signa ea Sabcol ead ore [ise [Fewest | Sibeode oad erable [tse [Fowes a8] [Crystal oscar reavoney [Xi Koy re] | Operating koquency range foo) [Ao 20 Te Electrical Characterlstics at Ta = 25°C, Vgg = 0 V, Vpp = 5 V : [sim | ce 5 ameter ni nit “ _ [min [yp Tmax C2 A \\ Al, EFMIN, FZD, TES, SBCK, COIN, M4) | COCK, RES, HEL, RWC, ML: Vin = Vop. nA Input high level current TESTI 105, DEMO, GS: COCK, RES, HFL, RWC, ML: Vin = Veg, AO, PDO, EFMO, EFMO, CLV*, CLV-, Vv 1 FOCS, FSEQ, PCK, TOFF, TGL, THLD, vi 1 Vv fon) | ype, JP-, EMPH, EFLG, FSX, VIP: oD - lon =~1 mA Vout) | OOUT: i =1@ma a a Output high level voltage TASER, SQOUT, 16M, 4.2M, CONT, LRCLK, WRQ, C2F, DACLK, SFSY, LRSY, Vouta) | SBSY. CK2, PW, ROMOUT, C2FCLK, Vop-1 v ‘ow (3) | DFOUT (DATAL), TESTS (DATAR), TEST} VOD (SYSCLK), WCLK (TEST7), DFIN: lon =-0.5 mA Note: Pin names in parentheses are for the LC7869E ‘Continued on next page. No. 4520-3/22

LC7868E, 7869E tec (fo twer SBCK -_ two Yowoyaeyey nyu yw Yor y “or Pn Ree Keds hee yg ov fe trac aoteas Figure 3 Subcode Output Pin Description [Re [Rene [9 [ig [+ _|_test: | _1 _| Sttestinput, Normaliy unconnected. es Pin for input of the on-chip VCO output from the LA9210 (8.6436 MHz), Phase detector output (PDO) is phased output ao with the EFM signal, st so that frequency is raised by positive voltage. A a [77 FMo 6] [routs 1 10 2 Vep HF signal to EFMIN. Complementary EFM signal outoutis made trom EFMO and EFHIO via the amplitude timiter. These are used for slice level control. |e | erwn [| | 9 | Test2 | 1 | LSitestinput. Normally unconnected. = | 2] seri cont ouput. Lif av | o | [12 [we | © [| Outputis high with constant linear velocity rough servo, and low during phase control [+3 | Focs | o | [14 _[__ FST [0] Fotus servos switched olf when FOCS is high, Lens is lowered by FST and raised gradually when FOCS is high. Generation of FZD resets FOCS. Used for focus servo control. ps | ro | p16 [ HFL | tT Generates kick pulse, JP», or JP- according to track jump command. Jumps the specified number of tracks (1, 2, 4, | 18 | pck | 0 | 4.3218 MHz PCK monitor output. High when SYNC (true frame syne) detected trom the EFM signal matches SYNC from counter (interteaving frame sync). (Single-frame latch output) | 20 | | o | [a1 [Te] 0] Generates kick pulse, JP, or UP- according to rack ump command. Jumps the speciied number of tacks (1,2, 4, 16, 32, 64, or 128), Le [Ho [0 | | 23 [| tests | 1 | LSttestinput. Normally unconnected. a | [25 [Pr [0 T Generates kick puise, JP», or JP according o track jump command. Jumps the specified number of tacks (1,2, 4, [26 [a [0 | 16,9266, 0128 [_27_| DEMO | 1 _| Sound generation function for set adjustment, | 26 | Testa | | | LSttestinput. Normally unconnected, | 29 | EMPH | 0 | Deemphasis required when high. | 30 | DrOFF | 1 | Digital iter on/off switch: the fiter is disabled when this pin is high. WCLK (TEST?) TESTS (SYSCLK) = = | ° | Signal outputs for the DvA converter, including tatch, L/A switching, and sample and hold signals. DFOUT (DATAL) [“36_[ pack [0] DFIN | © | LSttestinput. Normally unconnected. Note: Pin names in parentheses are for the LC7869E. Continued on next page. No, 4520-5/22

LC7868E, 7869E Continued from preceding page. A A | se trsy [0 | [39 [oe [0 | |_40 | ROMOUT | 0 _| Foroutputof CD-ROM interface signals. orFeik [oO _| ee | 44 [| sasy | © { Subcode block synchronization output [45 [| EFLG | © | Ciand C2 single and double error correction flag. pe {et 'SFSY is subcode frame synchronization signal. P, Q, R, S, T, U, V, and W subcodes are read out by sending clock a as a [49 | FSX | © | 7.95kHz synchronization signal output | st [| RWC | |__| WRQgoes highwhen Q subcode dala passes the CRC check. Through exiernal connection and sending of GOK, [52 | SoouT | 0 _| 2#t8is read trom SQOUT. Set MSB-rsvLSB-tst to low when datain LSB-fst formats desired. [oss] con [1] ‘Command is generated by sending output synchronized with CQCK command data alter setting microprocessor RWC to high. [Wes [mes [1 | Sorwtewatpovows SS [56] wt [1 [Sane as or pins 501 50 TASER | 0 | Permits control via serial control from the microprocessor. [so [42m [0 _| «2006 wie output [60 | CONT | © | Permits control via serial control from the microprocessor. | 61 [| tests | 1 _[ LSttestinput. Normally unconnected [62 { CS | 1 _{ Chip setectpin. The LC7868/69 becomes active when this pin is low. (pull-down resistor built in) Le [Your | o | Note: Pin names in parentheses are for the LC 7869. Functional Description HF Signal Input Circuit (pin 8: EFMIN, pin 7: EFMO and pin 6: EFMO) An EFM signal (NRZ) sliced at the optimum level is obtained when the HF signal is input on EFMIN. Q Q HF signal PE | : | 404440 No. 4520-622

LC7868E, 7869E PLL Clock Regeneration Circuit (pin 4: PDO, pin 3: AI, and pin 2: AO) d PCK Yop Poo < Prece ~<—— EFM (NRZD lcomparator LAg210 Aosaas A PLL comprising a VCO can be made with an LA9210. Output from the PDO pin goes positive when the VCO phase is lagging. VCO Half-Frequency Clock (pin 18: PCK) This pin monitors a signal generated by dividing the VCO frequency by two. This signal has an average frequency of 4.3218 MHz. Frame Synchronization Detector Monitor (pin 19: FSEQ) FSEQ is latched high for one frame when the frame sync (true synchronization signal) recovered from the EFM signal matches the sync timing generated by an internal counter. Servo Command Function (pin 51: RWC, pin 53: COIN, pin 54: CQCK and pin 62: CS) Commands can be input by setting RWC high and issuing the command synchronized to the CQCK clock from COIN. Focus start Track jump Mute control 1-byte commands Disc motor control Other control commands Track count 1 2-byte command. 1, 1-byte Commands RWC cack te MSB Aosaaz No. 4520-7/22

LC7868E, 7869E | 2. 2-byte Commands AWC an ik os es an Se es 2: nn Sn in ae ae | earn TTY TTE TT Ty TTP yi ty) , fT vert ys | 01443 The commands are executed on the falling edge of RWC. | Focus Servocontroller (pin 13: FOCS, pin 14: FST, pin 15: FZD and pin 57: LASER) [se tse Command ES tow

00001000 FOCUS START #1

10100010 FOCUS START #2

00001010 LASER ON

10001010 LASER OFF

00000000 NOTHING

1, Laser Control RWC | cack 2 ne on ne ne nn a ee en ee oe com EPPE PPP ry NPE errr ery TASER y) Aosesa 2. Focus Start When a Focus Start command (either 1 or 2) is issued, the pickup lens is first lowered as C1 discharges through FST and then raised gradually as Cl is recharged by FOCS. FZD goes low when the focal point is reached, and FOCS is reset and the focus servocontroller turned on when this signal is received, After issuing this command, the microprocessor checks the DRF signal from the LA9210 to verify that focus has been reached, and advances to the next step. If C1 recharges fully before focus has been reached, the Focus Start command should be reissued to repeat operation of the focus servocontoller. No. 4520-8722

LC7868E, 7869E RWC coEK corn Pere r rey] Fst =50ms (240ms) Focs Fz0 AoLaas Note: If for Focus Start 2, the value in parentheses is in effect only whan FST is low (unlike Focus Start 1). Notes: 1. The falling edge of FZD is not accepted when FST is low. 2. After a Focus Start command has been issued, the focus servocontroller is reinitialized when RWC goes high. For this reason, a new command should not be issued until the S-curve for the focus coil drive has been completed. 3. If focus cannot be reached (i.e., the FZD signal does not go low), the FOCS signal remains high and the lens remains raised. In this case, the Nothing command should be issued to reinitialize the servocontroller. 4, When the RES pin is set low, LASER is directly set high. 5. Focus start using the DEMO pin is in mode 1. F.E mz cA 4 \\/ -sv | | +5v : 15 | 13_|14 Constant Linear Velocity Servocontroller (pin 10: CLV+, pin 11: CLV- and pin 12: V/P) a 2

00000100 DISC MOTOR START (accelerate)

00000101 DISC MOTOR CLV (CLV)

00000110 DISC MOTOR BRAKE (decelerate)

00000111 DISC MOTOR STOP (stop)

The disc motor accelerates when CLV+ is high and decelerates when CLV- is high. These outputs are selected by the motor mode commands issued by the microprocessor (accelerate, decelerate, CLV, or stop). The CLV* and CLV- outputs for each mode are shown in the following table. a a a SL [Sop tg to No. 4520-9/22

LC7868E, 7869E ee a4] ClLv— - + 4 | TT < ( DISC MOTOR L 401447 Note: + For constant linear velocity servo control commands, the TOFF pin is low only in the CLV mode; otherwise it is high. Control of the TOFF pin by command is effective only in the CLV mode. 1. CLV Mode * In the CLV (constant linear velocity) mode, the LC78681E detects disc speed from the HF signal and switches the internal DSP mode to perform various types of control for maintaining the correct linear velocity. The pulse-width modulation cycle is 7.35 kHz, and the 1/64 duty cycle is 1.114 s. V/P outputs high during rough servo and Jow during phase control. [ Rouphsenovelciy ole Th twig [ Roughsero velciy ohigh) [tow High Tigh [Press conteieuexeid) | Pw wd td 2. CLV Control Gain Switching

40101000 DISC 8 set

10101001 DISC 12 set °°

CLV control gain during rough switching for 8-cm discs can be set at 8.5 dB lower than for 12-cm discs. 3. Internal Brake Mode [sa sa command Sw

11000101 Internal brake on

11000100 Internal brake oft

a | * The internal brake mode is enabled when an Internal Brake On command (C5H) is input. Executing a Brake command (06H) in this mode allows the deceleration of the disk to be monitored at the WRQ pin. * In this mode, the EFM signal density per frame can be counted to determine the status of disc deceleration. When there are fewer than four EFM signals, CLV- falls to low, and the WRQ pin simultaneously goes high to indicate that brakes is completed. The microprocessor issues a Stop command when it senses that the WRQ pin is high, thereby completing the stopping of the disc. * Note that if false deceleration state detections occur, changing the EFM signal count from 4 to 8 using the internal brake control command (A3H) may help in some cases. eee No. 4520-10/22

LC7868E, 7869E 06H command civ- j notes Notes: 1. If focus is lost during execution of an internal brake command, it is necessary to first refocus and then input the internal brake command again. 2. Due to the possibility of state determination errors due to the EFM signal playback state (e.g., damaged disk or access in progress) we recommend that this product be used in conjunction with a microprocessor. Track Jump Circuit (pin 16: HFL, pin 17: TES, pin 20: TOFF, pin 21: TGL, pin 22: THLD, pin 25: JP* and pin 26; JP-) 1. Internal Track Count The LC7868/69 supports two internal track counting modes, as shown in the table below. SO oo1o00010 ‘New track count (combination of TES and HFL) oo100011 Standard track count (direct count of the TES signal) The standard track count uses the TES signal without modification as the internal track count clock. In order to reduce counting errors due to noise on the rising and falling edges of the TES signal, the new track counter suppresses this noise through combination with the HFL signal, enabling an accurate track count. However, if the HEL signal is lost because of foreign matter or scratching on the disk, no track count pulse may be generated. For this reason, caution is required when using this mode. No. 4520-1122

LC7868E, 7869E 2. Track Jump Commands MSB ise [oo Commang ES tw |

10100000 Standard track jump

10100001 New track jump

ooo0100014 T TRACK JUMP IN #1 00010010 1 TRACK JUMP IN #2 001100014 1 TRACK JUMP IN #3 00010000 2 TRACK JUMP IN 00010011 4 TRACK JUMP IN 00010100 16 TRACK JUMP IN 00110000 32 TRACK JUMP IN 00010101 64 TRACK JUMP IN 00010111 128 TRACK JUMP IN 00011001 1 TRACK JUMP OUT #1 ooo1r1o010 1 TRACK JUMP OUT #2 oo1r1r1001 1 TRACK JUMP OUT #3 00011000 2 TRACK JUMP OUT ooo0110114 4: TRACK JUMP OUT 00011100 46 TRACK JUMP OUT 00111000 32 TRACK JUMP OUT ooo011101 64 TRACK JUMP OUT ooor114d4 128 TRACK JUMP OUT

255 TRACK CHER ot

10001111 TON

10001100 TRACK JUMP BRAKE

When a track jump command is issued to the servocontroller, an acceleration pulse is generated (a period), followed by a deceleration pulse (b period) and braking (c period), completing the specified jump. TES and HFL input during braking detects the direction of beam slippage, and the portion of the TE signal that compensates for slippage is cut off by TOFF, which, together with boosting of the servo gain by TGL, supplements the destination track for the jump. Note: Of the disc motor control outputs, the TOFF pin is low in the CLV mode, and high in the Start Stop, and Brake modes. TOFF can also be independently switched on or off by the microprocessor. However, disc motor control is enabled only in the CLV mode. No. 4520-12/22

LC7868E, 7869E 3. Track Jump Modes The relationship between acceleration pulses, deceleration pulses, and brake periods is shown in the following table. Standard track jump mode New track jump mode conmand Pee TTRAGKIOMP NOU [ee «did did TTRAGK JUMPIN OUT) #2 [osvackime _[2s0ys [aims [osvactimp [apered | zame ‘| 2 TRACK JUMP IN (OUT) There are no a, b, or ¢ periods. STRACK JUNPIN(OUT) | ZvecKhum [#86 y0 ___—‘[2ems__[ewackunp [apoiod [tens | TB TRACKUMP IN(OUT)_[vackjomp | Tvackiunp [ees | @vecrionp [apeied [ema | S2TRACK JUMPIN (OUT) | Teiackiump | reckimp [esms ~~ [ eaccurp __[evaccine [eames | G4 TRACK JOMBWN (OUT) [SEveckiump [2a-veckimp _[24ms | oe-vackjurp | ee-vackiurp | 24ms |

123 TAAGK JUN IN (OUT) Secvackionp [Bes | Tevackino | Serackione | 2¢ms |

TOFF goes high after 256 tracks are TOFF goes high after 256 tracks are 256 TRACK CHECK jumped. The a and b pulses are not jumped. The a and b pulses are not output. output. TRACK JUMP BRAKE There are no a or b periods. [24ms __| There arenoaorb periods. [zams | Notes: 1. The actuator drive signals are not generated for the 256-track Check. Instead issuance of a feed motor signal is required because the TES signal is in the track-count mode and the tracking servocontroller is oft. 2. The servocontroller register is automatically reset afier one a, b, and c track jump sequence. 3, When a new track jump command is issued while a previous command is still being processed, the new command is executed immediately. 22 24 20 26 25 HEL () | Slip detector Tes = 8 | BKEA aos4s0 4, Track Check Mode MsB use [Command RSs

11110000 Track Count In

11111000 Track Count Out

raoaaradd 2-byte COMMAND RESET A Track Count In or Track Count Out command followed by a binary number between 16 and 254 can be used to start track counting for the specified number of tracks. Track Count in/ Binary input of desired Two-byte Command Reset Brake command ‘Out command track number Track count —— waa N poses Rises at (track count) /2 Falls at track count No. 4520-13/22

LC7868E, 7869E Notes: 1. The fall of RWC when the desired number of tracks is input in binary format starts the track count. 2. During track counting, TOFF is high and the tracking servocontroller is tuned off. For this reason, issuance of a feed motor signal is required. 3. The Track Count In and Track Count Out commands cause the WRQ signal to change from the Q subcode . standby monitor when normal to the track count monitor. WRQ goes high at half the track count and low again at the end of the count. The microprocessor monitors WRQ to detect track count completion. 4. When a 2-byte Command Reset command is not issued, the track count starts again. For example, to advance 20,000 tracks, the microprocessor can set the track count number to 200 and wait 100 WRQ pulses. 5. The Brake command is used to bring the pickup to the track when counting is finished. Error Flag Output (pin 45: EFLG and pin 49; FSX) FSX ‘One correction : Two corrections l Uncorrectable No error aotas2 The 7.35 kHz FSX frame synchronization signal is divided down from the reference clock. The status of error correction in each frame is output on EFLG, as shown in the figure, where the number of high pulses in each FSX period indicates the quality of the replay signal. P, Q, and R through W Subcode Output Circuit (pin 46: PW, pin 44: SBSY, pin 47: SFSY and pin 48: SBCK) PW is the subcode signal output pin. The falling edge of SFSY starts the 136 [1s period during which SBCK is clocked eight times, allowing all codes — P, Q, and R through W — to be read. The signals appearing at the PW pin change with the rising edge of SBCK. When SBCK is static, the P code is input to PW. SFSY is the signal output for each subcode frame, and the rising edge of this signal indicates standby status for output of the subcode symbols (P through W). Subcode data P if output simultaneously with the falling edge of this signal. SFSY SBCK To. WoV V V V Vv V V V V em oheY oe Xe Xr Xe Xv Xv frets 404483 SBSY is output for each subcode block. It is high during the SO and S1 synchronization cycles. Its falling edge indicates the end of synchronization and the start of E[AJ-format data within the subcode block. so | s1 | se | sa | ss | ss | so 96 | ss7_| so | si | se sBsy sFsy posse No. 4520-14/22

LC7868E, 7869E Q Subcode Output Circuit (pin 50: WRQ, pin 51: RWC, pin 52: SQOUT, pin 54: CQCK, pin 56: M/L and pin 62: CS) [sp tse Corman RES wow 00001001 ‘ADDRESS FREE

10001001 ADDRESS 1

Q subcode data can be read from the SQOUT pin by clocking the CQCK pin. Of the 8-bit subcode data, the Q signal is effective for operations such as song access and display. WRQ is high only when the block CRC is correct and the address in the Q subcode format is 1*.When the microprocessor senses that WRQ is high and issues CQCK, data can be read from SQOUT in the sequence indicated below. When CQCK is activated, the DSP disables internal register updating. When the microprocessor finishes reading data, it briefly sets RWC high to reenable data updating and resets WRQ low. CQCK should start to oscillate in the 11.2 ms period during which WRQ is high. Data can be read in LSB-first format when M/L is low and in MSB-first format when it is high. Note: * This condition is ignored when the Address Free command is issued. (The Address Free command is used in CD-V applications.) > Mis high —— Mis low ee ee output remains unchanged whether Note: * Items in parentheses are for the disc lead-in area. No. 4520-15/22

LC7868E, 7869E wRo Bopit i sebit rack CONT AOR AFLAME f Q subcode data Level meter or peak meter data : Rc Aosass Notes: 1. The WAQ pin normally indicates Q subcode standby status, but provides different information during the Track Count mode or internal braking. . (See the sections on track counting and internal braking.) 2. The LC78681E is active when CS is low, with output from SQOUT. SQOUT is in the high-impedance state when the GS pin is high. Reading Level Meter (LVM) and Peak Meter (PKM) Data [sp tse Command RES tow .

001010114 PKM set (LVM reset)

oo101100 LVM set (PKM reset)

00101101 PKM mask set

Level Meter (LVM) * The Level Meter mode is enabled by inputting the Level Meter Set command (2CH). + Level meter data is 16 bits, and is composed of 15 bits of absolute-value data and an MSB indicating left-right polarity. Data is for the left channel when the MSB is high and for the right channel when low. * Level meter data is appended at the end of 80 bits of Q subcode data, and can be read from the SQOUT pin by clocking the CQCK pin 96 times. The left and right channels are swapped each time that level meter data is read. The left and right channels are independent, and the highest value read for each of the channels is held. 2. Peak Meter (PKM) * The Peak Meter mode is enabled by inputting the Peak Meter Set command (2BH). * Peak meter data is 16 bits, and is composed of 15 bits of absolute-value data and an MSB fixed at 0. The maximum value is detected with no regard for right or left channel. + Peak meter data is read in a manner similar to that for level meter data. However, data is not updated by further reading. * The absolute time for Q subcode data when in the Peak Meter mode is issued while holding the absolute time (ATIME) that is detected after generation of the maximum value. (Relative time is normal operation.) + Issuing a Peak Meter Mask Set command causes values larger than the maximum value already in memory to be ignored, even when this command is issued in the Peak Meter mode. This is canceled by the Peak Meter Mask Reset command (used in peak searches for songs in memory). No. 4520-16722

LC7868E, 7869E Mute Control Circuit ssn ed

00000001 Mute 0 dB

00000010 Mute ~12 dB

00000011 Mute = dB

Volume can be reduced by 12 dB (MUTE -12 dB) or muted fully (MUTE dB) by issuing the commands shown above. Muting switches at zero crossings to prevent switching noise on the audio output. A zero crossing is judged to be any data where the upper seven bits are all 1 or all 0. Bilingual Function [ss tsa omman RS tw

00101000 STOCONT

00101001 Lich CONT

00101010 Reh CONT

+ The left and right channels are output to the left and right channels when reset or when the Stereo command (28H) is issued. + Left channel data is output to both the left and right channels when the Left Channel Set command (29H) is issued. * Right channel data is output to both the left and right channels when the Right Channel Set command (2AH) is issued. Deemphasis Control (pin 29: EMPH) The preemphasis on/off bit in the Q subcode data is output on EMPH. Deemphasis is required when EMPH is high. [8 rn ee a The LC7868/69 includes a digital deemphasis circuit in the Difil block. On reset, the IC enters a mode in which the internal deemphasis is used. If an external deemphasis circuit is added, issue the DEP OFF command described above. D/A converter interface; Pin 30: DFOFF, pin 31: WCLK (TEST7), pin 32: TEST (SYSCLK), pin 33: LRCLK, pin 34: DFOUT (DATAR), pin 35: DFOUT (DATAR), pin 36: DACLK Data for the D/A converter is output from DFOUT MSB first, synchronized with the falling edge of DACLK. [sp tse Commang RES tow

01100010 DF FORM IS

01400011 DF FORMLC78815

01101000 DF FORMB.B

10001000 CD-ROM XA

10001014 CONT and CD-ROM XA reset

When the CD-ROM XA command listed above is issued, data for which neither interpolation nor muting is performed is output from DFOUT. This is for use with CD-ROM XA applications, Note that the CD-ROM XA reset is shared with the CONT reset (pin 60). No. 4520-17/22

LC7868E, 7869E (a) Le7aese cars) Leveess eS a cc ar | a pas teste a an Pm Maree ENC) CT CO EY NED ED CE) CE ED) ee mee UTC UU oot 2.8. pacer Op paz reste evs A ci ose este SR bear rent) SEREEREP EEE PEE TetTsTe) pa once TULnuuinininnnninnn TUnULuunn 118 ponysee Op bests tS cc cS p34 sesta a error PEEEEEEr ECE EEE ESC Ta TEESE] : . ta 3 2 2 2 i “ as @) \\c7e69e (FS) Leveeis pay Test7 Wa) paz syscuw UUM estes nun nen pas gate AENEAN CS CHEN ETA PERSE EP PT EEEEET Pan garn, PEEEEMED PPE E TT PEE REn REP oP EEE 1 * te ‘3 0 23 30 . a as pss ovcte UUUUU UU UU UU 8.8. Pee ee) ps2 syscux UUUUULIUIIUIUIUU UU mess a a rs P3a pases PEERERED TPE ET ETT PREEEME PE POET TTT) Pas paras PREBERED TEE EET CATES EDGE CVC AE ALESIS 118 a 9? ecu TTT ests, a a Ae P34 antes PEE BEMEP POE EE ETT PREBEREE PP Er rE Pan onrn OMB EO Oo Oe Goce PEPER PRET A * te " a ” 10 2 « ae Sora eSeam TAO TOTOLU GU aQaQaQaVaNaUnOgesvaQatatataesOceananavaTatg trent at aatatsiqnstatslsegtataQseinatatar No. 4520-18/22

LC7868E, 7869E Output for CD-ROM (pin 39; CK2, pin 37: LRSY, pin 40; ROMOUT: pin 42: C2F and pin 41: C2FCLK) Data from the ROMOUT pin which is synchronized with the LRSY signal is output in MSB-first format. Because this data has not been processed by either the interpolation, previous-value hold, or digital filtering circuits, it is suitable for CD-ROM IC input. CK2 is a 2.1168 MHz clock, and data is output on its rising edge. C2F flags 8-bit units of data, and is synchronized to C2FCLK. C895 10-LC7868/69 Interface 4847.0 4 2 7 8 8 10411213 1415 26 17 10 19 20 24 22 29 24 25 2691 32.33 34 35.26 37 36.29 40 4: 42434045 4647 0 4 Lnsy te or, ach r_ sowour Pl oe PPP E PE PTE EP Ly -o bb Pele P TEE eL Le) noses Digital Audio Out Circuit (pin 43: DOUT) This is the output pin for the digital audio interface, with output in EIAJ format. The signa! is output after interpolation and muting. This output pin has a built-in driver, and can drive a transistor directly.

01000010 BOUT ON

01000011 DOUT OFF

01000000 UBIT ON

+ The digital out pin can be fixed low by issuing the DOUT OFF command. + The UBIT data in the DOUT data can be fixed at 0 by issuing the UBIT OFF command. Control Pin (pin 60: CONT) a [Pecan onto Od The CONT pin can be set high by issuing the CONT Set command. Crystal Oscillator (pin 63: Xyy and pin 64: Xoyr) a 100017110 ‘OSC ON

100011014 OSC OFF

01100000 VCO8M

01100001 VCO 16M

: No. 4520-19722

LC7868E, 7869E ee A 16,9344 MHz crystal oscillator is attached at these pins to form the time base clock. The OSC OFF command turns off both the crystal oscillator and the VCO. The table below shows the relationship between the crystal oscillator and the VCO. 63 64 I X‘tal 16.9344MHz I in ihe t Aos4sa External a a <n Menaleemponens [esate nen er a a oT Recommended crystal oscillator constants a CT 4.2M and 16M Pins (pin 59: 4.2M and pin 58: 16M) The 16.9344 MHz buffer output from the 16.9344 MHz crystal oscillator is output from the 16M pin. This signal is divided by four to generate a 4.2336 MHz signal, which is output from the 4.2M pin. When the oscillator is not operating, these pins are fixed to either high or low. Reset Circuit (pin 55; RES) This pin should momentarily be held low after power-on before being driven high. This is set to -c dB for muting or to STOP for the disc motor. The states shown above in boxes are set directly when RES is low. +5V Aos450 om SSSSSSSSSSSSSeSSSSSSSSSSSSeeeeEE No. 4520-20722.

LC7868E, 7869E Audio Output for Calibration (pin 27; DEMO) —ttrin a0se AWC DEMO cLy Constant linear velocity mode Conditions under which FOCS goes low @ When focus is pulled in and the FZD pin has gone to zero. ure a8 @ When the RES pin is tow or the RWC ee is high Therefore, when setting DEMO high, RWC must Focs be low J s5ome @ DEMO pin is low FST A08465 Setting this pin high sets muting to 0 dB and the disc motor to constant linear velocity, even when the microprocessor issues no command, and activates focusing. Because this also makes the LASER pin active, EFM signals and audio output can be obtained without the microprocessor as long as the mechanism and servo are hooked up correctly. Other Pins (pin 1: TEST1, pin 9: TEST2, pin 23: TESTS, pin 28: TEST4, pin 61: TESTS and pin 37: DFIN) These are test pins for the internal circuitry of the LC7868E and the LC7869E. TEST1 through TESTS have internal pull-down resistors. The test inputs can be left open during normal operation. Description of Block Operation 1, RAM Address Control The LC7868 includes an 8 bit by 2 kword RAM on chip. This is used as a +4 frame buffer memory for the EFM demodulated data jitter compensation function, which is implemented using address control. The buffer controller constantly monitors buffer free space and adjusts the CLV servocontoller divider ratio to keep the data write address in the middle of the buffer (i.., at zero). If the +4-frame limit is exceeded, the write address is forced to +0, and the output is muted for 128 frames because the resulting error cannot be handled by normal error processing algorithms. [tories Forces a a EC No. 4520-21/22

LC7868E, 7869E Cl and C2 Error Correction After EFM demodulation, data is written to the internal RAM, jitter is absorbed, and the processing described below is carried out under uniform timing according to the crystal clock. First, the C1 stage involves error detection and correction, determination of the C1 flags, and writing to the C1 flag register. Next, the C2 stage involves error detection and correction, determination of the C2 flags, and writing to the internal RAM. No errors No correction required Flag reset 1 error Correction Flag reset 2 errors Correction Flag set 3 errors or more Correction not possible Flag set No errors No correction required Fiag reset 1 error Correction Flag reset 2 errors Depends on C1 flags"! 3 errors or more Depends on C1 flags"? Notes; 1. If the error positions determined in the C2 stage match the C1 flags, correction is carried out and the flags are reset. However, if there are seven or more C1 flags, no correction is made (because of the danger of erroneous correction), and the C1 flags are taken as the C2 flags without change. If one error position matches but another does not, correction cannot be performed. Moreover, if there are five or fewer C1 flags, the results of the C1 stage may be incorrect, and the flag is set. If there are six or more, the situation is handled as uncorrectable, and the C1 flags are taken as the C2 flags without change. Correction is not possible if even only one error position is different, and the flags are set even it there are two or fewer C1 flags, because such data may be erroneous even if it passes the C1 stage. Otherwise the C1 flags are taken as the C2 flags without change, 2. I there are three or more errors and correction is determined to be impossible, no correction is made; if there are two or fewer C1 flags, data which passes the C1 stage may stil be corrupt, and so the flags are set. Otherwise the C1 flags are taken as the C2 flags without change No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss, HM Anyone purchasing any products described or contained herein for an above-mentioned use shall ® Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: @ Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO, LTD,, its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally, i Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guarant- eed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties, No. 4520-22722

Summary

Digital Signal Processor for Compact Disc Players???

Description