LT3020 LINER
Document overview
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Technical content
LT3020/LT3020-1.2/ LT3020-1.5/LT3020-1.8 sn3020 3020fas TEMPERATURE (°C) –50 MINIMUM INPUT VOLTAGE (V) 1.1 1.0 0.9 0.8 0.6 0.7 0.5 0.4 0.3 0.2 0.1
3020 TA02
250–25 50 75 125100 IL = 100mA APPLICATIO SU
FEATURES
100mA, Low Voltage, Very Low Dropout Linear Regulator ■ VIN Range: 0.9V to 10V ■ Minimum Input Voltage: 0.9V ■ Dropout Voltage: 150mV Typical ■ Output Current: 100mA ■ Adjustable Output (VREF = VOUT(MIN) = 200mV) ■ Fixed Output Voltages: 1.2V, 1.5V, 1.8V ■ Stable with Low ESR, Ceramic Output Capacitors (2.2µF Minimum) ■ 0.2% Load Regulation from 0mA to 100mA ■ Quiescent Current: 120µA (Typ) ■ 3µA Typical Quiescent Current in Shutdown ■ Current Limit Protection ■ Reverse-Battery Protection ■ No Reverse Current ■ Thermal Limiting with Hysteresis ■ 8-Lead DFN (3mm × 3mm) and MSOP Packages 1.8V to 1.5V, 100mA VLDO Regulator ■ Low Current Regulators ■ Battery-Powered Systems ■ Cellular Phones ■ Pagers ■ Wireless Modems The LT 3020 is a very low dropout voltage (VLDO TM ) linear regulator that operates from input supplies down to 0.9V. This device supplies 100mA of output current with a typical dropout voltage of 150mV. The LT3020 is ideal for low input voltage to low output voltage applications, providing comparable electrical efficiency to that of a switching regulator. The LT3020 regulator optimizes stability and transient response with low ESR, ceramic output capacitors as small as 2.2 µF. Other LT3020 features include 0% line regulation and 0.2% typical load regulation. In shutdown, quiescent current typically drops to 3µA. Internal protection circuitry includes reverse-battery pro- tection, current limiting, thermal limiting with hysteresis, and reverse-current protection. The LT3020 is available as an adjustable output device with an output range down to the 200mV reference. Three fixed output voltages, 1.2V, 1.5V and 1.8V, are also available. The LT3020 regulator is available in the low profile (0.75mm) 8-lead (3mm × 3mm) DFN package with ex- posed pad and the 8-lead MSOP package. , LTC and LT are registered trademarks of Linear Technology Corporation. IN SHDN 2.2µF
3020 TA01
1.8V GND LT3020-1.5 VOUT 1.5V 100mA2.2µF VLDO is a trademark of Linear Technology Corporation. Minimum Input Voltage
LT3020/LT3020-1.2/ LT3020-1.5/LT3020-1.8 sn3020 3020fas (Note 1) Operating Junction Temperature Range Storage Temperature Range ABSOLUTE AXI U RATI GSW WW U PACKAGE/ORDER I FOR ATIOUU W TJMAX = 125°C, θJA = 35°C/ W*, θJC = 3°C/ W EXPOSED PAD IS GND (PIN 9) CONNECT TO PIN 4 *SEE THE APPLICATIONS INFORMATION SECTION TOP VIEW DD PACKAGE 8-LEAD (3mm × 3mm) PLASTIC DFN 1OUT OUT ADJ GND IN IN NC SHDN OUT OUT ADJ GND IN IN NC SHDN TOP VIEW MS8 PACKAGE 8-LEAD PLASTIC MSOP TJMAX = 150°C, θJA = 125°C/ W, θJC = 40°C/ W SEE THE APPLICATIONS INFORMATION SECTION LT3020EDD ORDER PART NUMBER Consult factory for parts specified with wider operating temperature ranges. DD PART MARKING LAEX LT3020EDD-1.2 LT3020EDD-1.5 LT3020EDD-1.8 ORDER PART NUMBER DD8 PART MARKING LBKC LBKD LBKF TJMAX = 125°C, θJA = 35°C/ W*, θJC = 3°C/ W EXPOSED PAD IS GND (PIN 9) CONNECT TO PIN 4 *SEE THE APPLICATIONS INFORMATION SECTION LT3020EMS8 ORDER PART NUMBER LT3020EMS8-1.2 LT3020EMS8-1.5 LT3020EMS8-1.8 ORDER PART NUMBER MS8 PART MARKING LTBKG LTBKH LTBKJ MS8 PART MARKING LTAGL TJMAX = 150°C, θJA = 125°C/ W, θJC = 40°C/ W SEE THE APPLICATIONS INFORMATION SECTION OUT OUT OUT GND IN IN NC SHDN TOP VIEW MS8 PACKAGE 8-LEAD PLASTIC MSOP TOP VIEW DD PACKAGE 8-LEAD (3mm × 3mm) PLASTIC DFN 1OUT OUT OUT GND IN IN NC SHDN
LT3020/LT3020-1.2/ LT3020-1.5/LT3020-1.8 sn3020 3020fas Minimum Input Voltage (Note 14) I LOAD = 100mA, TJ > 0°C 0.9 1.05 V ILOAD = 100mA, TJ < 0°C 0.9 1.10 V ADJ Pin Voltage (Notes 4, 5) V IN = 1.5V, ILOAD = 1mA 196 200 204 mV 1.15V < VIN < 10V, 1mA < ILOAD < 100mA ● 193 200 206 mV (Note 4) 1.5V < V IN < 10V, 1mA < ILOAD < 100mA ● 1.157 1.200 1.236 V 1.8V < VIN < 10V, 1mA < ILOAD < 100mA ● 1.447 1.500 1.545 V 2.1V < VIN < 10V, 1mA < ILOAD < 100mA ● 1.737 1.800 1.854 V Line Regulation (Note 6) ∆VIN = 1.15V to 10V, ILOAD = 1mA ● –1.75 0 1.75 mV LT3020-1.2 ∆VIN = 1.5V to 10V, ILOAD = 1mA ● –10.5 0 10.5 mV LT3020-1.5 ∆VIN = 1.8V to 10V, ILOAD = 1mA ● –13 0 13 mV LT3020-1.8 ∆VIN = 2.1V to 10V, ILOAD = 1mA ● –15.8 0 15.8 mV Load Regulation (Note 6) V IN = 1.15V, ∆ILOAD = 1mA to 100mA –1 0.4 1 mV VIN = 1.15V, ∆ILOAD = 1mA to 100mA ● –2 1 mV LT3020-1.2 V IN = 1.5V, ∆ILOAD = 1mA to 100mA –6 1 6 mV VIN = 1.5V, ∆ILOAD = 1mA to 100mA ● –12 6 mV VIN = 1.8V, ∆ILOAD = 1mA to 100mA ● –15 7.5 mV LT3020-1.8 V IN = 2.1V, ∆ILOAD = 1mA to 100mA –9 2 9 mV VIN = 2.1V, ∆ILOAD = 1mA to 100mA ● –18 9 mV Dropout Voltage (Notes 7, 12) I LOAD = 10mA 85 115 mV ILOAD = 10mA ● 180 mV ILOAD = 100mA 150 180 mV ILOAD = 100mA ● 285 mV GND Pin Current I LOAD = 0mA ● 120 250 µA VIN = VOUT(NOMINAL) ILOAD = 1mA 570 µA (Notes 8, 12) I LOAD = 10mA 920 µA ILOAD = 100mA ● 2.25 3.5 mA Output Voltage Noise C OUT = 2.2µF, ILOAD = 100mA, BW = 10Hz to 100kHz, VOUT = 1.2V 245 µVRMS ADJ Pin Bias Current V ADJ = 0.2V, RIPPLE = 1.2V (Notes 6, 9) 20 50 nA Shutdown Threshold V OUT = Off to On ● 0.61 0.9 V VOUT = On to Off ● 0.25 0.61 V SHDN Pin Current (Note 10) V SHDN = 0V, VIN = 10V ● ±0.3 µA VSHDN = 10V, VIN = 10V ● 3 9.5 µA Quiescent Current in Shutdown V IN = 6V, VSHDN = 0V 3 9 µA Ripple Rejection (Note 6) V IN – VOUT = 1V, VRIPPLE = 0.5VP-P, fRIPPLE = 120Hz, ILOAD = 100mA 64 dB LT3020-1.2 VIN – VOUT = 1V, VRIPPLE = 0.5VP-P, fRIPPLE = 120Hz, 60 dB ILOAD = 100mA LT3020-1.5 VIN – VOUT = 1V, VRIPPLE = 0.5VP-P, fRIPPLE = 120Hz, 58 dB ILOAD = 100mA LT3020-1.8 VIN – VOUT = 1V, VRIPPLE = 0.5VP-P, fRIPPLE = 120Hz, 56 dB ILOAD = 100mA The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TJ = 25°C.
ELECTRICAL CHARACTERISTICS
PARAMETER CONDITIONS MIN TYP MAX UNITS
LT3020/LT3020-1.2/ LT3020-1.5/LT3020-1.8 sn3020 3020fas Current Limit (Note 12) V IN = 10V, VOUT = 0V 360 mA VIN = VOUT(NOMINAL) + 0.5V, ∆VOUT = –5% ● 110 310 mA Input Reverse Leakage Current V IN = –10V, V OUT = 0V 1 10 µA Reverse Output Current V OUT = 1.2V, VIN = 0V 3 5 µA (Notes 11, 13) LT3020-1.2 V OUT = 1.2V, VIN = 0V 10 15 µA LT3020-1.5 V OUT = 1.5V, VIN = 0V 10 15 µA LT3020-1.8 V OUT = 1.8V, VIN = 0V 10 15 µA The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TJ = 25°C. PARAMETER CONDITIONS MIN TYP MAX UNITS Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: The LT3020 regulators are tested and specified under pulse load conditions such that TJ ≈ TA. The LT3020 is 100% production tested at TA = 25°C. Performance at –40 °C and 125°C is assured by design, characterization and correlation with statistical process controls. Note 3: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 125°C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability. Note 4: Maximum junction temperature limits operating conditions. The regulated output voltage specification does not apply for all possible combinations of input voltage and output current. Limit the output current range if operating at maximum input voltage. Limit the input voltage range if operating at maximum output current. Note 5: Typically the LT3020 supplies 100mA output current with a 1V input supply. The guaranteed minimum input voltage for 100mA output current is 1.10V. Note 6: The LT3020 is tested and specified for these conditions with an external resistor divider (20k and 30.1k) setting V OUT to 0.5V. The external resistor divider adds 10µA of output load current. The line regulation and load regulation specifications refer to the change in the 0.2V reference voltage, not the 0.5V output voltage. Specifications for fixed output voltage devices are referred to the output voltage. Note 7: Dropout voltage is the minimum input to output voltage differential needed to maintain regulation at a specified output current. In dropout the output voltage equals: (V IN – VDROPOUT). Note 8: GND pin current is tested with VIN = VOUT(NOMINAL) and a current source load. The device is tested while operating in its dropout region. This condition forces the worst-case GND pin current. GND pin current decreases at higher input voltages. Note 9: Adjust pin bias current flows out of the ADJ pin. Note 10: Shutdown pin current flows into the SHDN pin. Note 11: Reverse output current is tested with IN grounded and OUT forced to the rated output voltage. This current flows into the OUT pin and out of the GND pin. For fixed voltage devices this includes the current in the output resistor divider. Note 12: The LT3020 is tested and specified for these conditions with an external resistor divider (20k and 100k) setting V OUT to 1.2V. The external resistor divider adds 10µA of load current. Note 13: Reverse current is higher for the case of (rated_output) < VOUT < VIN, because the no-load recovery circuitry is active in this region and is trying to restore the output voltage to its nominal value. Note 14: Minimum input voltage is the minimum voltage required by the control circuit to regulate the output voltage and supply the full 100mA rated current. This specification is tested at V OUT = 0.5V. At higher output voltages the minimum input voltage required for regulation will be equal to the regulated output voltage VOUT plus the dropout voltage. TYPICAL PERFOR A CE CHARACTERISTICSUW Typical Dropout Voltage Dropout Voltage Quiescent Current OUTPUT CURRENT (mA) DROPOUT VOLTAGE (mV) 250 225 200 150 175 125 100
3020 G01
TJ = 125°C TJ = 25°C TEMPERATURE (°C) –50 DROPOUT VOLTAGE (mV) 250 225 200 150 175 125 100
3020 G02
250–25 50 75 125100 IL = 1mA IL = 100mA IL = 50mA IL = 10mA VOUT = 1.2V TEMPERATURE (°C) –50 QUIESCENT CURRENT (µA) 250 225 200 150 175 125 100
3020 G03
250–25 50 75 125100 VSHDN = VIN VSHDN = 0V VIN = 6V VOUT = 1.2V IL = 0
LT3020/LT3020-1.2/ LT3020-1.5/LT3020-1.8 sn3020 3020fas TEMPERATURE (°C) –50 ADJ PIN VOLTAGE (mV) 206 204 202 198 200 196 194
3020 G04
250–25 50 75 125100 IL = 1mA ADJ Pin Voltage TYPICAL PERFOR A CE CHARACTERISTICSUW INPUT VOLTAGE (V) QUIESCENT CURRENT (µA) 1000 900 800 600 700 500 400 300 200 100
3020 G05
VOUT = 1.2V IL = 0 TJ = 25°C VSHDN = VIN VSHDN = 0V INPUT VOLTAGE (V) GND PIN CURRENT (µA) 2500 2250 2000 1500 1750 1250 1000 750 500 250
3020 G06
VOUT = 1.2V TJ = 25°C RL = 12Ω IL = 100mA RL = 24Ω IL = 50mA RL = 120Ω IL = 10mA RL = 1.2k, IL = 1mA Quiescent Current GND Pin Current TEMPERATURE (°C) –50 OUTPUT VOLTAGE (V) 1.830 1.820 1.810 1.800 1.790 1.780 1.770 25 75
3020 G22
–25 0 50 100 125 IL = 1mA TEMPERATURE (°C) –50 OUTPUT VOLTAGE (V) 1.530 1.520 1.510 1.500 1.490 1.480 1.470 25 75
3020 G23
–25 0 50 100 125 IL = 1mA TEMPERATURE (°C) –50 OUTPUT VOLTAGE (V) 1.230 1.220 1.210 1.200 1.190 1.180 1.170 25 75
3020 G24
–25 0 50 100 125 IL = 1mA INPUT VOLTAGE (V) 1000 900 800 700 600 500 400 300 200 100 QUIESCENT CURRENT (µA)
3020 G25
VOUT = 1.8V (LT 3020-1.8) IL = 0 TJ = 25°C VSHDN = VIN VSHDN = 0V INPUT VOLTAGE (V) 2500 2250 2000 1750 1500 1250 1000 750 500 250 GND PIN CURRENT (µA)
3020 G26
VOUT = 1.8V (LT 3020-1.8) TJ = 25°C RL = 18Ω IL = 100mA RL = 36Ω IL = 50mA RL = 180Ω IL = 10mA RL = 1.8k IL = 1mA INPUT VOLTAGE (V) 1000 900 800 700 600 500 400 300 200 100 QUIESCENT CURRENT (µA)
3020 G27
VOUT = 1.5V (LT 3020-1.5) IL = 0 TJ = 25°C VSHDN = VIN VSHDN = 0V Output Voltage Output Voltage Output Voltage Quiescent Current GND Pin Current Quiescent Current
LT3020/LT3020-1.2/ LT3020-1.5/LT3020-1.8 sn3020 3020fas GND Pin Current vs ILOAD SHDN Pin Threshold SHDN Pin Input Current SHDN Pin Input Current (µA) ADJ Pin Bias Current Current Limit OUTPUT CURRENT (mA) GND PIN CURRENT (µA) 2000 1800 1600 1200 1400 1000 800 600 400 200
3020 G07
VIN = 1.7V VOUT = 1.2V TJ = 25°C TEMPERATURE (°C) –50 SHDN PIN THRESHOLD (V) 1.0 0.9 0.8 0.6 0.7 0.5 0.4 0.3 0.2 0.1
3020 G08
250–25 50 75 125100 IL = 1mA SHDN PIN VOLTAGE (V) SHDN PIN INPUT CURRENT (µA) 5.0 4.5 4.0 3.0 3.5 2.5 2.0 1.5 1.0 0.5
3020 G09
TJ = 25°C TEMPERATURE (°C) –50
3020 G10
250–25 50 75 125100 VSHDN = 10V SHDN PIN INPUT CURRENT (µA) 5.0 4.5 4.0 3.0 3.5 2.5 2.0 1.5 1.0 0.5 TEMPERATURE (°C) –50 ADJ PIN BIAS CURRENT (nA)
3020 G11
250–25 50 75 125100 TEMPERATURE (°C) –50
3020 G12
250–25 50 75 125100 VOUT = 0V VIN = 1.7V VIN = 10V CURRENT LIMIT (mA) 500 450 400 300 350 250 200 150 100 Reverse Output Current Input Ripple Rejection TEMPERATURE (°C) –50
3020 G13
250–25 50 75 125100 VIN = 0V VOUT = 1.2V REVERSE OUTPUT CURRENT (µA) 500 450 400 300 350 250 200 150 100 FREQUENCY (Hz) RIPPLE REJECTION (dB)20 10 1k 10k 1M
3020 G14
VIN = 1.5V + 50mVRMS RIPPLE VOUT = 0.5V IL = 100mA COUT = 2.2µF COUT = 10µF TYPICAL PERFOR A CE CHARACTERISTICS UW INPUT VOLTAGE (V) 2500 2250 2000 1750 1500 1250 1000 750 500 250 GND PIN CURRENT (µA)
3020 G28
VOUT = 1.5V (LT 3020-1.5) TJ = 25°C RL = 15Ω IL = 100mA RL = 30Ω IL = 50mA RL = 150Ω IL = 10mA RL = 1.5k IL = 1mA GND Pin Current
LT3020/LT3020-1.2/ LT3020-1.5/LT3020-1.8 sn3020 3020fas TEMPERATURE (°C) –50 MINIMUM INPUT VOLTAGE (V) 1.1 1.0 0.9 0.8 0.6 0.7 0.5 0.4 0.3 0.2 0.1
3020 G16
250–25 50 75 125100 IL = 100mA TEMPERATURE (°C) –50 LOAD REGULATION (mV) 1.0 0.8 0.6 0.2 0.4 –0.2 –0.4 –0.6 –0.8 –1.0
3020 G17
250–25 50 75 125100 VIN = 1.15V VOUT = 0.5V *LOAD REGULATION NUMBER REFERS TO CHANGE IN THE 200mV REFERENCE VOLTAGE Minimum Input Voltage Load Regulation ∆IL = 1mA to 100mA Output Noise Spectral Density RMS Output Noise vs Load Current (10Hz to 100kHz) TYPICAL PERFOR A CE CHARACTERISTICSUW TEMPERATURE (°C) –50 RIPPLE REJECTION (dB) 100
3020 G15
250–25 50 75 125100 VIN = 1.5V + 0.5VP-P RIPPLE AT f = 120Hz VOUT = 0.5V IL = 100mA FREQUENCY (Hz) OUTPUT NOISE SPECTRAL DENSITY (µV/√Hz) 0.1 0.01 1k 100k 1M100 10k
3020 G18
VOUT = 1.2V IL = 100mA COUT = 2.2µF LOAD CURRENT (mA) OUTPUT NOISE (µVRMS) 300 250 200 150 100 0.01 1 10 100
3020 G19
0.1 VOUT = 1.2V COUT = 2.2µF No-Load Recovery Threshold OUTPUT OVERSHOOT (%) OUTPUT CURRENT SINK (mA)
3020 G20
50µs/DIV 3020 G21 IOUT = 10mA TO 100mA VOUT = 1.5V Input Ripple Rejection
LT3020/LT3020-1.2/ LT3020-1.5/LT3020-1.8 sn3020 3020fas UUUPI FU CTIO S OUT (Pins 1, 2): These pins supply power to the load. Use a minimum output capacitor of 2.2µF to prevent oscillations. Applications with large load transients require larger out- put capacitors to limit peak voltage transients. See the Applications Information section for more information on output capacitance and reverse output characteristics. OUT (Pin 3, Fixed Voltage Device Only): This pin is the sense point for the internal resistor divider. It should be tied directly to the other OUT pins (1, 2) for best results. ADJ (Pin 3, Adjustable Device Only): This pin is the inverting terminal to the error amplifier. Its typical input bias current of 20nA flows out of the pin (see curve of ADJ Pin Bias Current vs Temperature in the Typical Perfor- mance Characteristics). The ADJ pin reference voltage is 200mV (referred to GND). GND (Pin 4): Ground. SHDN (Pin 5): The SHDN pin puts the LT3020 into a low power state. Pulling the SHDN pin low turns the output off. Drive the SHDN pin with either logic or an open collector/ drain device with a pull-up resistor. The pull-up resistor supplies the pull-up current to the open collector/drain logic, normally several microamperes, and the SHDN pin current, typically 2.3µA. If unused, connect the SHDN pin to V IN. The LT3020 does not function if the SHDN pin is not connected. IN (Pins 7, 8): These pins supply power to the device. The LT3020 requires a bypass capacitor at IN if it is more than six inches away from the main input filter capacitor. The output impedance of a battery rises with frequency, so include a bypass capacitor in battery-powered circuits. A bypass capacitor in the range of 2.2µF to 10µF suffices. The LT3020 withstands reverse voltages on the IN pin with respect to ground and the OUT pin. In the case of a reversed input, which occurs if a battery is plugged in backwards, the LT3020 acts as if a diode is in series with its input. No reverse current flows into the LT3020 and no reverse volt- age appears at the load. The device protects itself and the load. GND (Pin 9, DD8 Package Only): Ground. Solder Pin 9 (the exposed pad) to the PCB. Connect directly to Pin 4 for best performance. BLOCK DIAGRA W SHUTDOWN CURRENT GAIN THERMAL SHUTDOWN 3020 BD ERROR AMP NO-LOAD RECOVERY IN (7, 8) OUT (1, 2) OUT SENSE (3) NOTE: FOR LT3020 ADJUST PIN 3 IS CONNECTED TO THE ADJUST PIN, R1 AND R2 ARE EXTERNAL. FOR LT3020-1.X PIN 3 IS CONNECTED TO THE OUTPUT SENSE PIN, R1 AND R2 ARE INTERNAL. GND (4,9) ADJ (3) 25k SHDN (5) 200mV 212mV BIAS CURRENT AND REFERENCE GENERATOR FIXED VOUT 1.2V 1.5V 1.8V 20k 20k 20k 100k 130k 160k
output current and dropout voltage is typically 150mV. pin. Use the formula in Figure 1 to calculate output voltage. appear in the Typical Performance Characteristics section. Give extra consideration to the use of ceramic capacitors. but exhibit strong voltage and temperature coefficients. X5R is less expensive and is available in higher values. coefficient comparisons between Y5V and X5R material.
3020 F01
Figure 1. Adjustable Operation
shuts down the bias current/reference generator circuitry.
- Output current multiplied by the input-to-output volt-
- GND pin current multiplied by the input voltage:
current curves in the Typical Performance Characteristics.
3020 F02
1210 CASE SIZE, 10µF
3020 F03
Figure 2. Ceramic Capacitor DC Bias Characteristics Figure 3. Ceramic Capacitor Temperature Characteristics Figure 4. Noise Resulting from Tapping on a Ceramic Capacitor
exceed the maximum junction temperature rating of 125°C. 2) from the lead frame to where the die is attached. pins of the LT3020 also assist in spreading heat to the PCB. FR-4 board with one ounce copper. Table 1. Measured Thermal Resistance for DD Package Table 2. Measured Thermal Resistance for MS8 Package *Device is mounted on topside. exceed a junction temperature of 125°C.
LT3020/LT3020-1.2/ LT3020-1.5/LT3020-1.8 sn3020 3020fas The LT3020 incurs no damage if OUT is pulled below ground. If IN is left open circuit or grounded, OUT can be pulled below ground by 10V. No current flows from the pass transistor connected to OUT. However, current flows in (but is limited by) the resistor divider that sets the output voltage. Current flows from the bottom resistor in the divider and from the ADJ pin’s internal clamp through the top resistor in the divider to the external circuitry pulling OUT below ground. If IN is powered by a voltage source, OUT sources current equal to its current limit capability and the LT3020 protects itself by thermal limiting. In this case, grounding SHDN turns off the LT3020 and stops OUT from sourcing current. The LT3020 incurs no damage if the ADJ pin is pulled above or below ground by 10V. If IN is left open circuit or grounded and ADJ is pulled above ground, ADJ acts like a 25k resistor in series with a 1V clamp (one Schottky diode in series with one diode). ADJ acts like a 25k resistor in series with a Schottky diode if pulled below ground. If IN is powered by a voltage source and ADJ is pulled below its reference voltage, the LT3020 attempts to source its current limit capability at OUT. The output voltage in- creases to V IN – VDROPOUT with VDROPOUT set by whatever load current the LT3020 supports. This condition can potentially damage external circuitry powered by the LT3020 if the output voltage increases to an unregulated high voltage. If IN is powered by a voltage source and ADJ is pulled above its reference voltage, two situations can occur. If ADJ is pulled slightly above its reference voltage, the LT3020 turns off the pass transistor, no output current is sourced and the output voltage decreases to either the voltage at ADJ or less. If ADJ is pulled above its no load recovery threshold, the no load recovery circuitry turns on and attempts to sink current. OUT is actively pulled low and the output voltage clamps at a Schottky diode above ground. Please note that the behavior described above applies to the LT3020 only. If a resistor divider is con- nected under the same conditions, there will be additional V/R current. In circuits where a backup battery is required, several different input/output conditions can occur. The output voltage may be held up while the input is either pulled to ground, pulled to some intermediate voltage or is left open APPLICATIO S I FOR ATIOWU UU circuit. In the case where the input is grounded, there is less than 1µA of reverse output current. If the LT3020 IN pin is forced below the OUT pin or the OUT pin is pulled above the IN pin, input current drops to less than 10µA typically. This occurs if the LT3020 input is connected to a discharged (low voltage) battery and either a backup battery or a second regulator circuit holds up the output. The state of the SHDN pin has no effect on the reverse output current if OUT is pulled above IN. Input Capacitance and Stability The LT3020 is designed to be stable with a minimum capacitance of 2.2µF placed at the IN pin. Ceramic capaci- tors with very low ESR may be used. However, in cases where a long wire is used to connect a power supply to the input of the LT3020 (and also from the ground of the LT3020 back to the power supply ground), use of low value input capacitors combined with an output load current of 20mA or greater may result in an unstable application. This is due to the inductance of the wire forming an LC tank circuit with the input capacitor and not a result of the LT3020 being unstable. The self-inductance, or isolated inductance, of a wire is directly proportional to its length. However, the diameter of a wire does not have a major influence on its self- inductance. For example, the self inductance of a 2-AWG isolated wire with a diameter of 0.26 in. is about half the inductance of a 30-AWG wire with a diameter of 0.01 in. One foot of 30-AWG wire has 465nH of self inductance. The overall self-inductance of a wire can be reduced in two ways. One is to divide the current flowing towards the LT3020 between two parallel conductors. In this case, the farther the wires are placed apart from each other, the more inductance will be reduced, up to a 50% reduction when placed a few inches apart. Splitting the wires basi- cally connects two equal inductors in parallel. However, when placed in close proximity from each other, mutual inductance is added to the overall self inductance of the wires. The most effective way to reduce overall inductance is to place the forward and return-current conductors (the wire for the input and the wire for ground) in very close proximity. Two 30-AWG wires separated by 0.02 in. re- duce the overall self-inductance to about one-fifth of a single isolated wire.
LT3020/LT3020-1.2/ LT3020-1.5/LT3020-1.8 sn3020 3020fas APPLICATIO S I FOR ATIOWU UU If the LT3020 is powered by a battery mounted in close proximity on the same circuit board, a 2.2µF input capaci- tor is sufficient for stability. However, if the LT3020 is powered by a distant supply, use a larger value input capacitor following the guideline of roughly 1µF (in addi- tion to the 2.2µF minimum) per 8 inches of wire length. As power supply output impedance may vary, the minimum input capacitance needed to stabilize the application may also vary. Extra capacitance may also be placed directly on the output of the power supply; however, this will require an order of magnitude more capacitance as opposed to placing extra capacitance in close proximity to the LT3020. Furthermore, series resistance may be placed between the supply and the input of the LT3020 to stabilize the appli- cation; as little as 0.1Ω to 0.5Ω will suffice.
LT3020/LT3020-1.2/ LT3020-1.5/LT3020-1.8 sn3020 3020fas UPACKAGE DESCRIPTIO 8-Lead Plastic DFN (3mm × 3mm) (Reference LTC DWG # 05-08-1698) 3.00 ±0.10 (4 SIDES) NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON TOP AND BOTTOM OF PACKAGE 0.38 ± 0.10 BOTTOM VIEW—EXPOSED PAD 1.65 ± 0.10 (2 SIDES) 0.75 ±0.05 R = 0.115 TYP 2.38 ±0.10 (2 SIDES) PIN 1 TOP MARK (NOTE 6)
0.200 REF
0.00 – 0.05 (DD8) DFN 1203 0.25 ± 0.05 2.38 ±0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 1.65 ±0.05 (2 SIDES)2.15 ±0.05 0.50 BSC 0.675 ±0.05 3.5 ±0.05 PACKAGE OUTLINE 0.25 ± 0.05
0.50 BSC
LT3020/LT3020-1.2/ LT3020-1.5/LT3020-1.8 sn3020 3020fas UPACKAGE DESCRIPTIO 8-Lead Plastic MSOP (Reference LTC DWG # 05-08-1660) MSOP (MS8) 0204 0.53 ± 0.152 (.021 ± .006) SEATING PLANENOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 0.18 (.007) 0.254 (.010) 1.10 (.043) MAX 0.22 – 0.38 (.009 – .015) TYP 0.127 ± 0.076 (.005 ± .003) 0.86 (.034) REF 0.65 (.0256) BSC 0° – 6° TYP DETAIL “A” DETAIL “A” GAUGE PLANE 12 3 4 4.90 ± 0.152 (.193 ± .006) 8 7 6 5 3.00 ± 0.102 (.118 ± .004) (NOTE 3) 3.00 ± 0.102 (.118 ± .004) (NOTE 4) 0.52 (.0205) REF 5.23 (.206) MIN 3.20 – 3.45 (.126 – .136) 0.889 ± 0.127 (.035 ± .005) RECOMMENDED SOLDER PAD LAYOUT 0.42 ± 0.038 (.0165 ± .0015) TYP 0.65 (.0256) BSC Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LT3020/LT3020-1.2/ LT3020-1.5/LT3020-1.8 sn3020 3020fas LT/TP 0604 1K REV A • PRINTED IN USA © LINEAR TECHNOLOGY CORPORA TION 2004 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com PART NUMBER DESCRIPTION COMMENTS LT1121/LT1121HV 150mA, Micropower LDOs V IN: 4.2V to 30V/36V, VOUT(MIN) = 3.75V, VDO = 0.42V, IQ = 30µA, ISD = 16µA, Reverse-Battery Protection, SOT-223, S8, Z Packages LT1129 700mA, Micropower LDO V IN: 4.2V to 30V, VOUT(MIN) = 3.75V, VDO = 0.4V, IQ = 50µA, ISD = 16µA, DD, SOT-223, S8, TO220-5, TSSOP20 Packages LT1761 100mA, Low Noise Micropower LDO V IN: 1.8V to 20V, VOUT(MIN) = 1.22V, VDO = 0.3V, IQ = 20µA, ISD < 1µA, Low Noise: < 20 µVRMS, Stable with 1µF Ceramic Capacitor, ThinSOT Package LT1762 150mA, Low Noise Micropower LDO V IN: 1.8V to 20V, VOUT(MIN) = 1.22V, VDO = 0.3V, IQ = 25µA, ISD < 1µA, Low Noise: <20µVRMS, MS8 Package LT1763 500mA, Low Noise Micropower LDO V IN: 1.8V to 20V, VOUT(MIN) = 1.22V, VDO = 0.3V, IQ = 30µA, ISD < 1µA, Low Noise: < 20µVRMS, S8 Package LT1764/LT1764A 3A, Low Noise, Fast Transient Response LDOs V IN: 2.7V to 20V, VOUT(MIN) = 1.21V, VDO = 0.34V, IQ = 1mA, ISD < 1µA, Low Noise: <40µVRMS, “A” Version Stable with Ceramic Capacitors, DD, TO220-5 Packages LTC1844 150mA, Low Noise, Micropower VLDO V IN: 1.6V to 6.5V, VOUT(MIN) = 1.25V, VDO = 0.09V, IQ = 35µA, ISD < 1µA, Low Noise: < 30µVRMS, ThinSOT Package LT1962 300mA, Low Noise Micropower LDO V IN: 1.8V to 20V, VOUT(MIN) = 1.22V, VDO = 0.27V, IQ = 30µA, ISD < 1µA, Low Noise: < 20µVRMS, MS8 Package LT1963/LT1963A 1.5A, Low Noise, Fast Transient Response LDOs V IN: 2.1V to 20V, VOUT(MIN) = 1.21V, VDO = 0.34V, IQ = 1mA, ISD < 1µA, Low Noise: < 40µVRMS, “A” Version Stable with Ceramic Capacitors, DD, TO220-5, SOT223, S8 Packages LT1964 200mA, Low Noise Micropower, Negative LDO V IN: –2.2V to –20V, V OUT(MIN) = 1.21V, VDO = 0.34V, IQ = 30µA, ISD = 3µA, Low Noise: <30µVRMS, Stable with Ceramic Capacitors, ThinSOT Package LT3010 50mA, High Voltage, Micropower LDO V IN: 3V to 80V, VOUT(MIN) = 1.2V, VDO = 0.3V, IQ = 30µA, ISD < 1µA, Low Noise: <100µVRMS, Stable with 1µF Output Capacitor, Exposed LT3150 Low V IN, Fast Transient Response, VLDO Controller V IN: 1.1V to 10V, VOUT(MIN) = 1.23V, VDO = Set by External MOSFET RDS(ON), 1.4MHz Boost Converter Generates Gate Drive, SSOP16 Package RELATED PARTS