L7980.fm
Document overview
- Manufacturer or author: STMICROELECTRONICS
- PDF pages: 43
Technical content
Datasheet sections
- 1 Pin settings
- 1.1 Pin connection
- 1.2 Pin description
- 2 Maximum ratings
- 3 Thermal data
- 4 Electrical characteristics
- 5 Functional description
- 5.1 Oscillator and synchronization
- 5.2 Soft-start
- 5.3 Error amplifier and compensation
- 5.4 Overcurrent protection
- 5.5 Enable function
- 5.6 Hysteretic thermal shutdown
- 6 Application informations
- 6.1 Input capacitor selection
- 6.2 Inductor selection
- 6.3 Output capacitor selection
- 6.4 Compensation network
- 6.4.1 Type III compensation network
- 6.4.2 Type II compensation network
- 6.5 Thermal considerations
- 6.6 Layout considerations
- 6.7 Application circuit
- 7 Application ideas
- 7.1 Positive buck-boost
- 7.2 Inverting buck-boost
Features
- 2 A DC output current
- 4.5 V to 28 V input voltage
- Output voltage adjustable from 0.6 V
- 250 kHz switching frequency, programmable up to 1 MHz
- Internal soft-start and enable
- Low dropout operation: 100% duty cycle
- Voltage feed-forward
- Zero load current operation
- Overcurrent and thermal protection
- VFQFPN 3 x 3 - 8L and HSOP8 package
Applications
- Consumer: – STB, DVD, DVD recorder, car audio, LCD TV and monitors
- Industrial: – PLD, PLA, FPGA, chargers
- Networking: XDSL, modems, DC-DC modules
- Computer: – Optical storage, hard disk drive, printers, audio/graphic cards
- LED driving
Description
The L7980 device is a step-down switching regulator with a 2.5 A (minimum) current limited embedded Power MOSFET, so it is able to deliver up to 2 A current to the load depending on the application conditions. The input voltage can range from 4.5 V to 28 V, while the output voltage can be set starting from
0.6 V to V
IN . Requiring a minimum set of external components, the device includes an internal 250 kHz switching frequency oscillator that can be externally adjusted up to 1 MHz. The QFN and the HSOP packages with exposed pad allow reducing the R thJA down to 60 °C/W and 40 °C/W respectively. Figure 1. Application circuit
1 Pin settings
1.1 Pin connection
Figure 2. Pin connection (top view)
1.2 Pin description
Table 1. Pin description
1 OUT Regulator output
2 SYNCH
powers turn on have a phase shift of half a period. 1.2 V the device is ON and with EN is lower than 0.3 V the device is OFF.
4 COMP Error amplifier output to be used for loop fre quency compensation
external resistor divider is required from Vout to the FB pin. works at its free-running frequency of 250 kHz.
7 GND Ground
2 Maximum ratings
3 Thermal data
Table 2. Absolute maximum ratings Table 3. Thermal data
- Package mounted on demonstration board.
4 Electrical characteristics
TJ = 25 °C, V CC = 12 V, unless otherwise specified. Table 4. Electrical characteristics
- Specification referred to T J from -40 to +125 °C. Specification in the -40 to + 125 °C temperature range are assured by
design, characterization and statistical correlatio n. Table 4. Electrical characteristics (continued)
5 Functional description
off time of the power switch.
- A fully integrated oscillator that provides sawtooth to modulate the duty cycle and the synchronization signal. Its switching frequency can be adjusted by an external resistor. The voltage and frequency feed forward are implemented.
- The soft-start circuitry to limit inrush current during the start-up phase.
- The voltage mode error amplifier
- The pulse width modulator and the relative logic circuitry necessary to drive the internal power switch.
- The high-side driver for embedded P-channel Power MOSFET switch.
- The peak current limit sensing block, to handle overload and short-circuit conditions.
- A voltage regulator and internal reference. It supplies internal circuitry and provides a fixed internal reference.
- A voltage monitor circuitry (UVLO) that checks the input and internal voltages.
- A thermal shutdown block, to prevent thermal runaway.
Figure 3. Block diagram
5.1 Oscillator and synchronization
as shown in Figure 6 by external resistor connected to ground. according to the input voltage change (see Figure 5 .a). flowing through the input capacitor (see the L5988D datasheet). Figure 4. Oscillator circuit block diagram Figure 5 .c). This changing has to be taken into account when the loop stability is studied. truncation of sawtooth, due to the external synchronization.
5.2 Soft-start
avoids inrush current surge and makes the output voltage increases monothonically. Figure 7. Soft-start scheme
5.3 Error amplifier and compensation
mode operational amplifier so with high DC gain and low output impedance. compensation network selection).
5.4 Overcurrent protection
MOSFET, the current sensing is disabled during the initial phase of the conduction time. “masking time” or “blanking time”. The masking time is about 200 ns.
- Output voltage in regulation . When the overcurrent is sensed, the Power MOSFET is
reference begins ramping (see Figure 8 .a).
- Soft-start phase . If the overcurrent limit is reached the Power MOSFET is turned off
Table 5. Uncompensated error amplifier characteristics
Functional description L7980
5.5 Enable function
The enable feature allows to put in standby mode the device. With the EN pin lower than 0.3 V the device is disabled and the power consumption is reduced to less than 30 µA. With the EN pin lower than 1.2 V, the device is enabled. If the EN pin is left floating, an internal pull down ensures that the voltage at the pin reaches the inhibit threshold and the device is disabled. The pin is also V CC compatible.
5.6 Hysteretic thermal shutdown
The thermal shutdown block generates a signal that turns off the power stage if the junction temperature goes above 150 °C. Once the junction temperature goes back to about 130 °C, the device restarts in normal operation. The sensing element is very close to the PDMOS area, so ensuring an accurate and fast temperature detection.
6 Application informations
6.1 Input capacitor selection
The capacitor connected to the input has to be capable to support the maximum input operating voltage and the maximum RMS input current required by the device. The input capacitor is subject to a pulsed current, the RMS value of which is dissipated over its ESR, affecting the overall system efficiency. So the input capacitor must have an RMS current rating higher than the maximum RMS input current and an ESR value compliant with the expected efficiency. The maximum RMS input current flowing through the capacitor can be calculated as: Equation 3 Where I O is the maximum DC output current, D is the duty cycle, η is the efficiency. Considering η = 1, this function has a maximum at D = 0.5 and it is equal to I O/2. In a specific application the range of possible duty cycles has to be considered in order to find out the maximum RMS input current. The maximum and minimum duty cycles can be calculated as: Equation 4 and Equation 5 Where V F is the forward voltage on the freewheeling diode and VSW is voltage drop across the internal PDMOS. The peak to peak voltage across the input capacitor can be calculated as: Equation 6 where ESR is the equivalent series resistance of the capacitor. IRMS IO D 2 D 2⋅ DMAX VOUT VF+ DMIN VOUT VF+ VPP IO η- - - - – D D
neglecting the small ESR of ceramic capacitors.
6.2 Inductor selection
minimum inductance value in order to have the expected current ripple has to be selected. The rule to fix the current ripple value is to have a ripple at 20% - 40% of the output current. (see Section 6.1 to calculate minimum duty). Table 6. Input MLCC capacitors
SW is the switching frequency, 1 / (T ON + T OFF ). inductance value to have ΔIL = 30% of I O is about 28 µH. output current that can be delivered, without reaching the current limit. Table 7 some inductor part numbers are listed.
6.3 Output capacitor selection
Table 7. Inductors
1 D MIN –
drop dominates and the voltage ripple is 33 mV . have to be chosen in order to sustain the load transient. In Table 8 some capacitor series are listed. Table 8. Output capacitors
6.4 Compensation network
will be considered as ideal, that is, its bandwidth is much larger than the system one. and how to keep it constant in spite of the external synchronization). Figure 9. The error amplifier, the PWM modulation and the LC output filter
Application informations L7980 The transfer function on the LC filter is given by: Equation 16 where: Equation 17 Equation 18 As seen in Section 5.3 on page 12 two different kind of network can compensate the loop. In the two following paragraph the guidelines to select the Type II and Type III compensation network are illustrated.
6.4.1 Type III compensation network
The methodology to stabilize the loop consists of placing two zeros to compensate the effect of the LC double pole, so increasing phase margin; then to place one pole in the origin to minimize the dc error on regulated output voltage; finally to place other poles far away the zero dB frequency. If the equivalent series resistance (ESR) of the output capacitor introduces a zero with a frequency higher than the desired bandwidth (that is: 2 π ∗ ESR ∗ C OUT < 1 / BW), the type III compensation network is needed. Multi layer ceramic capacitors (MLCC) have very low ESR (< 1 mΩ ), with very high frequency zero, so type III network is adopted to compensate the loop. In Figure 10 the type III compensation network is shown. This network introduces two zeros (f Z1 , f Z2 ) and three poles (f P0 , f P1 , f P2 ). They are expressed as: Equation 19 Equation 20 GLC s( ) 1 s 1 s 2 + + fLC 2π L C OUT ⋅ 1 ESR ROUT Q ROUT L C OUT ROUT ESR +( ) ⋅ ⋅ ⋅ VOUT IOUT fZ1 fP0 0= fP1 2π R4 C4 C5⋅
Application informations L7980 3. Calculate C 4 by placing the zero at 50% of the output filter double pole frequency (f LC ): Equation 22 4. Calculate C 5 by placing the second pole at four times the system bandwidth (BW): Equation 23 5. Set also the first pole at four times the system bandwidth and also the second zero at the output filter double pole: Equation 24 The suggested maximum system bandwidth is equals to the switching frequency divided by 3.5 (F SW /3.5), anyway lower than 100 kHz if the F SW is set higher than 500 kHz. For example with V OUT = 5 V, V IN = 24 V, I O = 2 A, L = 27 µH, C OUT = 22 µF, ESR < 1 m Ω , the type III compensation network is: Equation 25
4 BW ⋅
R1 4.99k Ω= R2 680 Ω= R3 150 Ω= R4 3.3k Ω= C3 4.7nF = C4 22nF = C5 220pF =, , , , , ,
54 kHz and the phase margin is 50°. Figure 12. Open loop gain bode diagram with ceramic output capacitor
6.4.2 Type II compensation network
The guidelines for positioning the poles and the zeroes and for calculating the component values can be summarized as follow: 1. Choose a value for R 1, usually between 1 k Ω and 5 k Ω , in order to have values of C4 and C5 not comparable with parasitic capacitance of the board. 2. Choose a gain (R 4 / R1) in order to have the required bandwidth (BW), that means: Equation 27 Where f ESR is the ESR zero: Equation 28 and V S is the saw-tooth amplitude. The voltage feed forward keeps the ratio VS/VIN constant. 3. Calculate C 4 by placing the zero one decade below the output filter double pole: Equation 29 4. Then calculate C 3 in order to place the second pole at four times the system bandwidth (BW): Equation 30 For example with V OUT = 5 V, V IN = 24 V, I O = 2 A, L = 27 µH, C OUT = 330 µF, ESR = 50 m Ω, the type II compensation network is: Equation 31 In Figure 15 is shown the module and phase of the open loop gain. The bandwidth is about 24 kHz and the phase margin is 48°. fESR fLC 2 BW fESR VS VIN fESR R1 1.1k Ω= R2 150 Ω= R4 6.8k Ω= C4 82nF = C5 82pF =, , , ,
Figure 15. Open loop gain bode diagram with electro lytic/tantalum output capacitor
6.5 Thermal considerations
The thermal design is important to prevent the thermal shutdown of the device if junction temperature goes above 150 °C. The three different sources of losses within the device are: a) Conduction losses due to the not negligible R DSon of the power switch; these are equal to: Equation 32 Where D is the duty cycle of the application and the maximum R DSon overtemperature is 300 m Ω . Note that the duty cycle is theoretically given by the ratio between V OUT and V IN , but actually it is quite higher to compensate the losses of the regulator. So the conduction losses increases compared with the ideal case. b) Switching losses due to Power MOSFET turn ON and OFF; these can be calculated as: Equation 33 Where T RISE and TFALL are the overlap times of the voltage across the power switch (V DS ) and the current flowing into it during turn ON and turn OFF phases, as shown in Figure 16 . TSW is the equivalent switching time. For this device the typical value for the equivalent switching time is 30 ns. c) Quiescent current losses, calculated as: Equation 34 where I Q is the quiescent current (I Q = 2.4 mA). The junction temperature T J can be calculated as: Equation 35 Where T A is the ambient temperature and PTOT is the sum of the power losses just seen. RthJA is the equivalent thermal resistance junction to ambient of the device; it can be calculated as the parallel of many paths of heat conduction from the junction to the ambient. For this device the path through the exposed pad is the one conducting the largest amount of heat. The Rth JA measured on the demonstration board described in the following paragraph is about 60 °C/W for the VFQFPN package and about 40 °C/W for the HSOP package. PON RDSON IOUT ( ) 2 D⋅ ⋅ = PSW VIN IOUT TRISE TFALL +( ) PQ VIN IQ⋅= TJ TA Rth JA PTOT ⋅+=
Figure 16. Switching losses
6.6 Layout considerations
close as possible to the input voltage pin of the device. of the converter allowing high power conversion.
In Figure 17 a layout example is shown. Figure 17. Layout example
6.7 Application circuit
In Figure 18 the demonstration board application circuit is shown. Figure 18. Demonstration board application circuit (rev 1.0) Table 9. Component list (rev 1.0)
7 Application ideas
7.1 Positive buck-boost
The L7980 device can implement the step-up/down converter with a positive output voltage. Figure 33. Positive buck-boost regulator output current for the buck boost topology can be calculated from Equation 38 . SW is the average current in the embedded Power MOSFET in the on time.
39 , must be lower than the minimum current limit (3.7 A). input voltage from 4.5 V to 28 V. Figure 34. Maximum output current according to max DC switch current (2.0 A):
7.2 Inverting buck-boost
to the standard buck topology. 38 , where the duty cycle is given by Equation 42 . Figure 35. Inverting buck-boost regulator and GND (28 V). Thus if the output is -5 V the input voltage can range from 4.5 V to 23 V. MOSFET are taken into account.
Figure 36. Maximum output current according to max DC switch current (2.0 A):
8 Package information
specifications, grade definitions and product status are available at: www.st.com. Figure 37. VFQFPN8 (3 x 3 x 1.08 mm) package outline
Table 10. VFQFPN8 (3 x 3 x 1.08 mm) package mechanical data
Figure 38. HSOP8 package outline Table 11. HSOP8 mechanical data
9 Order codes
Table 12. Order codes
Table 13. Document revision history 19-Nov-2008 1 Initial release. 13-Dec-2010 4 Updated: Section 6.5 on page 27. Updated Table 5 on page 12 (added header). IN ”and “V OUT ” with values). Updated cross-references throughout document. Minor modifications throughout document. related to the VFQFPN8 in tube). Minor modifications throughout document.