Datasheet - L6981 - 38 V, 1.5 A synchronous step-down converter with 20 µA quiescent current
Document overview
- Manufacturer or author: STMICROELECTRONICS
- PDF pages: 52
Technical content
Datasheet sections
- 1 Diagram
- 2 Pin configuration
- 3 Typical application circuit
- 4 Absolute maximum ratings
- 5 Electrical characteristics
- 6 Functional description
- 6.1 Enable
- 6.2 Soft-start
- 6.3 Undervoltage lockout
- 6.4 Light-load operation
- 6.4.1 Low consumption mode (LCM)
- 6.4.2 Low noise mode (LNM)
- 6.4.3 Efficiency for Low consumption mode and Low noise mode part number
- 6.4.4 Load regulation for low consumption mode and low noise mode part number
- 6.5 Switch-over feature (fixed VOUT part numbers only)
- 6.6 Output overvoltage protection
- 6.6.1 Low consumption mode part numbers
- 6.6.2 Low noise mode part numbers
- 6.7 Overcurrent protection
- 6.8 Thermal shutdown
- 7 Closing the loop
- 7.1 GCO(s) control to output transfer function
- 7.2 Error amplifier compensation network
- 7.3 Voltage divider (Adjustable part number)
- 8 Design of the power components
- 8.1 Programmable power up threshold
- 8.2 External synchronization (only available for Low Noise Mode)
- 8.3 Output voltage adjustment (Adjustable part number)
- 8.4 Design of the power components
- 8.4.1 Input capacitor selection
- 8.4.2 Inductor selection
- 8.4.3 Output capacitor selection
- 9 Application board
- 10 Efficiency curves
Features
- 3.5 V to 38 V operating input voltage
- Output voltage from 0.85 V to V IN
- 3.3 / 5 V fixed output voltage versions
- 1.5 A DC output current
- 20 μA operating quiescent current
- Internal compensation network
- Two different versions: LCM for high efficiency at light-loads and LNM for noise sensitive applications
- 2 μA shutdown current
- Internal soft-start
- High voltage V IN compatible Enable
- Output overvoltage protection
- Output voltage sequencing
- Thermal protection
- Synchronization to external clock for LNM devices
- SO8 package
Applications
- Designed for 24 V buses industrial power systems
- 24 V battery powered equipment
- Decentralized intelligent nodes
- Sensors and always-on applications
- Low noise applications
- Smart meters
- Robot cleaner
Description
The L6981 is an easy to use synchronous monolithic step-down regulator capable of delivering up to 1.5 A DC to the load. The wide input voltage range makes the device suitable for a broad range of applications. The L6981 is based on a peak current mode architecture and is packaged in an SO8 with internal compensation, thus minimizing design complexity and size. The L6981 is available both in low consumption mode (LCM) and low noise mode (LNM) versions. LCM maximizes the efficiency at light-load with controlled output voltage ripple so the device is suitable for battery-powered applications. LNM makes the switching frequency constant and minimizes the output voltage ripple for light-load operations, meeting the specification for low noise sensitive applications. The EN pin provides output enable/disable functionality. The typical shutdown current is 2 µA when disabled. As soon as the EN pin is pulled up the device is enabled and the internal 1.3 ms soft-start takes place. Pulse-by-pulse current sensing on both power elements implements an effective constant current protection and thermal shutdown prevents thermal run-away. SO 8L Maturity status link L6981 38 V, 1.5 A synchronous step-down converter with 20 µA quiescent current L6981 Datasheet DS13554 - Rev 3 - December 2022 For further information contact your local STMicroelectronics sales office.
1 Diagram
Figure 1. Block diagram (*) Synchronization is allowed for LNM versions only.
2 Pin configuration
Figure 2. Pin connection (top view) (*) Synchronization is allowed for LNM versions only. Table 1. Pin description
1 SW Switching node
2 BOOT
(≥ 1 µF) to filter internal voltage reference.
4 VOUT/FB
5 EN/CLKIN
6 AGND Analog ground
7 VIN DC input voltage
8 PGND Power ground
3 Typical application circuit
Figure 3. Basic application (adjustable version) (*) Synchronization is allowed for LNM versions only. Figure 4. Basic application (fixed VOUT versions) (*) Synchronization is allowed for LNM versions only. Table 2. Typical application components
4 Absolute maximum ratings
Stressing the device above the ratings listed in the table below may cause permanent damage to the device. Table 3. Absolute maximum ratings Note: All values are referred to AGND unless otherwise specified. Table 4. ESD performance Table 5. Thermal data
5 Electrical characteristics
Table 6. Electrical characteristics TJ = 25 °C, VIN = 24 V unless otherwise specified.
Electrical characteristics
Symbol Parameter Test Conditions Min. Typ. Max. Unit VFB Voltage feedback Fixed 3.3 V version TJ = -40 °C ≤ TJ ≤ 125 °C (3) 3.284 3.3 3.346 V Fixed 5.0 V version TJ = 25 °C 4.955 5.0 5.045 V Fixed 5.0 V version TJ = -40 °C ≤ TJ ≤ 125 °C Overvoltage protection VOVP Overvoltage trip (VOVP/VREF) 115 120 125 % VOVP_HYST Overvoltage Hysteresis 1 2 6 % Synchronization (LNM versions only) fCLKIN (4) Synchronization range 200 500 KHz VCLKIN_TH (4) Amplitude of synchronization clock 2.3 V VCLKIN_T (4) Synchronization pulse ON and OFF time 2.3 ≤ VCLKIN_TH ≤ 2.5 V 60 ns Synchronization pulse ON and OFF time VCLKIN_TH > 2.5 V 20 ns Thermal Shutdown TSHDWN (5) Thermal shutdown temperature 165 °C THYS (5) Thermal shutdown hysteresis 30 °C 1. Parameter tested in the static condition during testing phase. The parameter value may change over a dynamic application condition. 2. LCM version. 3. Specifications in the - 40 to 125 °C temperature range are assured by characterization and statistical correlation. 4. LNM version. 5. Not tested in production. L6981
6 Functional description
mode) to increase the efficiency at light-load.
- Embedded power elements
- The ramp for the slope compensation to avoid subharmonic instability
- A transconductance error amplifier with integrated compensation network
- The high-side current sense amplifier to sense the inductor current
- A “Pulse Width Modulator” (PWM) comparator and the driving circuitry of the embedded power elements
- The soft-start block ramps up the reference voltage on error amplifier, thus decreasing the inrush current at power-up. The EN pin inhibits the device when driven low
- The EN/CLK pin section, which for LNM versions, allows synchronizing the device to an external clock generator
- The pulse-by-pulse high-side / low-side switch current sensing to implement the constant current protection
- A circuit to implement the thermal protection function
- The OVP circuitry to discharge the output capacitor in case of overvoltage event.
6.1 Enable
The EN pin is a digital input that turns the device on or off.
- The Wake-Up threshold, V WAKE_UP = 0.5 V (see Table 6)
- The Start-Up threshold, V EN = 1.2 V (see Table 6)
The following image shows the device behavior. Figure 5. Power up/down behavior increasing the current consumption.
Once the voltage becomes lower than VEN,FALLING, the device interrupts the switching activities. reducing the current consumption. Please refer to Table 6 for the reported thresholds.
6.2 Soft-start
The soft-start (SS) limits the inrush current surge and makes the output voltage increase monotonically. coming directly from the band gap cell. Figure 6. Soft-start procedure
- EN pin rising over VEN threshold. Please refer to Table 6.
Figure 7. Soft-start phase with IOUT = 1.25 A
6.3 Undervoltage lockout
UVLO lasts more than 10 μs, the internal logic resets the device by turning off both LS and HS. After the reset, if the EN pin is still high, the device repeats the soft-start procedure.
6.4 Light-load operation
- Low consumption mode (LCM).
Please refer to Table 11 to select the part number with the preferred light-load strategy.
6.4.1 Low consumption mode (LCM)
The LCM maximizes the efficiency at light-load. Where VFB, LCM is 1.8% (typ.) higher than VFB.
- The peak inductor current required is lower than I SKIP.
- The voltage on the FB pin is higher than V FB, LCM.
6.4.2 Low noise mode (LNM)
Figure 14. Low noise mode operation at zero load
6.4.3 Efficiency for Low consumption mode and Low noise mode part number
and LCM part numbers. The graph reports also the same efficiency at the medium / high load. Figure 15. Light-load efficiency for low consumption mode and low noise mode - linear scale. VIN = 24 V; Figure 16. Light-load efficiency for low consumption mode and low noise mode - log scale. VIN = 24 V;
6.4.4 Load regulation for low consumption mode and low noise mode part number
defined in the Low consumption mode (LCM) paragraph, the behavior of the different part numbers is the same. Figure 17. Load regulation for LCM and LNM. VIN = 24 V; VOUT = 5 V; FSW = 400 KHz - linear scale Figure 18. Load regulation for LCM and LNM part numbers. VIN = 24 V; VOUT = 5 V; FSW = 400 KHz - log
6.5 Switch-over feature (fixed VOUT part numbers only)
The Switch-Over maximizes the efficiency at light-load that is crucial for LCM applications. internal circuitry are supplied from VOUT pin.
6.6 Output overvoltage protection
with the load dynamic request. Consequently, the output voltage regulation would be affected.
6.6.1 Low consumption mode part numbers
limitation is reached, in order to discharge the output capacitor. The following graph shows the LCM part number behavior during an OVP event. Figure 19. OVP event low consumption mode part number
6.6.2 Low noise mode part numbers
The following graph shows the LNM part number behavior during an OVP event. Figure 20. OVP event low noise mode part numbers sinking capability of the device (highlighted in green in Figure 20). maximum sinking capability above described (highlighted in blue in Figure 20).
6.7 Overcurrent protection
current (please refer to Table 6) in an overcurrent condition. the low-side sensing “valley”. The L6981 device assures an effective overcurrent protection sensing the current flowing in both power elements. limits assure the effectiveness of the overcurrent protection even in extreme duty cycle conditions.
the high-side turn-on, so the device can skip pulses decreasing the switching frequency. Figure 21. Overcurrent protection behavior and TMASKHS is the masking time of the high-side switch. and so the peak current protection limits the switch current.
Figure 22 shows the L6981 soft-start procedure with VOUT shorted to GND. Figure 22. Soft-start procedure with VOUT shorted to GND Figure 23 shows the L6981 over current protection with a persistent short-circuit between VOUT and GND. Figure 23. Over current procedure with persistent short circuit between VOUT and GND
6.8 Thermal shutdown
and OFF too fast. After a thermal protection event has expired, the L6981 restarts with a new soft-start.
7 Closing the loop
The following image shows the typical compensation network required to stabilize the system. Figure 24. Block diagram of the loop
7.1 GCO(s) control to output transfer function
amplifier that introduces a double pole at one half of the switching frequency. Where ISLOPE is equal to 1 A.
implements the slope compensation to avoid sub-harmonic oscillations at duty cycle over 50 %.
7.2 Error amplifier compensation network
The following figure shows the typical compensation network required to stabilize the system. Figure 25. Trans-conductance embedded error amplifier
7.3 Voltage divider (Adjustable part number)
Figure 26. Leading network example (*) Synchronization is allowed for LNM versions only.
8 Design of the power components
8.1 Programmable power up threshold
Figure 27. Leading network example (*) Synchronization is allowed only for LNM versions.
8.2 External synchronization (only available for Low Noise Mode)
The device allows a direct connection between a clock source and the EN/CLKIN pin. Figure 28. External synchronization. Direct connection (*) Synchronization is allowed only for LNM versions. value of the applied signal.
turns off when the average of the signal should be lower than VEN falling (refer to Table 6). The device allows also the AC coupling. Figure 29. External synchronization. AC coupling (*) Synchronization is allowed only for LNM versions. to the EN/CLKIN pin and described in the "Programmable power up threshold" section. keeping the selected power-up and down thresholds. Table 7. External synchronization AC coupling suggested operation range The minimum amplitude for the external clock signal is, for both configurations, equal to 2.3 V. capacitor equal to 1 nF is a correct choice.
8.3 Output voltage adjustment (Adjustable part number)
Figure 30. Application circuit (*) Synchronization is allowed only for LNM versions.
8.4 Design of the power components
8.4.1 Input capacitor selection
The input capacitor voltage rating must be higher than the maximum input operating voltage of the application.
In the following table, some suitable capacitor part numbers are listed. Table 8. Input capacitors
8.4.2 Inductor selection
8.4.3 Output capacitor selection
output voltage ripple, which depends on the capacitor value and the equivalent resistive component (ESR).
As the compensation network is internal, the output capacitor should be selected in order to have a proper phase margin and then a stable control loop. A good rule to obtain a proper dimensioning for the minimum amount of the output capacitor is to set the target system bandwidth equal to FSW/10. The following equation takes into account the precedent consideration: C O U T , BW , m i n = 4.02 F SW 10 ∙ V OU T (42) The maximum amount of the output capacitor is given by: C O U T , BW , M A X = 0.48 ∙ 10 − 3 V OU T (43) L6981 Design of the power components DS13554 - Rev 3 page 28/52
9 Application board
Figure 31. Evaluation board schematic
0 Ohm
The additional input filter (C11, L3, C12, L4, C14 and C10) limits the conducted emission on the power supply.
Table 9. Bill of material
10 Efficiency curves
- COUT: – 1 x GRJ32EC71E226KE11 22 µF 16 V (Murata) – 1 x C3216X7R1H106K160AC 10 µF 50 V (TDK)
- Inductor: – MSS1038T-333ML (Coilcraft)
- C8: – 10 pF
Figure 34. Efficiency VIN = 24 V; VOUT = 5 V; FSW = 0.4 MHz Figure 35. Efficiency VIN = 24 V; VOUT = 5 V; FSW = 0.4 MHz (log scale)
11 Thermal dissipation
The thermal design is important in order to prevent thermal shutdown of the device if junction temperature goes above 165°C. The three different sources of losses within the device are:
- Conduction losses due to the ON resistance of the high-side switch (R DSON_HS) and low-side switch (RDSON_LS); these are equal to: P C O N D = R D SO N _ HS ∙ I O UT 2 ∙ D + R DSON _ L S ∙ I OUT 2 ∙ 1 − D (44) Where D is the duty cycle of the selected application and is given by: D = V OUT + R DSON _ LS + D CRl ∙ I O UT V I N − R DSON H S − R DSON _ LS ∙ I OUT (45) In order to obtain a more accurate estimation it is necessary to keep in mind that the amount of resistance of the internal power MOSFET increases with the temperature. For this reason, the value of RDSONHS and RDSONLS, should be increased from the typical of a factor equal to 20%.
- Switching losses due to high-side Power MOSFET turn ON and OFF; these can be calculated as: P SW = V I N ∙ I OU T ∙ T RI SE + T F A LL
2 F SW = V I N ∙ I OU T ∙ T SW ∙ F SW (46)
Where TRISE and TFALL are the overlap times of the voltage across the high-side power switch (VDS) and the current flowing into it during turn ON and turn OFF phases, as shown in Figure 46. TSW is the equivalent switching time. For this device the typical value for the equivalent switching time is 30 ns.
- Quiescent current losses, calculated as: P Q = V I N ∙ I Q , M A X (47) The quiescent current for constant current operation is equal to 3 [mA]: The power losses are given by: P L OS S = P CO ND + P SW + P Q (48) The junction temperature TJ can be calculated as: T J = T A + R t ℎ J A ∙ P L OS S (49) Where TA is the ambient temperature. RthJA is the equivalent thermal resistance junction to ambient of the device; it can be calculated as the parallel of many paths of heat conduction from the junction to the ambient. For this device the path through the exposed pad is the one conducting the largest amount of heat. The RthJA measured on the demonstration board described in the following section is about 65 °C/W. L6981 Thermal dissipation DS13554 - Rev 3 page 38/52
Figure 46. Switching losses stationary application condition.
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. L6981
Package information
DS13554 - Rev 3 page 40/52
12.1 SO 8L package information
Figure 47. SO 8L package outline
Table 10. SO 8L mechanical data Figure 48. SO 8L recommended footprint
12.2 SO 8L packing information
Figure 49. SO 8L tape outline
Figure 50. SO 8L reel outline
Table 11. Order codes
Ordering information
DS13554 - Rev 3 page 45/52
Revision history
Table 12. Document revision history 15-Jan-2020 1 First release. Updated title and added features on the cover page.
Contents
DS13554 - Rev 3 page 48/52
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